CMOS Operational Transconductance Amplifier Research Articles

A Survey of Ultra-Low-Power Amplifiers for Internet of Things Nodes

This paper investigates CMOS operational transconductance amplifier (OTA) design methodologies suitable for Internet of Things nodes. The use of MOS transistors in the subthreshold of the body terminal for signal input or bias, as well as newer inverter- and digital-based techniques, is considered. Solutions from the authors’ work are utilized as main case examples. State-of-the-art ultra-low-power OTAs are then thoroughly compared using a data-driven approach. According to the findings, digital- and inverter-based solutions have the lowest area occupation and superior small-signal performance but are inherently susceptible to process, supply, and temperature (PVT) variations. The only “analog” approach suitable for a sub-0.6 V supply is body driving in conjunction with subthreshold bias. It offers competitive large-signal performance and, more importantly, is less sensitive to PVT variations at the expense of silicon area.

On the exact mid-band gain of the CMOS OTA with low-voltage-cascode-current-mirror

This article presents an exact mid-band gain-expression for the CMOS operational-transconductance-amplifier (OTA) with low-voltage-cascode-current-mirror (LVCCM) load. Its small-signal analysis is not available in any CMOS text-book or other published sources/articles. A simplified and innovative technique is employed in performing this analysis with an in depth tutorial flavor. It shows that the derived mid-band gain of the CMOS OTA with LVCCM load is significantly more accurate than that obtained using the highly approximate classical gain-expression of the OTA employing a standard cascode-current-mirror equivalence which may be used in textbooks and other articles. Circuit simulations employing the 180-nm and 65-nm TSMC CMOS process technologies has been performed to indicate the progressively higher accuracy of the derived exact gain-expression for the LVCCM loaded OTA with technology scaling. This new analysis indicates an additional degree of freedom in tuning the gain of the OTA with LVCCM load using an additional transconductance parameter, gm5,6 of (M5, M6). A simplified expression is also deduced which provides an improvement over the classical approximate expression, due to the additional design insight and accuracy provided by this additional parameter while still being amenable to first order gain evaluation in a simplified way. The presented analysis is new and has not been reported before in open literature in any form.

Resistorless First-Order Universal Filter Structures Employing OTAs with Independent Controllability of Gain and Pole Frequency

This communication presents two new first order universal active filter configurations employing operational transconductance amplifiers (OTA) and use grounded capacitor which is prominently suitable for integrated chip (IC) fabrication. One of the proposed topologies provides voltage mode (VM) and transconductance mode (TCM) of operations while the other circuit provides current mode (CM) in addition with transresistance mode (TRM) filter functions. All three first order filter functions namely low pass filter (LPF), high pass filter (HPF) and all pass filter (APF) are configurable with appropriate choice(s) of input voltage/current signals. An equal transconductor condition (which can be easily achieved) is required for the realization of APF functions. The proposed filter configurations possess high input impedance and high output impedance and also offer independent electronic tunability of pole frequency/cut-off frequency. The gain of filters realized in VM, TCM and TRM has independent electronic tunability feature and can be adjusted through transconductor. For the usability of proposed filters, multi-phase sinusoidal oscillator has also been demonstrated. To assure the workability of the proposed filter structures, PSPICE simulations with CMOS OTA implemented in 0.18 µm TSMC technology parameters has been used. Various simulation results including Monte-Carlo simulations, process corner analysis, total harmonic distortions (%THD) and temperature analysis have also been appended. Experimental results employing off-the-shelf IC LM13700 type OTAs have also been included to verify the theoretical propositions of first order universal filters and multiphase sinusoidal oscillators.

Retraction Note: Design of three stage cascaded low power CMOS operational trans conductance amplifier (OTA) for ECG applications

Retraction Note: Design of three stage cascaded low power CMOS operational trans conductance amplifier (OTA) for ECG applications

Analysis and Design Procedures of CMOS OTAs Based on Settling Time

Analysis of generic single-pole, two-pole, and three-pole operational transconductance amplifiers (OTAs) is carried out based on settling time. The most important design metrics of the open-loop frequency response, such as the stability margins and the gain-bandwidth product (GBW) are related to the settling time of single-, two- and three-stage OTAs in closed-loop configuration, enabling to present a design procedure for each OTA based on the settling time specifications. Transistor-level design examples are provided for each case to validate the described settling-based design strategies.

Planar CMOS and multigate transistors based wide-band OTA buffer amplifiers for heavy resistance load

Analog buffer amplifier configurations capable of driving heavy resistive load using different operational transconductance amplifier (OTA) are presented in this paper. The OTA CMOS buffer configurations are designed using 0.18 ?m SCL technology library in Cadence Virtuoso tool and multigate transistor OTA buffer in TCAD Sentaurus tool. CMOS OTA buffer configuration using simple OTA outperform the OTA buffer circuits using other OTAs in terms of power dissipation and stability. Measured results show that the OTA buffer circuit works well for resistive load below 100 ?. The gain tuning of up to 5 V/V is achieved with RL equal to 50 ?, output swing of 1 V. OTA buffer configuration implemented using multigate transistor with resistive load below 1 k? exhibits a bandwidth around 5 GHz and tunable gain up to 5 V/V.

On the Sizing of CMOS Operational Amplifiers by Applying Many-Objective Optimization Algorithms

In CMOS integrated circuit (IC) design, operational amplifiers are one of the most useful active devices to enhance applications in analog signal processing, signal conditioning and so on. However, due to the CMOS technology downscaling, along the very large number of design variables and their trade-offs, it results difficult to reach target specifications without the application of optimization methods. For this reason, this work shows the advantages of performing many-objective optimization and this algorithm is compared to the well-known mono- and multi-objective metaheuristics, which have demonstrated their usefulness in sizing CMOS ICs. Three CMOS operational transconductance amplifiers are the case study in this work; they were sized by applying mono-, multi- and many-objective algorithms. The well-known non-dominated sorting genetic algorithm version 3 (NSGA-III) and the many-objective metaheuristic-based on the R2 indicator (MOMBI-II) were applied to size CMOS amplifiers and their sized solutions were compared to mono- and multi-objective algorithms. The CMOS amplifiers were optimized considering five targets, associated to a figure of merit (FoM), differential gain, power consumption, common-mode rejection ratio and total silicon area. The designs were performed using UMC 180 nm CMOS technology. To show the advantage of applying many-objective optimization algorithms to size CMOS amplifiers, the amplifier with the best performance was used to design a fractional-order integrator based on OTA-C filters. A variation analysis considering the process, the voltage and temperature (PVT) and a Monte Carlo analysis were performed to verify design robustness. Finally, the OTA-based fractional-order integrator was used to design a fractional-order chaotic oscillator, showing good agreement between numerical and SPICE simulations.

An ultra-low-power bulk-driven subthreshold super class-AB rail-to-rail CMOS OTA with enhanced small and large signal performance suitable for large capacitive loads

This paper introduces a power-efficient super class-AB bulk-driven (BD) operational transconductance amplifier (OTA) in the subthreshold region suitable for driving a high capacitive load. An improved auxiliary differential amplifier is employed using a cross-coupled connection to the gate of the input core differential pairs and its adaptive biasing BD FVF differential pairs to boost the input core transconductance and slew rate in superclass-AB mode. The utilization of a partial positive feedback operation further improves the open-loop voltage gain, overall effective transconductance, and unity-gain frequency (UGF) with a sufficient phase margin of 93⁰. The Post layout simulation results of the proposed OTA in Cadence DFW-II platform using UMC 0.18 μm technology for a 0.5 V single supply and a capacitive load of 200 pF confirm enhancement of 22 times slew rate, 54.32 dB DC gain, and 75 times UGF achieved by the proposed design over its conventional counterpart with only a narrow increase of 1.19 times in power expenditure.

High-Speed CMOS Three-Stage Amplifier Based on Feedback Attenuation

This paper presents a new and simple frequency compensation scheme for multistage CMOS operational transconductance amplifiers (OTAs). In this work, by applying a differential block frequency compensation (DBFC) technique to a compensation network of three-stage OTA, the dominant pole is drastically improved independent from the DC gain path. The DBFC introduces amplified signal directly to the second-stage output through the compensation capacitor. The signal injection increases operational frequency range while just a single and small value capacitor is used as the Miller capacitor, which leads to considering the proposed configuration as a low die area occupation and high-speed amplifier. The simulation results show with the same capacitive load and power dissipation the gain bandwidth (GBW) frequency can be improved considerably compared to conventional nested Miller compensation. The presented circuit is simulated in a 0.18[Formula: see text][Formula: see text]m CMOS technology with a 1.8[Formula: see text]V supply voltage. According to the results, the proposed circuit shows 102[Formula: see text]dB, 105[Formula: see text]MHz, and 343[Formula: see text][Formula: see text]W as the DC gain, GBW, and power consumption, respectively.

A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

In this paper, a new strategy for the design of ultra-low-power CMOS operational transconductance amplifiers (OTAs), using the gm/ID approach, is proposed for the Internet-of-things (IoT) scenario. The strategy optimizes the speed/dissipation of the OTA in terms of settling time, including slew-rate effects. It was designed for large capacitive loads and for transistors biased in the sub-threshold region, but it is also suitable for low-capacitive loads or for transistors biased in the saturation region. To validate the proposed strategy, a well-known three-stage OTA was designed starting from capacitive load and settling time requirements. Simulations confirmed that the OTA satisfies the specifications (even under Monte Carlo analysis), thus proving the correctness of the proposed approach.

New Resistorless Third-Order Quadrature Sinusoidal Oscillators

This paper introduces four new resistorless, third-order, electronically tunable, quadrature sinusoidal oscillators using three operational transconductance amplifiers (OTAs) and three capacitors. The proposed third-order quadrature sinusoidal oscillators (TOQSOs) provide noninteracting control of the oscillation condition (OC) and oscillation frequency (OF) by changing the transconductance of different OTAs, to produce sustained oscillations and offer quadrature output voltages and currents. Two of the proposed quadrature oscillator circuits have capacitor control of OF, a feature, useful in capacitive transducers. The presented TOQSO structures have good frequency stability and exhibit low active and passive sensitivities. PSPICE simulations using CMOS OTAs along with hardware results (using off-the-shelf available OTA IC LM13700) have also been provided to confirm the workability of the presented circuits.

Thermal Reliability of a CMOS-OTA Versus Improving Its Parameters

In this study, the relationship between thermal sensitivity of a CMOS operational transconductance amplifier (OTA) and other parameters of the OTA such as gain bandwidth (GBW), DC gain, settling time, slew rate (SR), etc. is analyzed and discussed. For the first time, it is shown that although some techniques such as adaptive biasing and DC gain enhancement can be utilized to improve the transient response of a CMOS-OTA by increasing the input stage’s gain, DC gain, GBW and SR, yet this causes a significant increase in the thermal sensitivities of the CMOS-OTA, so that, the reliability of accurate operation of the CMOS-OTA under variation in ambient temperature effectively decreases. This paper concludes that a reconciliation of the thermal reliability with improvement of the CMOS-OTA parameters should be considered when the CMOS-OTA is designed and implemented. This point is the contribution of this work that has not been considered and addressed in any other works. Simulated results performed using 0.18[Formula: see text][Formula: see text]m SILTERRA CMOS process technology and real experimental results are presented that explicitly verify the theoretical results.

Two New Third-Order Quadrature Sinusoidal Oscillators

ABSTRACT This communication presents a systematic realization of two new third-order quadrature sinusoidal oscillators employing operational transconductance amplifiers (OTAs). These oscillators use canonical number of transconductors (four) and canonical number of grounded capacitors (three). The proposed oscillators enjoy independent electronic control of the condition of oscillation (CO) and frequency of oscillation (FO). The independent electronic adjustment of FO through two identical transconductances controlled by a single external voltage (without disturbing CO) is beneficial in designing voltage-controlled oscillators (VCOs). The presented oscillators have high-frequency stability factor and low power consumption. Circuit simulations employing CMOS OTAs and experimental results using off-the-shelf available OTA IC LM13700 have also been included to confirm the workability of the presented circuits.

Mathematical Formulation and OTA based Emulator for Three Cross-over Memristor

ABSTRACT The Mathematical formulation and a circuit emulator for memristor having three cross-over points in its transient VI curve, has been reported in this paper. The condition for exhibiting three cross-over (pinch-off) points, coordinates of the cross-over points, cross-over instances and the area enclosed under lobes have been derived from three cross-over memristive equation. Furthermore to verify the mathematical model, a three pinch-off memristor (TPM) emulator employing five operational transconductance amplifiers (OTAs), three grounded resistances and single-grounded capacitance has also been proposed. The use of grounded passive elements confirms the suitability of proposed emulator for on-chip implementation. The presented TPM emulator does not require any external voltage multiplier/IC, which can be considered as the key advantage of this configuration. The electronic tunabilty of proposed emulator can be achieved through biasing voltage. The behaviour of realised emulator is studied by performing simulations in the PSPICE environment using CMOS OTA with 0.18um TSMC technology. The presented OTA-based TPM emulator is also realised by commercially available IC LM13700.

Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior

In this paper we are going to analyze the settling-time in single-, two- and three-stage amplifiers with the intent of deriving approximate but useful design equations that include the effects of the zeros and of the slew-rate limitations. The analysis is mainly devoted to the definition of an approach for the design of three-stage CMOS operational transconductance amplifiers from settling-time specifications. A design example is carried out to validate the proposed approach.

Low quiescent current capacitor-less LDO regulator with high slew rate super class AB CMOS OTA

This paper presents a low quiescent current capacitor-less low-dropout regulator (LDO) with high slew rate super class AB CMOS operational transconductance amplifier (OTA). The OTA of this design is based on the combination of class AB differential input stages and local common-mode feedback (LCMFB) which provides additional dynamic current boosting, increased gain-bandwidth (GBW) product and slew rate (SR). LCMFB is applied to various class AB differential input stages, leading to different class AB OTA topologies. The design also uses dynamic charging transistor (DCT) to enhance the transient characteristics of the circuit. The presented LDO is fabricated in a 0.18 um standard CMOS process. The circuit consumes a quiescent current of 10 uA at no load, regulating the output at 1.0V with maximum output current of 100mA from a voltage supply of 1.2V. It achieves full range stability from 1mA to 100mA load current at a maximum 100pF load capacitor.

A wide linear range CMOS OTA and its application in continuous-time filters

In this paper, we have proposed a highly linear Operational Transconductance Amplifier (OTA) with wide linear input range. The proposed OTA utilizes conventional source degeneration with an auxiliary differential pair which increases the linear range significantly by reducing the distortion components. The proposed OTA is targeted for current mode circuit applications including low-frequency continuous time filters. A second-order fully differential filter architecture is also implemented by using this proposed OTA. The linear OTA and the filter are implemented in SCL 180 nm CMOS process technology with 1.8 V supply voltage. The proposed OTA achieves third order harmonic distortion ($${\textit{HD}}_3$$) of $$-\,74.3$$ dB, inter modulation distortion ($${\textit{IM}}_3$$) of $$-\,75.5$$ dB for $$600\,\hbox{mV}_{p-p}$$ differential input with 1 MHz signal frequency and a linear range of 0.9 V for 1% transconductance variation. The filter is designed for 100 kHz cutoff frequency and achieves $${\textit{HD}}_3$$ of $$-\,68.75$$ dB and $${\textit{IM}}_3$$ of $$-\,64.3$$ dB for $$300\,\hbox{mV}_{p-p}$$, 10 kHz input signal.

Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers

In this paper, a new architecture of four-stage CMOS operational transconductance amplifier (OTA) based on an alternative differential AC boosting compensation called DACBC is proposed. The presented structure removes feedforward and boosts feedback paths of compensation network simultaneously. Moreover, the presented circuit uses a fairly small compensation capacitor in the order of 1 pF, which makes the circuit very compact regarding enhanced several small-signal and largesignal characteristics. The proposed circuit along with several state-of-the-art schemes from the literature have been extensively analysed and compared together. The simulation results show with the same capacitive load and power dissipation the unity-gain frequency (UGF) can be improved over 60 times than conventional nested Miller compensation. The results of the presented OTA with 15 pF capacitive load demonstrated 65° phase margin, 18.88 MHz as UGF and DC gain of 115 dB with power dissipation of 462 μW from 1.8 V.

RETRACTED ARTICLE: Design of Three Stage Cascaded Low Power CMOS Operational Trans Conductance Amplifier (OTA) for ECG Applications

The primary test incorporates intensifying the weak signal within the noisy environment. The OTA configuration is all around used to evacuate the glint commotion. The execution of the ECG enhancer can be enhanced by three-arrange operational transconductance amplifiers (OTAs) utilizing nanometer CMOS advancements with doping input transistor measuring, device coordinating and filtration process. This three phase configuration has a few favorable circumstances, for example, current part, source degeneration to expand the linearity of the device.

High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of <inline-formula> <tex-math notation="LaTeX">${C}_{L}$ </tex-math> </inline-formula>

This brief presents a low-power, area-efficient three-stage CMOS operational transconductance amplifier (OTA) suitable for very large capacitive loads, C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> . A single Miller capacitor and an inverting current buffer embedded in the input stage are exploited to implement the frequency compensation network. An additional feed-forward path and a slew rate enhancer are also utilized to improve the large-signal transient response. Detailed small-signal analysis reveals that the proposed OTA does not exhibit an upper limit of drivable C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> . The OTA is fabricated in a standard 0.35-μm technology and occupies 0.0027 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of die area. Under 1.4-V supply and 6.36-μA quiescent current consumption, it provides a dc gain greater than 110 dB and is stable for any C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> larger than 5 nF. Comparison with the state of the art shows remarkable improvement of both small- and large-signal performance.