CMOS NAND Gate Research Articles

Thermodynamic Property of a CMOS Device beyond Landauer Limit

Focusing on a CMOS NAND GATE operating in a sub-threshold region, the thermodynamic cost of computation was analyzed in relation to input/output voltages surpassing the Landauer limit.

HALF ADDER DESIGN USING VARIOUS TECHNOLOGIES AND COMPARISON OF

: In this paper, investigate and analysis various techniques for implementing a half adder circuit with the fewest transistors possible. In digital electronics half adder combinational circuit used to add two numbers. It is an arithmetic circuit that performs the arithmetic operation of adding two single-bit words. The half adder technique, design of half adder using AVL technology, Design of a 3-T Half Adder, NMOS pass transistors logic design of half adder using 2:1 MUX, half adder circuit design with CMOS NAND gates, half adder circuit design with CMOS transmission logic gates in cadence virtuoso. In this section, compare half adder circuit design techniques and compare various parameters of half adder circuit design used various circuit design techniques. Conventional techniques required fewer number routing resources. A 3-T halfadder circuit performs with less delay, high speed, small layout area, less power consumption and batter efficiency and accuracy

Experimental Validation of a Resilient Electronic Logic Design with Autonomous Fault Discrimination/Masking

This paper presents the experimental validation of a novel fault-tolerant electronic logic design conducted by an automated mixed-signal fault injection procedure. The design under evaluation relies upon a novel redundant design strategy intended to provide fault discrimination and selective fault masking embedded within a functional CMOS NAND gate. The traditional logic layout is modified to include fault detection and reporting at an extremely fine-grained design level with 2x overhead as opposed to the traditional 4x overhead. The fault injection test bench procedure requires automated fault injection, programmable fault load conditions and combined analogue/digital domain verification. The device under test is implemented using discrete n- and p-FETs arranged as a modular test board together with automated fault injection and test lines. The fault response is measured and confirms the predicted intrinsic fault rate of 25% with a successful 100% masking of suck low-faults and precise identification of stuck-high via IDDQ trigger. The test procedure is shown to be extensible towards more complex logic unit designs and for evaluation of multiple simultaneous faults.

Optimisation of digital circuits using quantum ant colony algorithm

In this paper, a comparison of different optimisation algorithms on various digital circuits is investigated. We consider evolutionary algorithms such as ant colony optimisation (ACO) and quantum ACO (QACO) for optimisation of four different digital circuits, namely, transmission gate implementation of XOR gate, CMOS NAND gate, four-inverter CMOS buffer chain and a 1-bit full adder circuit. The transistor sizes of these circuits were optimised so as to obtain the minimum weighted average of power and delay. The simulation results show that the performance of QACO is better than that of the ACO for the circuitry containing more number of transistors.

Optimisation Of Digital Circuits using Quantum Ant Colony Algorithm

In this paper, a comparison of different optimisation algorithms on various digital circuits is investigated. We consider evolutionary algorithms such as ant colony optimisation (ACO) and quantum ACO (QACO) for optimisation of four different digital circuits, namely, transmission gate implementation of XOR gate, CMOS NAND gate, four-inverter CMOS buffer chain and a 1-bit full adder circuit. The transistor sizes of these circuits were optimised so as to obtain the minimum weighted average of power and delay. The simulation results show that the performance of QACO is better than that of the ACO for the circuitry containing more number of transistors.

A new universal gate for low power SoC applications

This paper formulates a new design technique for an area and energy efficient Universal NAND gate. The proposed robust three transistors (3T) based NAND gate is just as effective for dynamic power control in CMOS VLSI circuits for System on Chip (SoC) applications. The 3T NAND gate is intuitively momentous and lead to better performance measures in terms of dynamic power, reduced area and high speed while maintaining comparable performance than the other available NAND gate logic structures. Simulation tests were performed by employing standard Berkeley Predictive Technology Model (BPTM) 22 nm, 45 nm and 90 nm process technologies. The experiment and simulation results show that, the proposed 3T NAND gate effectively outperforms the basic CMOS NAND gate with excellent driving capability and signal integrity with exact output logic levels.

A Quadrature Pulse Generator for Short-Range UWB Vehicular Radar Applications Using a Pulsed Oscillator and a Variable Attenuator

A new quadrature tunable pulse generator is presented in this paper using 0.13 μm CMOS for 22-29 GHz ultrawideband (UWB) vehicular radar. A quadrature inductor-capacitor (LC) oscillator is quickly switched on and off for the duration of the pulse, and the amplitude envelope is modulated with an impulse using a variable passive CMOS attenuator. The impulse is realized using a glitch generator (CMOS nand gate) and its duration can be changed over a wide range (375 ps to more than 1 ns). The switching technique used in the quadrature oscillator creates a large initial voltage for fast startup (0.5 ns) and locks the initial phase of the oscillations to the input clock for pulse coherence. The measured phase noise thus matches that of the clock signal, with a relatively low phase noise of -70 dBc/Hz and -100 dBc/Hz at 1kHz and 1 MHz offsets respectively. The entire circuit operates in switched-mode with a low average power consumption of less than 2.2 mW and 14.8 mW at 50 MHz and 600 MHz pulse repetition frequencies, or below 11 pJ of energy for each of the four differential quadrature pulses. It occupies an active area of less than 0.41 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Circuit delay calculation considering data dependent delays

Accurate detection of both maximun and minimum circuit delay times and the detection of input vectors that produce those delays are crucial tasks in the design and testing of high speed CMOS circuits. This is especially true for timing disciplines, such as single phase latching, wave pipelining, and asynchronous design, where combinational logic delays paths are designed to be nearly equal and timing constraints are very tight. For these design methodologies, traditional timing analysis based on gate delay models assuming single delay values forgates or delay values based only on gate inputs is not sufficient. For example, two input CMOS NAND gate delay can vary by as much as a factor of two based on whether one input is changing or both inputs are changing. This implies that, for accurate detection of maximum and minimum overall delay, sensitization of multiple paths must be considered to ascertain feasibility of multiple simulationeous input transitions at particular gates. This paper considers this problem beginning with a brief discussion of CMOS gate delays. An algorithm is then presented that accurately detects both maximum and minimum delays considering the effect of delay differences due to rising and falling transitions and due to single vs. multiple simultaneous signal changes at gate inputs. Results of this process are demonstrated in a prototype timing analyzer XTV.