CMOS Gate Array Technology Research Articles

RESIDUE-WEIGHTED NUMBER CONVERSION FOR MODULI SET {2n-1, 2n + 1, 22n + 1, 2n} USING SIGNED-DIGIT NUMBER

Signed-digit number systems support carry-free, constant time addition. By introducing the signed-digit number arithmetic into a residue number system (RNS), arithmetic operations can be performed efficiently. In this paper, a new algorithm for residue-to-binary conversion for four moduli set {2n-1, 2n + 1, 22n + 1, 2n} that only requires modulo 24n - 1 SD number addition is proposed. This moduli set has 5n-bit dynamic range. Based on the proposed algorithm, the converters are designed with a two-level binary tree structure formed by the modulo 24n - 1 SD number residue adders. Moreover, we simplify the residue adders in converters to obtain more area and time efficiency. The comparison of the converters proposed with the converter using binary arithmetic using 0.18 μm CMOS gate array technology yields reductions in delays of 44%, 60% and 75% for n = 4, n = 8 and n = 16, respectively.

A VLSI implementation method of a compressor for audio systems.

In this paper, we present a VLSI implementation method on a dynamic range controller, audio level compressor, which is used to make sound effects as an important functional part in a digital audio system on a chip. To implement the gain calculation in a digital dynamic range controller, a power calculation with fractional numbers is required and it is difficult to be performed directly in a digital audio system. We introduce a polynomial expression to approximate the power operation, then the gain calculation is easily performed with a number of additions, multiplications and a division. Based on the gain calculation method of the gain, an efficient VLSI architecture with some arithmetic circuits is proposed. We designed the circuit of a 16-bit audio level compressor by using a hardware description language, VHDL. As a result of the compact circuit design, the 16-bit compressor has only 5,688 gates by 1 μm CMOS gate array technology. The design and simulation results show that the presented audio level compressor has high performance and can be integrated into an audio system on a chip for practical use.

Development of front-end electronics and TDC LSI for the ATLAS MDT

Architecture of the front-end electronics for the ATLAS muon precision chamber (MDT) is presented. Especially, test results of a prototype TDC chip are described in detail. The chip was fabricated in a 0.3 μm CMOS Gate-Array technology. Measurements of critical elements of the chip such as the PLL, and data buffering circuits demonstrated adequate performance. The effect of gamma-ray irradiation, using a 60Co source, and neutron irradiation, were also examined. The test results revealed radiation tolerance adequate for the operation of the circuits in the environment of the ATLAS MDT. Mounting of the front-end electronics to the MDT is scheduled to start in the year 2001.

Time memory cell VLSI for the PHENIX drift chamber

A high-precision Time-to-Digital-Converter VLSI, TMC-PHX1, was developed for the PHENIX drift chamber. The chip contains 4 channels of TDC with two stages of data buffering and a trigger buffering which are necessary for very high rate experiments. In addition to the fixed data size readout, the chip also supports zero-suppression mode readout. The chip records both rising and falling edge timings, and has a least timing count of 0.83 ns/bit and 1.66 ns/bit respectively. A level 1 buffer has a recording depth of 6.8 /spl mu/sec and a readout FIFO has a depth of 128 words. High precision timing was derived from an asymmetric ring oscillator stabilized with a PLL. The chip runs at 4 times faster clock (37.6 MHz) of the RHIC bunch clock, and was fabricated with 0.5 /spl mu/m CMOS gate-array technology.

An ASIC implementation of an optimized digital video encoder

This paper presents a design of an optimized video encoder using a simple pipelined architecture. The proposed video encoder accepts conventional NTSC/PAL video signals. It also processes the PALplus video signal using an improved decimation process. The proposed encoder requires only 25 K gates, which is a 41% reduction in hardware compared with the systolic pipelined architecture of Oh, Choi, Kwon and Lee (see ibid., vol.43, no.3, p.965-71, 1997). The encoder has been designed in a 5-stage pipelined structure to assure stable operation. The overall performance of the encoder has been verified by using 0.65 /spl mu/m CMOS gate array technology. The chip size is 5170 /spl mu/m * 435O /spl mu/m.

A variable length coding ASIC chip for HDTV video encoders

This paper describes functions and architecture of a VLC ASIC chip specially designed for a parallel processing HDTV video encoder. It is designed to have several operating modes which is very flexible in that it can process in a master or slave sub-picture encoding module of an HDTV encoder, as well as in a stand-alone encoder for several video input formats according to MPEG-2 MP@ML. The VLC chip is fabricated using 0.8 /spl mu/m CMOS gate array technology, and runs at 27 MHz clock rate.

Vector quantization with compressed codebooks

Abstract Codebook storage is the key limitation in reducing distortion of vector quantization (VQ). We propose an effective lossless compression scheme with reduced computational requirements. Variable precision representation (VPR) for each vector y stores exp( y ), the number of leading bits which are zero in all elements, and avoids storing the zero bits. We show that storing the difference of centroid codevectors effectively removes the redundancy in the codebook. This difference is non-stationary. As the mean square error of the VQ encoder decreases, the added codevector differences become smaller and more amenable to compression. In mean-residual VQ, VPR can save more than 50% in storage, and achieve more than 75% bit reduction of entropy coding. Moreover, VPR reduces the cost of VQ. The VPR inner product module has 10% less area × time cost than the conventional inner product. The designs are verified and their speed estimated for 1.0-μ CMOS gate array technology. Using tree-structured VQ, they can encode in real-time television quality video (720 × 576 pixels × 30 frames/s).

A chip set for pipeline and parallel pipeline FFT architectures

A chip set for pipelined and parallel pipelined FFT applications is presented. The set consists of two cascadeable chips with built-in self-test and a chip-interconnectivity test feature. The two ASICs are a 15k gate Complex-Butterfly and a 9k gate FFT Switch. The Complex-Butterfly uses redundant binary arithmetic (RBA), a modified Booth algorithm and a Wallace tree architecture to achieve a throughput of better than 25 Msamples/sec. The cascadeable FFT Switch is designed to support the implementation of radix-2, 2N point, pipeline FFTs. Both devices have been fabricated in 1.5μm CMOS gate array technology.

Decision-directed burst-mode carrier synchronization techniques

A decision-directed, digitally implemented carrier synchronizer for channels with both frequency and phase uncertainty is presented. This combined algorithm and its derivatives are analyzed with respect to the achievable carrier acquisition time and the resulting bit error probability. For certain data rates (approximately 50 MSps or less), this algorithm can be implemented using CMOS gate array technology. As examples BPSK and QPSK modulation formats are studied herein and compared to their differentially coherent counterparts of DPSK and DQPSK. >

Neural networks in CMOS: a case study

The design of a six-neuron chip using 1.3- mu m CMOS gate-array technology is described. With these neuro-chips, the authors developed a general-purpose neural-network system that can simulate a wide range of neural networks, including Hopfield-type networks, back propagation networks, and many others. The system consists of several neuro-boards and a host computer. Each neuro-board contains 72 neuro-chips, which constitute a network of 54 neurons with 2916 excitatory and 2916 inhibitory synapses. The computer can read and write various registers in the neuro-board, learning algorithms can be executed, and synaptic strength can be easily updated. A hierarchical bus structure of time-sharing buses connects each of the neurons on the wafer. As fabricated, the neuro-WSI uses 0.8- mu m, three-level-metal CMOS gate-array technology. >

An architecture of real‐time video signal processing LSI‐picot

AbstractA real‐time video signal processing LSI‐Picot has been developed which processes dynamic images at video rate. Picot has an architecture which is suited to the image and video signal processing. By employing several internal buses and a new program control scheme, all operations are performed in one cycle 70 ns (=1/14.3 MHz). It has functions of not only addition, subtraction, and multiplication but also the maximum, minimum and absolute value operations, which are indispensable to image processing. Its dedicated addressing units can concurrently perform the memory write/read and operation with a data memory of up to 16 Mw connected, and it can cope with a large‐size static image exceeding that of HDTV. Picot is constructed using 1.5 μm CMOS gate array technology and a 30,000‐gate circuit integrated on a 14.95 mm × 14.95 mm chip, to be implemented on a 223‐pin PGA. It operates on a 5‐V single power supply with the power consumption of approximately 1 W.