CMOS Frequency Doubler Research Articles

A Compact 24.5–32.6 GHz CMOS Frequency Doubler Based on Coupled Inductor

A Compact 24.5–32.6 GHz CMOS Frequency Doubler Based on Coupled Inductor

Optimally Matched 189-232 GHz 6.8 dBm Output Power CMOS Frequency Doubler

This paper presents the design and measurements of a 215-252 GHz 40 nm bulk CMOS frequency doubler with a 6.8 dBm deliverable peak output power and a conversion gain of 11.8 dB. The designed chip is composed of a 28.5 dB gain 6-stages 110 GHz power amplifier, an optimized push-push doubler biased in class-C configuration, and an output impedance matching network. A numerical method had been applied here for designing each implemented matching network achieving the optimum matching while maintaining the minimum insertion loss as well. The presented design shows the highest output power among the other sub-THz-designed CMOS counterparts. The design occupies an area of 0.795 mm2 and shows a total DC power dissipation of 262 mW and DC-RF efficiency of 1.87%.

185–215 GHz CMOS Frequency Doubler with a Single Row Staggered Distribution Layout Design

This paper presents a 220 GHz × 2 amplifier–doubler chain composed of a rat-race balun, a 6-stage driver amplifier, and a frequency doubler. The presented amplifier–doubler chain was fabricated in commercial 40 nm bulk CMOS technology. The maximum cutoff frequency fmax for the NMOS transistor produced by this manufacturing process was 290 GHz. The saturation output power of the six-stage driver amplifier at 110 GHz was 11.5 dBm. The transistor of the frequency doubler consisted of a single-row interleaved Poly-Diffusion Contact balancing structure. Theoretically, the single-row interleaved Poly-Diffusion Contact balancing structure was able to effectively avoid parasitic components. The simulated results demonstrate that the presented structure achieves a higher output than the conventional designs. Based on these measured results, the presented amplifier–doubler chain provides a peak output power of 7.9 dBm at 200 GHz and a 3-dB bandwidth of 30 GHz. Based on the comparison with other reported results, the presented amplifier–doubler chain provides the highest output power among reported frequency doublers fabricated in CMOS technology.

A CMOS Frequency Doubler from the Analog Cosine Mapping Function

This work presents the design of a new frequency doubler by a simple inductorless active network, without the exigency of additional quadrature signals. The frequency doubling function of the proposed circuit relies on the analog cosine mapping operation. The mapping circuit is possible in voltage mode as the circuit is based on two face-to-face CMOS inverters switched by the same differential input signal. The circuit is designed, with a simple set of functions, according to the nonlinear circuit’s nature. It was designed in a CMOS 0.18- $$\upmu $$ m process with a doubling frequency up to $$8~\text{ GHz }$$ . The experimental results of the prototype on the mentioned frequency range show the frequency doubling operation with a phase noise figure of $$-\,130~\text{ dBc/Hz }$$ @ $$10~\text{ KHz }$$ offset from the carrier.

A Truly Balanced Q-Band CMOS Frequency Doubler Based on Hybrid Quadrature Coupler

In this letter, a truly balanced CMOS Q-band frequency doubler with an ultra-compact differential hybrid quadrature coupler is demonstrated using 90-nm CMOS technology. The doubler incorporates two Gilbert-cells fed by I/Q signals to compensate the time delay from transconductance stage and avoid output DC offset, providing truly balanced differential outputs. The doubler achieves a 3-dB bandwidth from 40 to 49 GHz with a minimum conversion loss of 1.6 dB at 44 GHz, while the output amplitude imbalance is measured to be less than 0.7dB. The measured I/Q mismatch of the quadrature coupler is less than 1° within 10 GHz bandwidth. The doubler chip consumes 9.6 mA from a 1.2-V supply, and the chip dimension is 0.7 × 0.9 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A High Efficiency E-Band CMOS Frequency Doubler With a Compensated Transformer-Based Balun for Matching Enhancement

This letter presents a broadband high efficiency frequency doubler based on a new and effective compensation technique. A transformer based input balun achieves good balanced performance and input matching by the newly invented central capacitor based compensation technique. It demonstrates a peak conversion gain (CG) of $-$ 2.5 dB and peak efficiency of 9.7% with a saturated output power of 2.5 dBm at 74 GHz. The doubler exhibits a 3 dB CG bandwidth of 28 GHz from 62 to 90 GHz. The fundamental rejection is larger than 20 dB. The doubler is fabricated in a 65 nm CMOS technology with chip area of $0.6\times 0.45 {\rm mm}^{2}$ and consumes 9–14 mW power.

K‐band CMOS frequency doubler with high fundamental rejection

The design of a frequency doubler with current-reuse and fundamental rejection topology is presented. The frequency doubler is fabricated by a standard 0.18 μm CMOS process with a chip size of 0.57 mm2. The DC power consumption is 13.9 mW. In addition, the measured conversion gain is between –4.4 and –5.24 dB from 10 to 12 GHz input frequency. With the proposed active notch filter in the cascode stage of the doubler, a superior fundamental rejection is obtained. The measured fundamental rejection is between 32.4 and 53.8 dB.

Propagation delay matched CMOS 0.18 μm frequency doubler for L‐band application

AbstractIn this article, propagation delay matched CMOS frequency doubler for L‐band application is proposed. Schmitt trigger and voltage controlled delay line compensates duty cycle error and propagation delay mismatching that are induced as the frequency of operation is increased. As a consequence, unwanted harmonic components suppression is greatly improved for higher frequency of operation. CMOS frequency doubler is designed at the input fundamental frequency (f0) of 1.15 GHz and fabricated with TSMC 0.18 μm CMOS process. Measured output power at the doubled frequency (2f0) is 2.67 dBm for the input power of 0 dBm. The amount of harmonic suppression for f0, 3f0, and 4f0 are 43.65, 38.65, and 35.59 dB, respectively. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1729–1732, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24420

A 28GHz CMOS FREQUENCY DOUBLER WITH TFMS

In this paper, a 28GHz CMOS frequency doubler with TFMS (thin film microstrip line) has been introduced in order to experimentally study the possibility of millimeter wave CMOS devices based on TFMS. The present doubler shows 2dB conversion loss and approximately 12dB suppression to fundamental frequency. The result shows that the CMOS technology compatible TFMS are promising on the design of millimeter-wave CMOS devices.

A 1.8-V operation 5-GHz-band CMOS frequency doubler using current-reuse circuit design technique

This paper describes the circuit design and measurement results of a new CMOS frequency doubler proposed for 5-GHz-band wireless applications. The doubler, which can operate at 1.8 V, was fabricated in a standard 0.18-/spl mu/m bulk CMOS technology which has no extra processing steps to enhance RF performance. A current-reuse circuit-design technique is successfully incorporated into the doubler so as to realize both on-chip input/output matching and adequate conversion gain with low input power drive despite the utilization of the standard bulk CMOS technology. The doubler with a single input/output interface features a bypass resistor placed between common ground and a source node of the second stage FET in the current-reuse topology, thereby improving both input power level and conversion gain while saving waste current. Measurement results under the condition of 5.2 GHz and 1.8 V reveal the following good performance: a 2.7-dB maximum conversion gain, a 0.3-dBm high output power, and a 9-mA low current dissipation are achieved with a 2.6-GHz, -3-dBm input power. With a 7-mA low current dissipation and a -7-dBm low input power, the doubler can deliver conversion gain as high as 0 dB. These measurement results are good agreement with the simulated ones.