Current-mode CMOS Circuits Research Articles

Design of current steering logic CMOS circuit

The current-mode CMOS technology has many positive identities, while traditional current-mode CMOS circuits designing methods is comparatively more complex than voltage-mode CMOS. In this paper, using threshold logic, a current-mode CMOS circuits designing method based on spectral techniques is proposed. The proposed method is capable of designing combinational logic current-mode CMOS circuits. The sequential logic current-mode CMOS circuits can also be designed with the designed combinational logic current-mode CMOS circuit. The designed circuit is steered only by current signals. By using both simulations and real circuit tests, we proved the effectiveness of the proposed circuit designing method. Using HSPICE simulations, the designed circuit is proven to have advantages including lower circuit power consumption and higher stability of the current through power supply compared with voltage-mode CMOS and other main current-mode CMOS circuits, and the designed circuits require less control signals than other major current-mode CMOS circuits.

Low-voltage subthreshold CMOS current mode circuits: Design and applications

The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a gm/ID based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90nm and UMC 130nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.

Noise Minimization in CMOS Current Mode Circuits That Employ Differential Input Stage

Noise Minimization in CMOS Current Mode Circuits That Employ Differential Input Stage

Equivalent circuit models in current-mode circuits for time delay calculations

In this paper time delay calculations for current-mode circuits are considered and equivalent circuit models for delay estimation are developed. Three different equivalent circuit structures for the Core Circuit used in the multipurpose IC DU-TCC1209 are examined separately; however the relation obtained for the time delay can be applied to any CMOS current-mode circuit. The proposed calculation methods are verified with SPICE using 0.35 μm TSMC MOSIS technology parameters and with bench-test measurements using DU-TCC1209.

Temperature insensitive current-mode CMOS exponential function generator and its application in variable gain amplifier

A new CMOS current-mode circuit to produce the exponential function, y=exp(x), is proposed. The proposed design has large input and output dynamic ranges while keeping very small linearity error. The functionality of the proposed design, confirmed using Tanner tool with 0.35μm CMOS process technology indicates that it has superior performance compared to previously reported designs. A nearly 96dB output dynamic range is obtained with the linearity error less than ±0.5dB over an input range −5.75≤x≤5.75. The change in the output current due to temperature variation is ±1.27dB over 100°C range. Application of the proposed exponential function generator in the design of an exponentially controlled variable gain amplifier is presented and its functionality is confirmed using simulation. 71 Linear-in-dB variable gain was achieved. The dB gain is controlled linearly by the control current, resulting in simple and low power structure.

A Bionics Chemical Synapse

Implementation of the current mode CMOS circuit for chemical synapses (AMPA and NMDA receptors) with dynamic change of glutamate as the neurotransmitter input is presented in this paper. Additionally, circuit realisation for receptor GABA(A) and GABA(B) with an electrical signal which symbolises γ-Aminobutyric Acid (GABA) perturbation is introduced. The chemical sensor for glutamate sensing is the modified ISFET with enzyme (glutamate oxidase) immobilisation. The measured results from these biomimetics chemical synapse circuits closely match with the simulation result from the mathematical model. The total power consumption of the whole chip (four chemical synapse circuits and all auxiliary circuits) is 168.3 μW. The total chip area is 3 mm(2) in 0.35-μm AMS CMOS technology.

Low Voltage and Low Power Current-Mode Divider and 1/X Circuit Using MOS Transistor in Subthreshold

A new low-voltage and low-power CMOS current-mode circuit that can perform divide and 1/x function is presented. HSPICE simulation was used to confirm the functionality of the circuit. This circuit will be a useful sub-circuit for analog current mode signal processing in battery powered application especially in biomedical implants.

Synthesis of Bias-Scalable CMOS Analog Computational Circuits Using Margin Propagation

Approximation techniques are useful for implementing pattern recognizers, communication decoders and sensory processing algorithms where computational precision is not critical to achieve the desired system level performance. In our previous work, we had proposed margin propagation (MP) as an efficient piecewise linear (PWL) approximation technique to a log-sum-exp function and had demonstrated its advantages for implementing probabilistic decoders. In this paper, we present a systematic and a generalized approach for synthesizing analog piecewise-linear (PWL) computing circuits using the MP principle. MP circuits use only addition, subtraction and threshold operations and hence can be implemented using universal conservation principles like the Kirchoff's current law. Thus, unlike the conventional translinear CMOS current-mode circuits, the operation of the MP circuits are functionally similar in weak, moderate, and strong inversion regimes of the MOS transistor making the design approach bias-scalable. This paper presents measured results from MP circuits prototyped in a 0.5 μm standard CMOS process verifying the bias-scalable property. As an example, we apply the synthesis approach towards designing linear classifiers and we verify its performance using measured results.

CMOS Current-Mode Implementation of Fractional-Power Functions

A CMOS current-mode circuit, with only eight transistors and two current sources, is proposed to implement a fractional power function. The compact circuit comprises of an approximating logarithm circuit and an approximating exponential circuit. By sizing one transistor and tuning one current source, we improve the truncation errors in the Taylor series approximation, and reduce the MOS square-law errors that are caused by second-order effects. As example, a circuit, designed for gamma correction, with different gamma values controlled by three switches, is fabricated using 0.35 μm CMOS technology. The demonstration circuit can achieve a bandwidth of 155 MHz for an input range from 40 μA to 130 μA with 3% error, and maximum power dissipation of approximately 970 μW.

Comments on "Improved Accuracy Pseudo-Exponential Function Generator With Applications in Analog Signal Processing

Recently a new CMOS current-mode pseudo-exponential function generator circuit was reported by Popa. The entire analysis and exponential function generator circuit, given in Popa's paper, is based on a current-squaring circuit module. In this comment paper we show that the current-squarer circuit, presented in Popa's paper, does not work as a current squarer. Consequently the pseudo-exponential generator also does not work as described in Popa's paper. We present a detailed mathematical analysis in this paper to derive its actual operation. Simulation results of the circuit module using Mentor Graphics custom IC design tool set, in a TSMC 0.18-μm CMOS process, are also shown in this paper. Simulation results match the behavior predicted by mathematical analysis.

High-performance current-mode CMOS simultaneous implementation of window-literal operations for multi-valued logic

A new current-mode CMOS circuit for simultaneous implementation of literal and complementary literal operations is presented. It is shown that the proposed circuit exhibits superior performance compared to its previous counterparts in terms of speed, power dissipation and robustness with much smaller area. These advantages make the circuit a very useful design block for multi-valued logic function realisations.

Low-voltage CMOS current-mode circuits: topology and characteristics

The author presents an in-depth study of the topologies and characteristics of low-voltage CMOS current amplifiers. The input impedance, output impedance, bandwidth, noise performance, and dynamic range of current amplifiers are investigated both analytically and numerically. Several new circuit techniques specific to low-voltage CMOS current-mode circuits including pseudo-cascode, current–current feedback, inductive series peaking, and joint resistive/inductive series peaking and current–current feedback for bandwidth enhancement, output impedance boosting, and dynamic range improvement are proposed. To provide a quantitative comparison and to quantify the effect of these new circuit techniques, the current amplifiers investigated are implemented in TSMC 0.18 μm 1.8 V CMOS technology and analysed using Spectre from Cadence Design Systems with BSIM3V3 device models that count for both device parasitics and high-order effects. Simulation results are compared with those from analytical analysis.

Low-voltage CMOS current-mode preamplifier: analysis and design

This paper presents the analysis and design of a new low-voltage fully balanced differential CMOS current-mode preamplifier for multi-Gbps series data communications. The minimum supply voltage of the proposed preamplifier is V/sub T/+V/sub sat/. The preamplifier employs a balanced configuration to achieve large bandwidth and to minimize the effect of bias-dependent mismatches. Two new bandwidth enhancement techniques, namely inductive series peaking and current feedback that are specific to low-voltage CMOS current-mode circuits, are introduced. The inductive series peaking technique utilizes the resonant characteristics of LC networks to achieve both a flat frequency response and maximum bandwidth. Current feedback extends bandwidth, lowers input impedance, and improves dynamic range. The employment of both techniques further increases the bandwidth, reduces the value of the series peaking inductor, and improves noise performance of the pre-amplifier at high frequencies. The preamplifier has been designed using a 0.18-/spl mu/m 6-metal 1-poly 1.8-V CMOS technology. Simulation results from Spectre with BSIM3.3 device models that account for device parasitics demonstrate that the preamplifier has a flat frequency response with 25.3 dB dc current gain or equivalently 60 dB/spl Omega/ transimpedance gain with a 50-/spl Omega/ load and bandwidth of 2.15 GHz.

Implementation of Multi-Valued Logic Gates Using Full Current-Mode CMOS Circuits

In this paper, a novel multi-valued logic gate set is designed by using only current-mode CMOS circuits. The gate set consists of min, max, inverter, literal, and cyclic operators based on a current-mode, versatile, novel threshold topology. They are shown to exhibit better static and dynamic behavior and consume less area compared to previous MVL design topologies and binary-logic counterparts. The gate circuits are investigated in terms of analog design aspects, such as mismatch and noise. The proposed topology is compared to previous topologies in terms of attainable radix and DC characteristics. A radix-8 multiplex function and a radix-8 full-adder circuit is designed to demonstrate the advantages of new current-mode multi-valued logic circuits.

A Mixed Signal Fuzzy Controller Using Current Mode Circuits

A mixed analog-digital fuzzy logic inference processor chip, designed in a 0.35-μm CMOS technology, is presented. The analog fuzzy engine is based on a novel current-mode CMOS circuit used for the implementation of fuzzy partition membership functions. The architecture consists of a 3 inputs--1 output analog fuzzy engine, internal digital registers to store the parameters of the fuzzy controller, and a digital subsystem that allows the programmability of the fuzzy controller via an I 2 C interface. The architecture, circuits, and some Cadence Spectre simulations are presented.

A New Inductor Series-Peaking Technique for Bandwidth Enhancement of CMOS Current-Mode Circuits

This paper introduces a new inductor series-peaking technique for bandwidth enhancement of low-voltage CMOS current-mode circuits. The peaking inductor is in series with the capacitor constituting the dominant pole. It boosts the bandwidth by utilizing the resonance characteristics of LC networks. To reduce the value of the peaking inductor, a new negative current-current feedback mechanism is proposed. The employment of both inductive peaking and current feedback further increases the bandwidth. Both the inductor series-peaking and the current-current feedback do not affect the supply voltage and DC biasing conditions. Theoretical analysis and simulation results show that a significant bandwidth enhancement is achieved.

Modulo correlativity and its application in a multiple valued logic system

Several new concepts, such as pseudoprime and modulo correlativity, are presented. Then modulo subtraction and modulo division, which are very useful in computing the canonical expansion, are proposed in a multiple valued modulo algebra system with either a prime or a composite radix. Finally the completeness of modulo operations and the current mode CMOS circuit design for any unary function are discussed on the basis of modulo correlativity. This method is also applicable to a high-radix multiple valued modulo algebra system.

Algebraic properties of multiple-valued modulo systems and their applications to current-mode CMOS circuits

The paper presents the concepts of pseudoprime and modulo correlativity and establishes the relationships among completeness of modulo operations, uniqueness of solution of equations, invertibility of a square matrix, and correlativity of vectors in multiple-valued modulo system. It is shown that current-mode CMOS circuits are easy to design and economical using bounded operations.

Design of symmetric ternary current-mode CMOS circuits

By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.

Implementations of artificial neural networks using current-mode pulse width modulation technique

The use of a current-mode pulse width modulation (CM-PWM) technique to implement analog artificial neural networks (ANNs) is presented. This technique can be used to efficiently implement the weighted summation operation (WSO) that are required in the realization of a general ANN. The sigmoidal transformation is inherently performed by the nonlinear transconductance amplifier, which is a key component in the current integrator used in the realization of WSO. The CM-PWM implementation results in a minimum silicon area, and therefore is suitable for very large scale neural systems. Other pronounced features of the CM-PWM implementation are its easy programmability, electronically adjustable gains of neurons, and modular structures. In this paper, all the current-mode CMOS circuits (building blocks) required for the realization of CM-PWM ANNs are presented and simulated. Four modules for modular design of ANNs are introduced. Also, it is shown that the CM-PWM technique is an efficient method for implementing discrete-time cellular neural networks (DT-CNNs). Two application examples are given: a winner-take-all circuit and a connected component detector.