CMOS Cell Library Research Articles

Reduced-Complexity Tracking Algorithms on Chip for Real-Time Location Estimation

This article puts forward a low-complexity filtering algorithm to achieve a low-complexity filtering chip design for real-time location tracking. In order to meet the need for low-complexity and real-time, the positioning tracking algorithm based on Kalman Filter (KF) is proposed. The KF itself has the functions of tracking, predicting, etc., which can correct the positioning into more accurate results. However, in the calculation of KF algorithms, each iteration often requires tedious and complex calculations of Kalman Gain (KG). Both software and hardware are very resource-intensive. Therefore, use the feature of KG in alpha-beta (α-β) filtering algorithm which can gradually balance in each iteration. Proposed a filtering algorithm that is based on low-complexity, low cost, and high efficiency. This algorithm uses DKF (Difference Kalman Filter) and PKF (Percentage Kalman Filter) depending on different environments. In other words, DKF and PKF are the algorithms which are generated based on different judging conditions. This algorithm can not only significantly reduce the time and the complexity of computing, but also greatly shorten the circuit area of the original algorithm. This algorithm has a large number of matrix operation. In the hardware calculation process, it solves matrix problems about hardware and then developed chip design. Coefficients are used by a multiple of 2 for operation. Use shifters instead of multipliers and dividers, significantly reducing complexity and circuit area. At the same time, deal with the problem of a floating-point number, achieve circuit function verification on the FPGA, and finally tape-out. The design uses the TSMC 0.18μm CMOS cell library provided by the TSRI, uses EDA to implement VLSI with the Design Vision of SYNOPSYS, the operating frequency of the circuit is 83.33 MHz, the value of gate counts is 22.84 K, the power consumption is 3.86 mW, and chip area is 582.63 μm × 580.23 μm.

A Lightweight System-On-Chip Based Cryptographic Core for Low-Cost Devices.

The backbone of the Internet of things (IoT) platform consists of tiny low-cost devices that are continuously exchanging data. These devices are usually limited in terms of hardware footprint, memory capacity, and processing power. The devices are usually insecure because implementing standard cryptographic algorithms requires the use of a large hardware footprint which leads to an increase in the prices of devices. This study implements a System-on-Chip (SoC) based lightweight cryptographic core that consists of two encryption protocols, four authentication protocols, and a key generation/exchange protocol for ultra-low-cost devices. The hardware architectures use the concept of resource sharing to minimize the hardware area. The lightweight cryptographic SoC is tested by designing a desktop software application to serve as an interface to the hardware. The design is implemented using Verilog HDL and the 130 nm CMOS cell library is used for synthesis, which results in 33 k gate equivalents at a maximum clock frequency of 50 MHz.

Exploring Multi-Level Composition and Efficient MCM Schemes for an Energy-Efficient Wavelet Haar Architecture

This work explores multi-level fixed-point Haar transform compositions combined with MCM (multiple constant multiplication) schemes for an energy-efficient hardware architecture. We investigate a set of six lower-level Haar transforms for composing a Haar-9 architecture. The multiple-level Haar transforms use as a base M=1, M=2, and M=3 resolution levels. The processing module (PM) of the Haar explores efficient MCM schemes. The architectures were described in VHDL and synthesized employing the ST 65nm CMOS cell library. The results show that Haar-II architecture presents the lower circuit area results since this architecture requires fewer arithmetic operators. However, the most energy-efficient Haar-9 hardware architecture employs a combination of two M=2 with five M=1 blocks with a efficient MCM architecture reduced to only two arithmetic operators.

An efficient architecture for carry select adder

PurposeAdders play a vital role in almost all digital designs, as all four arithmetic operations can be confined within addition. Hence, area and power optimization of the adders will result in overall circuit optimization. Being the fastest adder, the carry select adder (CSLA) gains higher importance among the different adder styles. However, it suffers from the drawback of increased power and area. The implementation of CSLA in digital circuits requires lots of study for optimization. Hence, to overcome this problem, various improvements were made to the CSLA structure to reduce area and, consequently, reduce power. Among these, modified CSLAs show a significant improvement, as they utilize a binary excess-1 code (BEC) to replace the add-one circuit.Design/methodology/approachThis paper presents further enhancement in the modified CSLA by proposing a decision-based CSLA, which activates BEC on demand. This leads to reduced switching activity. The performance of the proposal is done by analyzing and comparing it with different adders. The comparison is done on the basis of three performance parameters: area, speed and power consumption. This is done by implementing the architecture on Xilinx Virtex5 XC5VLX30 in Verilog environment and is synthesized using Cadence® RTL Compiler® using TSMC 180-nm CMOS cell library.FindingsOptimization of power, area and increasing the speed of operation are the three main areas of research in very-large-scale integration (VLSI) design for portable devices. As adders are the most fundamental units for any VLSI design, optimization at the adder level has a huge impact on the overall circuit. The modified CSLA has a BEC which continuously switches irrespective of the previous carry bit generated. The unwanted switching results in excess power consumption while also introducing additional delay. Hence, the author has proposed a decider circuit to avoid this excess switching activity. This allows switching of the BEC only when a previous carry is generated. The modified CSLA is based on the ripple carry adder, while the decider-based CSLA utilizes a carry look-ahead adder. This makes a decider-based CSLA faster while utilizing less area and power consumption when compared to the modified CSLA.Originality/valueThe efficiency of the proposed decider-based CSLA has been verified using Cadence RTL Compiler using TSMC 180-nm CMOS cell library and has been found to have 17 per cent power and 11.57 per cent area optimization when compared to the modified CSLA, while maintaining operating frequency.

A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register

This brief presents a fast-acquisition 11-bit all-digital delay-locked loop (ADDLL) using a novel starting-bit prediction algorithm for the successive-approximation register (SBP-SAR). It can effectively eliminate the harmonic lock and the false lock. The achievable acquisition time is within 17.5–23.5 or 17.5–32.5 clock cycles when the ADDLL works at the low or high clock rate, respectively. The digital-controlled delay line and the SBP-SAR of the ADDLL chip are synthesized using Taiwan Semiconductor Manufacturing Company’s (TSMC’s) 0.18- $\mu \text{m}$ CMOS cell library. The proposed ADDLL can operate at a clock frequency from 60 MHz to 1.1 GHz.

Enhanced pipelined architecture of H.264/AVC intra prediction

This paper presents a high-performance encoder for H.264/AVC intra prediction. Due to long data dependency loop of intra 4×4 prediction and complex algorithms, improving encoding speed turns into a stumbling block we have to face. To solve this problem, we first propose a pipelined method in and between macro blocks with new block processing order to accelerate the encoding speed. Benefiting from the pipelined method, reconstructed pixels of up-right blocks are available for two blocks in a macro block which could not take advantage of reconstructed pixels of up-right blocks in JM. So diagonal down left mode and vertical left mode are effective for these two blocks, which ultimately achieves a better bit-rate. Secondly, all 4×4 mode formula sharing method is proposed to reduce the redundancy of predicting formulas. Thirdly, streamlined reconstruction method is applied to improve the performance of reconstruction. CAVLC encoder with three parallel units is proposed to improve entropy coding speed significantly. As a result, it takes 268 cycles to encode a macro block. The experimental results indicate that synthesized into a 0.18µm CMOS cell library, the new architecture only requires about 238K gates and it is able to encode 1080pHD video sequences at 30 frames per second (fps), at the operating frequency of 56MHz.

ENGLISH

Many of the current wireline networks are digitalized, In Japan, a synchronous digital hierarchy (SDH) system is installed in the public switched telephone network, and appliance data are transferred with a synchronous transfer module (STM). In this system to put together the advanced STM-16 using the CMOS technology in the technique. The STMs are constructed hierarchically with a nested structure. When commerce with the data for high-speed digital services, a nested level of four is required for each STM; that is, the lowest level of container, virtual container, administrative unit (AU), AU group, and STM. The VLSI has two kinds of I/O ports; one serial port operating at 2.5 Gb/s/pin and sixteen 8-b parallel ports operating at 19.5 Mb/s/pin. The high-speed port is connected to the set of connections side, while the lowspeed ports are connected to the fatal sides including tool switches.Using CMOS technique with STM-16 frame termination VLSI, the power utilization during the sampled by is 34 mW, and that for 2.5Gb/s operation is 1.2w at 25 °C.the proposed Gate Diffusion Technique(GDI) allows reducing power consumption, delay and area of digital circuits, while maintaining low difficulty of logic design.A multiplicity of logic gates have been implemented in 0.35 μm technology to compare the GDI technique with CMOS and PTL. A prototype test chip of STM-16 has been fabricated, based on GDI and CMOS cell libraries, showing up to 45% reduction in power-delay product in GDI.

Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line

Previous high-performance delay-locked loops (DLLs) were designed in a full-custom design flow that is labor-intensive. Most of those DLLs require tens to hundreds of clock cycles to achieve synchronization of the clock signal. This paper presents an all-digital DLL (ADDLL) with constant acquisition cycles in a cell-based design flow. The proposed ADDLL circuit can acquire the phase of a clock signal from 60-MHz frequency to 1.2-GHz frequency. In this paper, the digitally controlled delay line (DCDL) is resettable such that our constant acquisition-cycle DLL algorithm can apply. This paper realizes the DCDL using lattice delay units in a linear manner, so the delay profile of our DCDL shows good linearity. On the other hand, the proposed ADDLL algorithm can effectively eliminate the harmonic lock. The ADDLL chip is implemented using the Artisan-TSMC-0.18- $\mu{\rm m}$ CMOS cell library. The measured power consumption of the chip is 16.2 mW at 1.2-GHz clock frequency and at 1.8 V supply voltage. The rms jitter is 1.63 ps and the peak-to-peak jitter is 12.8 ps. Both are measured at 1.2-GHz clock frequency.

개선된 정규화 최소합 알고리듬을 적용한 WiMAX/WLAN용 LDPC 복호기

A hardware design of LDPC decoder which is based on the improved normalized min-sum(INMS) decoding algorithm is described in this paper. The designed LDPC decoder supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. The decoding function unit(DFU) which is a main arithmetic block is implemented using sign-magnitude(SM) arithmetic and INMS decoding algorithm to optimize hardware complexity and decoding performance. The LDPC decoder synthesized using a 0.18-㎛ CMOS cell library with 100 MHz clock has 284,409 gates and RAM of 62,976 bits, and it is verified by FPGA implementation. The estimated performance depending on code rate and block length is about 82 ~ 218 Mbps at 100 MHz@1.8V

WiMAX/WLAN용 다중표준 LDPC 복호기 설계

본 논문에서는 IEEE 802.16e 모바일 WiMAX 표준의 19가지 블록길이(576~2304)에 따른 6가지 부호율(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6)과 IEEE 802.11n WLAN 표준의 3가지 블록길이(648, 1296, 1944)에 따른 4가지 부호율(1/2, 2/3, 3/4, 5/6)을 지원하는 다중표준 LDPC 복호기를 설계하였다. Layered 복호방식의 블록-시리얼(부분병렬) 구조와 SM(sign-magnitude) 수체계 기반의 DFU(decoding function unit)를 적용하여 하드웨어 복잡도를 최소화시켰다. 설계된 회로는 FPGA 구현을 통해 하드웨어 동작을 검증하였으며, 0.13-<TEX>${\mu}m$</TEX> CMOS 셀 라이브러리로 합성한 결과 약 312,000 게이트와 70,000 비트의 메모리로 구현되었고, 100 MHz@1.8V로 동작하여 79~210 Mbps의 성능을 갖는 것으로 평가되었다. This paper describes a multi-standard LDPC decoder which supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A DFU(decoding function unit) based on sign-magnitude arithmetic is used for hardware reduction. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.13-<TEX>${\mu}m$</TEX> CMOS cell library. It has 312,000 gates and 70,000 bits RAM. The estimated throughput is about 79~210 Mbps at 100 MHz@1.8v.

4가지 운영모드와 3가지 마스터 키 길이를 지원하는 블록암호 알고리듬 ARIA의 효율적인 하드웨어 구현

국가표준으로 제정된 블록암호 알고리듬 ARIA의 효율적인 하드웨어 구현에 대해 기술한다. 본 논문의 ARIA 암 복호 프로세서는 표준에 제시된 3가지 마스터 키 길이 128/192/256-비트와 ECB, CBC, OFB, CTR의 4가지 운영모드를 지원하도록 설계되었다. 키 확장 초기화 과정과 암 복호 과정에 사용되는 라운드 함수가 공유되도록 설계를 최적화 하였으며, 이를 통해 게이트 수를 약 20% 감소시켰다. 설계된 ARIA 암 복호 프로세서를 FPGA로 구현하여 하드웨어 동작을 검증하였으며, <TEX>$0.13-{\mu}m$</TEX> CMOS 표준셀로 합성한 결과 46,100 게이트로 구현되었다. 레이아웃의 면적은 <TEX>$684-{\mu}m{\times}684-{\mu}m$</TEX> 이며, 200 MHz@1.2V로 동작하여 1.28 Gbps의 성능을 갖는 것으로 평가되었다. This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a <TEX>$0.13-{\mu}m$</TEX> CMOS cell library. It has 46,100 gates on an area of <TEX>$684-{\mu}m{\times}684-{\mu}m$</TEX> and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.

A Multi-mode LDPC Decoder for IEEE 802.16e Mobile WiMAX

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18- m CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V

경계선 보존 알고리즘 기반의 디블로킹 필터와 효율적인 VLSI 구조

본 논문은 새로운 경계선 보존 알고리즘을 이용하여 블록화 현상을 제거하는 디블로킹 필터와 HD해상도의 실시간 영상처리가 가능한 디블로킹 필터의 VLSI구조를 제안한다. 기존의 블록 분류 기반의 접근 방법과 달리 제안된 알고리즘은 픽셀 분류 기반 접근을 사용한다. 또한 제안된 경계선 보존 맵은 픽셀을 경계선 영역과 평탄 영역으로 분류하며, 블록화 현상 제거에 사용되는 오프셋 필터와 경계선 보존 필터의 기반이 된다. 이를 바탕으로 제안된 디블로킹 필터의 VLSI구조는 고연산량 처리를 위하여 블록 전체에 파이프라인 기법을 적용하였다. 또한 블록 버퍼를 위한 메모리 절감 구조는 메모리의 사용을 최적화 시킨다. 본 필터는 VHDL을 이용한 설계를 통하여 CycloneII FPGA상에서 구현된 구조의 동작을 검증 후, Synopsys의 Design Compiler와 ANAM 0.25 <TEX>${\mu}m$</TEX> CMOS cell library로 합성하여 칩으로 구현하였을 때의 성능을 예측하였다. 제안된 알고리즘의 실험 결과는 세밀한 영상성분을 보존하면서 효과적으로 블록화 현상을 제거하며, 픽셀 분류 기반에서 제안된 알고리즘은 블록 분류 기반보다 PSNR 성능이 우수함을 보였다. This paper presents a new edge-preserving algorithm and its VLSI architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-preserving maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is prototyped on FPGA Cyclone II, and then we estimated performance when the filter is synthesized on ANAM 0.25 <TEX>${\mu}m$</TEX> CMOS cell library using Synopsys Design Compiler. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details.

Sign-magnitude 수체계 기반의 WiMAX용 다중모드 LDPC 복호기 설계

WiMAX, WLAN 등의 무선통신 시스템에 사용되는 LDPC(low density parity check) 복호기의 핵심 기능블록인 DFU(decoding function unit)의 회로 최적화를 제안한다. DFU를 2의 보수 연산 대신에 sign-magnitude 연산 기반으로 설계함으로써 수체계 변환과정을 제거하였으며, 모바일 WiMAX용 다중모드 LDPC 복호기에 사용되는 96개 DFU 배열의 게이트 수를 18% 감소시켰다. 제안된 DFU 구조를 적용하여 모바일 WiMAX 표준을 지원하는 다중모드 LDPC 복호기를 설계하였다. 설계된 LDPC 복호기는 0.18-<TEX>${\mu}m$</TEX> CMOS 셀 라이브러리를 이용하여 50 MHz 클록주파수로 합성한 결과 268,870 게이트와 71,424 비트의 메모리로 구현되었으며, FPGA 구현을 통해 하드웨어 동작을 검증 하였다. This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems including WiMAX and WLAN. A new design of DFU based on sign-magnitude arithmetic instead of two's complement arithmetic is proposed, resulting in 18% reduction of gate count for 96 DFUs array used in mobile WiMAX LDPC decoder. A multi-mode LDPC decoder for mobile WiMAX standard is designed using the proposed DFU. The LDPC decoder synthesized using a 0.18-<TEX>${\mu}m$</TEX> CMOS cell library with 50 MHz clock has 268,870 gates and 71,424 bits RAM, and it is verified by FPGA implementation.

다항식 표현을 이용한 DCME 알고리즘 설계

본 논문에서는 고속 RS(Reed-Solomon) 복호기의 KES(Key Equation Solver) 블록 구현에 ME(Modified Euclidean) 알고리즘을 효율적으로 설계할 수 있는 구조를 제안하고 구현하였다. 제안된 구조에서는 각 PE(Processing Element) 블록을 제어하기 위해 새로운 상대변수를 정의하고 다항식으로 표현함으로써, 입출력 신호가 간단해지고, 차수계산회로가 필요 없기 때문에 회로의 복잡도를 줄일 수 있다. 또한, PE 회로가 오류 정정 능력 t와 무관하기 때문에, t가 증가함에 따라 KES 블록의 하드웨어 복잡도가 선형적으로 증가하는 장점을 가진다. 제안된 구조와 기존의 구조를 비교하기 위해, RS(255,239,8) 복호기에 대한 KES 블록을 구현하고, 0.13um CMOS cell library를 이용하여 합성하였다. 실험 결과로부터, 제안된 구조를 이용하여 적은 gate count로 고속 RS 복호기 구현이 가능함을 알 수 있다. In this paper, we have proposed and implemented a novel architecture which can be used to effectively design the modified Euclidean (ME) algorithm for key equation solver (KES) block in high-speed Reed-Solomon (RS) decoder. With polynomial expressions of newly-defined state variables for controlling each processing element (PE), the proposed architecture has simple input/output signals and requires less hardware complexity because no degree computation circuits are needed. In addition, since each PE circuit is independent of the error correcting capability t of RS codes, it has the advantage of linearly increase of the hardware complexity of KES block as t increases. For comparisons, KES block for RS(255,239,8) decoder is implemented using Verilog HDL and synthesized with 0.13um CMOS cell library. From the results, we can see that the proposed architecture can be used for a high-speed RS decoder with less gate count.

64비트 블록암호 알고리듬 HIGHT의 효율적인 하드웨어 구현

한국기술표준원(KATS)과 국제표준화기구(ISO/IEC)에 의해 표준으로 채택된 블록암호 알고리듬 HIGHT용 저면적/저전력 암호/복호 코어를 설계하였다. HIGHT 알고리듬은 USN, RFID와 같은 유비쿼터스 환경에 적합하도록 개발되었으며, 128 비트 마스터 키를 사용하여 64 비트 평문을 64 비트 암호문으로, 또는 그 역으로 변환한다. 저면적과 저전력 구현을 위해 암호화 및 복호화를 위한 라운드 변환 블록과 키 스케줄러의 하드웨어 자원이 공유되도록 설계를 최적화하였다. 0.35-<TEX>${\mu}m$</TEX> CMOS 표준 셀 라이브러리를 이용한 합성결과, HIGHT64 코어는 3,226 게이트로 구현되었으며, 80-MHz@2.5-V로 동작하여 150-Mbps의 성능을 갖는 것으로 평가되었다. This paper describes a design of area-efficient/low-power cryptographic processor for HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a 0.35-<TEX>${\mu}m$</TEX> CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

다중 블록길이와 부호율을 지원하는 IEEE 802.11n용 LDPC 복호기

본 논문에서는 IEEE 802.11n 무선 랜 표준에 규정된 3가지 블록길이(648, 1296, 1944)와 4가지 부호율(1/2, 2/3, 3/4, 5/6)을 지원하는 LDPC 복호기를 최소합 알고리듬과 layered 복호방식을 적용하여 설계하였다. 검사노드 값과 패리티 검사 행렬 정보의 효율적인 저장방법을 통해 메모리 용량을 최소화하였으며, 또한 효율적인 검사노드 메모리 어드레싱 방법을 적용하여 stall 없이 메모리 읽기/쓰기가 가능하도록 하였다. 설계된 회로는 FPGA 구현을 통해 하드웨어 동작을 검증하였으며, <TEX>$0.18-{\mu}m$</TEX> CMOS 셀 라이브러리로 합성한 결과 219,100 게이트와 45,036 비트의 메모리로 구현되었고, 50 MHz@2.5V로 동작하여 164～212 Mbps의 성능을 갖는 것으로 평가되었다. This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a <TEX>$0.18-{\mu}m$</TEX> CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD Video

H.264/AVC intra-frame encoding contains several computation-intensive coding tools that form a long data dependency loop that is difficult to speed up. In this paper, we present a low-power and high-performance H.264/AVC intra-frame encoder. We propose several novel approaches to alleviate the performance bottleneck caused by the long data dependency loop among 4 × 4 luma blocks, integrate an efficient CABAC entropy encoder, and apply a clock-gating technique to reduce power consumption. Synthesized into a TSMC 0.13 μm CMOS cell library, our design requires 265.3 K gates at 114 MHz and consumes 23.56 mW to encode 1080pHD (1920 × 1088) video sequences at 30 frames per second (fps). It also delivers the same video quality as the H.264/AVC reference software. Compared with all state-of-the-art designs, our design has a lower working frequency and achieves both better bit-rate saving and lower power consumption.

IEEE 802.16e WiMAX용 부호율 1/2, 2304-비트 LDPC 복호기

모바일 WiMAX 표준 IEEE 802.16e의 블록길이 2,304 비트, 부호율 1/2을 지원하는 LDPC(low-density parity-check) 복호기를 설계하였다. 설계된 LDPC 복호기는 최소-합(min-sum) 알고리듬과 layered 복호를 기반으로 <TEX>$96{\times}96$</TEX> 크기의 부행렬을 병렬로 처리하는 부분병렬 구조를 갖는다. 최소-합 알고리듬의 특징을 이용하여 메모리 용량을 감소시킬 수 있는 새로운 방법을 고안하여 적용함으로써 검사노드 메모리 용량을 기존의 방법보다 46% 감소시켰다. Verilog HDL로 설계된 LDPC 복호기를 <TEX>$0.18{\mu}m$</TEX> CMOS 셀 라이브러리로 합성한 결과 174,181개의 게이트와 52,992 비프의 메모리로 구현되었으며, Eb/No=2.1dB의 AWGN 채널에 대해 평균 비트 오율 (BER)는 <TEX>$4.34{\times}10^{-5}$</TEX>이고, 100 MHz@1.8-V로 동작하여 약 417 Mbps의 성능을 갖는다. This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of <TEX>$96{\times}96$</TEX> in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of <TEX>$4.34{\times}10^{-5}$</TEX> for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a <TEX>$0.18{\mu}m$</TEX> CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

Edge-Preserving Algorithm for Block Artifact Reduction and Its Pipelined Architecture

This paper presents a new edge-protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-protection maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 µm CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.