CMOS Bandgap Reference Circuit Research Articles

A New Piecewise-Compensated Bandgap Reference Circuit with a Trimming Procedure

A new CMOS bandgap reference (BGR) circuit with a piecewise-compensation circuit and a trimming network is proposed and designed to obtain a bandgap reference voltage with a low-temperature coefficient and a high precision, taking into account the effect of non-ideal factors on the results. The proposed piecewise compensation circuit is designed to achieve a constant reference voltage by using a current mirror to mirror the current, combined with a subtractive circuit and an additive circuit to obtain a low-temperature coefficient over an extensive temperature range. The trim network part is used to change the voltage value of the output reference by controlling the magnitude of the resistance value of the resistors connected to the circuit. The design and simulation of the proposed bandgap reference circuit are obtained by using Cadence Spectre simulation by SMIC 0.18 μm CMOS technology. The results indicates that when the power is 3.3 V and the temperature scope is within -40 °C to 125 °C, the output voltage is 1.2 V with the temperature coefficient equal to 0.658 ppm/°C. When the power varies within 3.2 V to 3.4 V, the linear regulating rate is 0.001019 %/V.

A Sub-1-V 8.5-ppm/°C Sampled Bandgap Voltage Reference

This brief proposes a novel sub-1V discrete-time CMOS bandgap reference circuit where a constant voltage is produced by summation of a CTAT and a PTAT voltage that are sampled onto a capacitor. By sampling the voltages onto a capacitor, we eliminate the need for an opamp in the bandgap core, which tends to be the dominant source of noise and offset concerns in low voltage bandgap designs in scaled technologies. A prototype was designed and fabricated in 28nm TSMC HPC+ technology with a nominal output voltage of 108mV. It demonstrates a temperature coefficient of 8.5ppm/°C between −40°C and 125°C, and occupies an area of 0.0075mm2 while consuming <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.6\mu \text{W}$ </tex-math></inline-formula> of power.

A CMOS Bandgap Reference Circuit with a Temperature Coefficient Adjustment Block

A bandgap reference voltage source with a temperature coefficient adjustment block was proposed. The bandgap topology employs current summation and the circuit was designed through metaheuristic algorithms in a 0.35-mm CMOS technology. Simulations with typical parameters show that the designed circuit has temperature coefficient of 15 ppm/0C, line regulation of 263 ppm/V, and current consumption of 2.71 uA in 1.0 V power supply. An additional 3-bit temperature adjustment block allowed keeping the temperature coefficient values lower than 26.6 ppm/0C for 90% of the circuits, without interfering with the reference voltage output or line regulation values.

A 1.16-V 5.8-to-13.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference Circuit With a Shared Offset-Cancellation Method for Internal Amplifiers

This article introduces an accurate current-mode bandgap reference circuit design with a novel shared offset compensation scheme for its internal amplifiers. This bandgap circuit has been designed to operate over a very wide temperature range from −40 °C to 150 °C. Its output voltage is 1.16 V with a 3.3-V supply voltage. A multi-section curvature compensation method alleviates the error from the bipolar junction transistor’s base–emitter nonlinear voltage dependence on temperature. The bandgap reference circuit contains two operational amplifiers that are utilized to generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) current sources. With the implementation of the described shared offset-cancellation methodology, the simulated output inaccuracy introduced by the amplifier is kept to a 5 $\sigma $ offset within ±4.6 $\mu \text{V}$ while allowing to conserve die size and power consumption by preventing that each amplifier is accompanied by its own active auxiliary offset-cancellation circuit. Designed and fabricated in a 130-nm CMOS process technology, the bandgap reference has a measured output voltage shift of less than 1 mV over a −40 °C to 150 °C temperature range and an overall variation of ±8.2 mV across seven measured samples without trimming.

A 24.4 ppm/°C Voltage Mode Bandgap Reference With a 1.05V Supply

This brief proposes a sub-1V, voltage mode CMOS bandgap reference circuit. Conventionally, sub-1V references are obtained by converting PTAT and CTAT voltages to currents and summing them in the current domain. Such techniques have multiple operating points and cannot natively support applications that require PTAT currents in addition to a bandgap voltage. This brief presents a voltage mode reference circuit, which adds a PTAT voltage with a scaled version of a CTAT voltage all within the sub-1V domain. Compared to current mode bandgaps, summing in voltage domain enables reduction of one CTAT current mirror stage and a significant reduction in PTAT current mirror ratio resulting in a reduced number of error sources. In addition, this circuit also natively supports applications that require PTAT current. A novel, high-accuracy self-biasing technique has been adopted to minimize the systematic offset induced temperature coefficient. A prototype designed in 45nm TSMC CMOS technology for a nominal voltage of 500mV demonstrates 24.4ppm/°C temperature coefficient from -40°C to 125°C, 0.15% line regulation, and draws 7.2μ\textA from a 1.05V supply.

A tunable low noise high PSRR high accuracy bandgap reference using stacked-long cascode technique in 14 ​nm FinFET process

A tunable CMOS bandgap reference circuit is presented. To improve the match performance of the current mirror, the proposed bandgap is realized with stacked-long Cascode technique. A detailed analysis of various error sources is provided and the techniques to reduce them are discussed. The bandgap reference with an accuracy of ±1.2% from −40 ​°C to 125 ​°C draws 57μA from a 1.8 ​V supply, and occupied 0.0036 ​mm2 in a 14 ​nm FinFET Process. The output noise is 0.76μV (rms) and the PSRR is −115dB@DC.

Design of programmable bandgap reference current source with high precision

A new programmable CMOS bandgap reference circuit of high precision is proposed. The whole circuit was designed with 0.18um standard CMOS technology, and the simulation results show that the movement of reference voltage is 3.2mV while the temperature is range -40°C from 120 °C. The circuit has been successfully applied in 14-bit high speed DAC, while the output current range of DAC is 8-32mA.

A 1.2-V 4.2-&lt;formula formulatype="inline"&gt; &lt;tex Notation="TeX"&gt;$\hbox{ppm}/^{\circ}\hbox{C}$&lt;/tex&gt;&lt;/formula&gt; High-Order Curvature-Compensated CMOS Bandgap Reference

This study presents a high-precision CMOS bandgap reference (BGR) circuit with low supply voltage. The proposed BGR circuit consists of two BGR cores and a curvature correction circuit, which includes a current mirror and a summing circuit. Two BGR cores adopt conventional structures with the curvature-down characteristics. A current-mirror circuit is proposed to implement one of the BGR cores to have the curvature-up characteristic. Selection of the appropriate resistances in the BGR cores results in one reference voltage with a well balanced curvature-down characteristic and another reference voltage with an evenly balanced curvature-up characteristic. The summation of these reference voltages is proposed to achieve a high-order curvature compensation. This curvature correction circuit causes the proposed BGR circuit without any trimming to show a measured temperature coefficient (TC) as low as 4.2 ppm/°C over a wide temperature range of 160 °C (-40 ~ 120 °C) at a power supply voltage of 1.2 V. The average TC for 8 random samples is approximately 9.3 ppm/°C. The measured power-supply rejection ratio (PSRR) of -30 dB is achieved at the frequency of 100 kHz. The total chip size is 0.063 mm 2 with a standard 0.13-μm CMOS process.

A Bandgap Reference with High Order Temperature Compensation

A kind of CMOS bandgap reference circuit with high order temperature compensation is introduced [1]. Compared to the traditional circuit, the bandgap reference proposed here has several advantages such as better temperature stability, smaller chip area, lower power consumption, self-power-on, and so on. Our design can be used in analog-to-digital or digital-to-analog converters, where high performance bandgap reference is required.

Design of sub-1-V CMOS bandgap reference circuit using only one BJT

This paper describes new CMOS bandgap reference (BGR) circuits capable of providing sub-1-V voltage reference while using only one BJT. The circuits use the concept of reverse bandgap voltage principle (RBVP) to generate attenuated versions of the silicon bandgap voltage of 1.205 V. Also, as opposed to the previously known sub-1-V BGR by Banba et al. (IEEE J Solid State Circuits 34:670---674, 1999), the circuits can be operated with lower supply voltage down to a 1.3 V supply. Based on the scheme, a 550 mV BGR is implemented in 65 nm CMOS process, with peak-to-peak variation of 7.19 mV across devices corners, temperature range of ?20 to 80° and supply range of 1.6---2.0 V.

An improvement of a piecewise curvature-corrected CMOS bandgap reference

In the current paper, an improvement of piecewise curvature-corrected CMOS bandgap reference (BGR) circuit is proposed. The circuit utilizes piecewise nonlinear curvature-corrected current (PNCCC) in a conventional BGR with a current control circuit, which compensates for the voltage reference at a higher temperature range. The current control circuit (CCC) is used to reduce the total current at low temperature when the PNCCC generator is inactive. The proposed circuit is realized in CMOS 0.13µm and has been verified to be able to save power consumption by 18.6% compared with a circuit without the current control circuit.

Generating sub-1V reference voltages from a resistorless CMOS bandgap reference circuit by using a piecewise curvature temperature compensation technique

A piecewise curvature compensated CMOS voltage reference that is able to generate a sub-1V reference voltage is presented. The presented voltage reference circuit is operated at a minimum operating voltage of 1.5 V (theoretically 1.408 V) and generates a stable 0.658 V reference voltage with a temperature coefficient of 9.617 ppm/°C over the temperature range of −10 °C to 130 °C. When implemented in a 0.18 μm CMOS technology, the presented design occupies a compact silicon area of 0.022 mm 2. Spectre SPICE simulation showed that the presented design achieves a line regulation of 0.89%, a power supply rejection ratio of −42.3 dB, a power consumption of 0.449 mW at 1.8 V power supply and a high immunity to process variation.

A low power CMOS voltage reference circuit with sub threshold MOSFETs

In this paper, a novel approach is proposed for the design of low power CMOS band gap reference circuit. In the literature, an inversion technique is proposed to make the voltage reference to be independent of temperature by using parasitic bipolar transistors. In the above technique, this paper proposes the use of MOSFETs operating in sub threshold region for generating a voltage with negative temperature coefficient. The performance of the proposed scheme is studied by implementing the band gap reference circuit for 1.2 V in TSMC035 CMOS process. Studies through Mentorgraphics IC station and Eldo simulator demonstrate that the proposed scheme has a voltage reference with temperature coefficient of less than 50 ppm/°C over the temperature range of −10°C to 120°C. The proposed scheme results in 18 times lesser area and dissipates ten times lower power compared with that using parasitic bipolar transistors. The circuit technique has been validated using both NMOS and PMOS diode connected sub threshold MOSFETs for generating voltages with negative temperature coefficient.

Sub-1-V-Output CMOS bandgap reference circuit with small area and low power consumption

In this paper, a new low-VDD CMOS bandgap reference circuit with small layout area and low power consumption is proposed. The proposed circuit delivering its output voltage below 1V has its Proportional-To-Absolute-Temperature (PTAT) term compensated by the Complementary-proportional-To-Absolute- Temperature (CTAT) voltage thereby suppressing a change in its output voltage regardless of temperature and VDD variations. Using a commercial CMOS 0.18-µ m process, the proposed circuit has been verified to be able to save its layout area by 48.7% and the power consumption by 29.9% compared with the previous sub-1-V-output bandgap circuit.

The Realization of an Area-Efficient CMOS Bandgap Reference Circuit with Less than 1.25 V of Output Voltage Using a Fractional VBE Amplification Scheme

This paper describes a CMOS voltage reference circuit which occupies small die area and has less than 1.25 V of output voltage. The reference voltage is determined by a resistor ratio, and it is possible to set the reference voltage from zero to near the supply voltage with the same temperature independence as those of Widlar's and Brokaw's bandgap voltage references. The temperature-independent reference voltage is formed by adding two voltages: the amplified fractional V BE (base-to-emitter voltage) of a bipolar transistor with a negative TC (temperature coefficient) and the amplified V T (thermal voltage) with a positive TC. When a reference voltage smaller than 1.25V is required, the voltage gain of the amplifier for V BE becomes less than one, and the voltage gain of the amplifier for V T becomes small. This enables the size of bipolar transistors for V T generation to be small. The proposed voltage reference circuit was implemented in a standard 0.35-pm CMOS technology. A temperature-independent current source was also obtained from the same circuit. The results were a TC (temperature coefficient) of46ppm/°C over 130°C change, a line regulation of 2.2 mV/V for the 0.5 V reference voltage with 8.7 7μA of current consumption in the voltage reference part, and a 6% change over 130°C change for the 13μA current source.

Reduction of EMI Susceptibility in CMOS Bandgap Reference Circuits

This paper presents a successful approach to increase the electromagnetic interference (EMI) immunity of CMOS bandgap reference circuits. Layout techniques along with some changes in the reference schematics lead to a robust electromagnetic immunity, preserving good overall performances. Measurement results confirm the low susceptibility of the proposed circuits. They exhibit only a few millivolts shift, for interfering signals of 1 Vpp in the frequency range of 1 MHz to 4 GHz, compared to the classical topologies that may reach more than 1 V. The circuits were fabricated in a 0.8-mum standard CMOS technology

A CMOS bandgap reference circuit with sub-1-V operation

This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply, In the conventional BGR circuit, the output voltage V/sub ref/ is the sum of the built-in voltage of the diode V/sub f/ and the thermal voltage V/sub T/ of kT/q multiplied by a constant. Therefore, V/sub ref/ is about 1.25 V, which limits a low supply-voltage operation below 1 V. Conversely, in the proposed BGR circuit, V/sub ref/ has been converted from the sum of two currents; one is proportional to V/sub f/ and the other is proportional to V/sub T/. An experimental BGR circuit, which is simply composed of a CMOS op-amp, diodes, and resistors, has been fabricated in a conventional 0.4-/spl mu/m flash memory process. Measured V/sub ref/ is 518/spl plusmn/15 mV (3/spl sigma/) for 23 samples on the same wafer at 27-125/spl deg/C.