CMOS Analog Front-end Research Articles

Design of CMOS Analog Front-End Local-Field Potential Chopper Amplifier With Stimulation Artifact Tolerance for Real-Time Closed-Loop Deep Brain Stimulation SoC Applications.

A CMOS analog front-end (AFE) local-field potential (LFP) chopper amplifier with stimulation artifact tolerance, improved right-leg driven (RLD) circuit, and improved auxiliary path is proposed. In the proposed CMOS AFE LFP chopper amplifier, common-mode artifact voltage (CMAV) and differential-mode artifact voltage (DMAV) removal using the analog template removal method are proposed to achieve good signal linearity during stimulation. An improved auxiliary path is employed to boost the input impedance and allow the negative stimulation artifact voltage passing through. The common-mode noise is suppressed by the improved RLD circuit. The chip is implemented in 0.18- μm CMOS technology and the total chip area is 5.46-mm2. With the improved auxiliary path, the measured input impedance is larger than 133 M[Formula: see text] in the signal bandwidth and reaches 8.2 G[Formula: see text] at DC. With the improved RLD circuit, the measured CMRR is 131 - 144 dB in the signal bandwidth. Under 60-μs pulse width and 130-Hz constant current stimulation (CCS) with ±1-V CMAV and ±50-mV DMAV, the measured THD at the SC Amp output of fabricated AFE LFP chopper amplifier is 1.28%. The measurement results of In vitro agar tests have shown that with ±1.6-mA CCS pulses injecting to agar, the measured THD is 1.69%. Experimental results of both electrical and agar tests have verified that the proposed AFE LFP chopper amplifier has good stimulation artifact tolerance. The proposed CMOS AFE LFP chopper amplifier with analog template removal method is suitable for real-time closed-loop deep drain stimulation (DBS) SoC applications.

A 296 nJ Energy-per-Measurement Relaxation Oscillator-Based Analog Front-End for Chemiresistive Sensors

An energy-efficient, wide dynamic-range (DR) CMOS analog front-end (AFE) for chemiresistive sensors is presented. The circuit is specifically designed for the Metal Oxide (MOX) gas sensors, a special technology of chemiresistive sensors, broadly diffused in modern portable devices due to their low-cost and simplicity of use. Energy efficiency is mandatory for the AFE in order to prolong the battery life that supply these devices. The proposed circuit implements the resistance-to-time (R-to-T) conversion of the sensor's resistance by adopting a relaxation oscillator-based architecture. A limiting resistor in series with the sensor is introduced for reducing the circuit's energy-per-measurement (EpM), while mitigating the error due to the sensor's parasitic capacitance. The analysis of the circuit is presented with emphasis on the design trade-off between error due to the sensor's parasitic capacitance and power consumption on one side and read-out sensitivity on the other. The chip prototype is realized in AMS 0.35μm process and has been tested in the DR between 100Ω and 4.7MΩ with an accuracy less than 0.1% and a precision less than 0.029%. The efficacy of the presented AFE is proved by adopting the circuit in a real chemical environment with a commercial sensor. The proposed AFE shows a maximum EpM of 296nJ which is three times better than the state of the art.

An analog correlator based CMOS analog front end with digital gain control circuit for hearing aid devices

In this paper, an analog correlator based analog front end with gain control circuit for hearing aid devices is designed and fabricated with 0.18 $$\upmu \mathrm{m}$$ CMOS process. The proposed analog front end consists of an analog correlator comprised of a multiplier, an integrator, and a mixed mode variable gain amplifier. The analog correlator is utilized to ensure the low input referred noise. A gain control circuit is implemented in variable gain amplifier. Based on the output of piezoelectric microphone, designed gain control circuit automatically sets the gain. The investigated analog front end offers lower noise and wider dynamic range with compact size compared to conventional architecture. It achieves a 42 $$\mathrm{n}V_{rms}$$ input referred noise and 84 dB signal to noise ratio. The total area of the designed analog front end circuit is 386 $$\upmu \mathrm{m}$$ $$\times$$ 569 $$\upmu \mathrm{m}$$ . Designed circuit is interfaced with a sensor model of piezoelectric microphone and its performance is successfully verified against simulation results.

High Input Impedance Low-Noise CMOS Analog Frontend IC for Wearable Electrocardiogram Monitoring

This brief presents a CMOS analog frontend (AFE) IC with high input impedance low input-referred noise, which for wearable electrocardiogram monitoring. The IC has three main parts, pseudo-differential chopper-stabilized instrumentation amplifier, switched capacitor filter, and low-power continuous–time <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${{\Sigma}} {{\Delta }}$ </tex-math></inline-formula> modulator. The pseudo-differential structure with chopper stabilization improves the input impedance, input–referred noise and chip area. Notably, we propose a new type of negative capacitor circuit to further boost the input impedance. Furthermore, the auto-zero technique is applied to the ripple reduction loop for suppressing the second harmonic ripple and maintain operation throughout the loop cycle. A dc servo loop suppresses the electrode dc offset. In <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS process, the proposed AFE IC occupies an active area of 0.99 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , consumes 5.8/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$46.6~\mu \text{A}$ </tex-math></inline-formula> from a 1.8 V supply, and achieves an input impedance above 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{G}{{\Omega }}$ </tex-math></inline-formula> , a CMRR of 102 dB and a PSRR of 72 dB.

Low leakage and high CMRR CMOS differential amplifier for biomedical application

A novel, competent, effortless, low leakage CMOS differential amplifier is explored with minimum deformation and proper power utilization. The proposed circuit can also represent a CMOS analog front-end (AFE) circuit for portable biomedical signals acquisition system. The proposed circuit is designed with the intention of supply the power either from VDD to VOUT or from VSS to VOUT. The proposed circuit has high CMRR. It means that the common mode voltage gain is minimum and differential mode voltage gain is high. The circuit is designed in such a way that the power supply couldn’t reach from VDD to VSS directly i.e. the driving power of the circuit couldn’t be short circuited. Due to this, the proposed circuit behaves like a perfect differential amplifier. Competent and speculative combinations of CMOS logic are utilized with cross coupled by Gate terminals of NMOS transistors to provide the better functionality of proposed differential amplifier circuit. The proposed circuit with unique combination of MOS has provided better performance parameters. Due to utilization of modified MOS structure with pull-up and pull-down stacked transistors, gain factor of differential amplifier is increased up to 5 dB with compare to other differential amplifier circuits and leakage power dissipation is reduced up to 49%. Proposed CMOS based differential amplifier is optimized at 45 nm CMOS technology. The simulations have been performed using cadence analog virtuoso spectre simulator. The experimental implementations have been done for analysis of leakage power and efficiency with better consistency through the proposed circuit.

Design of a multi-frequency Bio-Impedance Spectroscopy system Analog Front-End and Digital Back-End with system on-chip implementation

In this paper, the design of an on-board and system on-chip Bio-Impedance Spectroscopy (BIS) mixed-signal system is presented. It consists of a Direct Digital Synthesis Sine-Wave Generator (DDS-SWG), an Analog Front-End (AFE), an Analog-Digital Converter (ADC), and a Digital Back-End implemented on a Field Programmable Gate Array (FPGA). The FPGA drives the ADC, the DDS-SWG, and the LCD. The AFE consists of a high output impedance Load-In-Loop Current Source (LL-CS) and High Common-Mode Rejection Ratio (CMRR) Instrumentation Amplifiers (IA). It uses a simple and straightforward impedance extraction algorithm using division and constant multiplication. Furthermore, a method that extends the AFE implementation to BIS tomography applications is presented offering low power dissipation and more chip area budget. The CMOS implementation of the AFE and the digital ASIC using TSMC 0.18µm 1P6M are also presented. The CMOS AFE has been optimized to dissipate low power even when operating at high frequency. The system forms part of a platform that aims to predict a urolithiasis (urinary stone) event where qualitative measures of K+, Ca2+, Cl− and Na+ concentrations in urine can be obtained through impedance/ conductivity.

Dual-mode CMOS analog front-end (AFE) for electrical impedance spectroscopy (EIS) systems.

This paper presents the operation of a dual-mode wideband CMOS analog front-end (AFE) for electrical impedance spectroscopy. The chip combines two current-readout (CR) channels and four voltage-readout (VR) channels suitable for both bipolar and tetrapolar EIS analysis. The chip addresses the need for flexible readout units for real-time simultaneous single-cell and large scale tissue/organ analysis. Postlayout simulations show that the VR channel is capable of wideband operation up to 12 MHz with noise floor as low as 16.4 nV/Hz1/2. A 2-bit control allows to select between a high-frequency low-gain channel and a bandwidth-limited high-gain channel. Each VR channel occupies an area of 0.48 mm2. The CR channel is capable of 80 dB of dynamic range, by converting currents between 1 nA to 10μA, while achieving a noise floor of 1.4 pA/Hz1/2. An automatic gain control (AGC) unit can be enabled in order maintain the sensor signal within the ADC dynamic range. Each CR channel occupies an area of 0.21 mm2. The chip consumes between 290 μA and 690 μA per channel and operates from a 1.8 V supply. The chip will be part of a fully flexible and configurable dual-mode EIS systems for impedance sensors and bioimpedance analysis.

A Low-Power CMOS Analog Front-End IC with Adjustable On-Chip Filters for Biosensors

This paper presents a low-power CMOS analog front-end (AFE) IC designed with a selectable on-chip dual AC/DC- coupled paths for bio-sensor applications. The DC-coupled path can be selected to sense a biosignal with useful DC information, and the AC-coupled path can be selected for sensing the AC content of the biosignal by attenuating the unwanted DC component. The AFE IC includes a DC-coupled instrumentation amplifier (INA), two variable-gain 1st-order low pass filters (LPF) with tunable cut-off frequencies, a fixed gain 2nd-order Sallen-Key high-pass filter (HPF) with tunable cut-off frequencies, a buffer and an 8-bit differential successive approximation register (SAR) ADC. The entire AFE channel is designed and fabricated in a proprietary 0.35-μm CMOS technology. Excluding an external buffer needed to properly drive the ADC, the measured AFE IC consumes only 2.37 μA/channel with an input referred noise of ~40 μVrms in [1 Hz, 1 kHz], and successfully displays proper ECG (electrocardiogram) and electrogram (EGM) waveforms for QRS peaks detection. We expect that the low-power dual-path design of this AFE IC can enable it to periodically record both the AC and the DC signals for proper sensing and calibration for various bio-sensing applications.

Designs of Large Liquid Argon TPCs — from MicroBooNE to LBNE LAr40

Abstract Liquid argon time projection chamber (LArTPC) is a unique technology well suited for large scale detectors of neutrinos and other rare processes. Its combination of millimeter scale 3D precision particle tracking and calorimetry with good dE/dx resolution provide excellent efficiency of particle identification and background rejection. MicroBooNE is a LArTPC about to enter its final design phase and is scheduled for construction in 2012. Its active volume contains 86 ton of LAr. It has a 2.6m drift distance, 8256 sense wires connected to cold CMOS analog front–end electronics. Most of the TPC design features improve upon existing tried and true techniques. The LAr40 is one of the two far detector options under consideration for the Long Baseline Neutrino Experiment (LBNE). Its conceptual design has 40 kton active liquid argon mass, to be installed underground at a moderate depth. Due to its large scale, and underground siting, great emphasis was placed on the detector cost and reliability. A modular TPC design is the key to achieve these goals. The LAr40 consists of two 20 kton detectors in one underground cavern. Each detector is in turn constructed from an array of TPC modules. Innovative concepts enable the modules to be tiled with minimal dead space. An overview of both detectors is presented. The designs of key elements in these two TPCs are described in detail.

A 1.2 V 12 b 60 MS/s CMOS Analog Front-End for Image Signal Processing Applications

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 μm CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 mm 2 and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.

A Fully Integrated 900-MHz Passive RFID Transponder Front End With Novel Zero-Threshold RF–DC Rectifier

This paper presents a fully integrated CMOS analog front end for a passive 900-MHz radio-frequency identification (RFID) transponder. The power supply in this front end is generated from the received RF electromagnetic energy by using an RF-dc voltage rectifier. In order to improve the compatibility with standard CMOS technology, Schottky diodes in conventional RF-dc rectifiers are replaced by diode-connected MOS transistors with zero threshold. Meanwhile, theoretical analyses for the proposed rectifier are provided and verified by both simulation and measurement results. The design considerations of the pulsewidth-modulation (PWM) demodulator and the backscatter modulator in the front end are also discussed for low-power applications. The proposed front end is implemented in a 0.35-mum 2P4M CMOS technology. The whole chip occupies a die area of 490 times 780 mum2 and consumes only 2.1 muW in reading mode under a self-generated 1.5-V supply voltage. The measurement results show that the proposed rectifier can properly operate with a -14.7-dBm input RF power at a power conversion efficiency of 13.0%. In the proposed RFID applications, this sensitivity corresponds to 10.88-m communication distance at 4-W equivalent isotropically radiated power from a reader base station.

Full CMOS Single Supply PLC SoC ASIC with Integrated Analog Front-End

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ㎛ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 ㎃ at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 x 2.8 ㎟.

A CMOS analog front-end for silicon pixel detectors for γ imaging in medical application

In recent works we presented the γ0, a chip expressely designed for γ imaging in medical application. The chip was designed to be the anode of an Integrated Silicon Pixel Array (ISPA) tube. This chip consists of a matrix of 1024 pixels each 135u by 135u, each pixel comprises a CSA, designed to handle signals of few thousand electrons, a shaper, a discriminator and a 10 bit event buffer. The chip addresses many issues that are essential for the realization of cheap and fast detectors. Particularly it integrates a DAC controlled biasing network and an energy discrimination system. In this work, we present the test system and the first test results for the γ0.

A CMOS analog front-end IC for portable EEG/ECG monitoring applications

A new digital programmable CMOS analog front-end (AFE) IC for measuring electroencephalograph or electrocardiogram signals in a portable instrumentation design approach is presented. This includes a new high-performance rail-to-rail instrumentation amplifier (IA) dedicated to the low-power AFE IC. The measurement results have shown that the proposed biomedical AFE IC, with a die size of 4.81 mm/sup 2/, achieves a maximum stable ac gain of 10 000 V/V, input-referred noise of 0.86 /spl mu/ V/sub rms/ (0.3 Hz-150 Hz), common-mode rejection ratio of at least 115 dB (0-1 kHz), input-referred dc offset of less than 60 /spl mu/V, input common mode range from -1.5 V to 1.3 V, and current drain of 485 /spl mu/A (excluding the power dissipation of external clock oscillator) at a /spl plusmn/1.5-V supply using a standard 0.5-/spl mu/m CMOS process technology.

A 1 GHz CMOS analog front-end for a generalized PRML read channel

A 1 GHz CMOS analog front-end for general partial response maximum likelihood (GPRML) read channel in hard disk drive application has been implemented in 0.35 /spl mu/m CMOS. A continuous time analog filter fulfills the relaxed equalization for GPRML detection and can save up to 35% power consumption for the whole read channel. An analog DFE-based timing recovery loop is implemented to avoid the extremely long latency in the digital signal processing path (Viterbi decoder). The measured performances is 1.1 dB off simulations at 800 MHz and 1.6 dB off at 1GHz. The chip draws 240 mW from a 3.3 V supply at 800MHz clock and 380 mW from a 3.6 V supply at 1 GHz clock.

A CMOS HDSL2 analog front-end

A 5-V 0.5-/spl mu/m CMOS analog front-end (AFE) IC for HDSL2 incorporates transmit digital-to-analog converter (DAC), transmit filters, output buffer, receive AGC, and receive ADC. The AFE consumes 525 mW and provides better than 82-dB signal-to-noise-and-distortion ratio (SNDR) in both transmit and receive paths. It supports variable data rates from 64 kb/s up to 2.32 Mb/s, and enables an HDSL2 system to achieve better than 14 kft of noise-free reach (on 26-gauge wire) at 1.544 Mb/s.

Design of a 2.7 V CMOS analog front end for CCD video systems

A 2.7 V CMOS analog front end (AFE) is integrated with a 10-bit ADC for CCD video systems. The AFE provides correlated double sampling, 6-38 dB programmable gain and consumes 20 mA under a 2.7 V supply clocked at 15 MHz. The INL and DNL of the AFE and ADC under 0.8 V input signal are 9LSB and /spl plusmn/0.5LSB.

D/A conversion interface design for DMT-ADSL applications

For high-speed internet access, high-performance analog front-ends are needed, and data converters are one of the crucial building blocks in these bent-ends. In this article we will report on the modeling and design of a D/A conversion interface for a DMT (discrete multi tone)-based ADSL system that could be integrated into a complete CMOS analog front-end. We will discuss the DMT transmit spectrum and its impacts on data converters, we will focus on modeling and simulating of the whole D/A interface, and we will describe a test chip implemented in a 0.6 /spl mu/m CMOS process.

CMOS analog front end of a transceiver with digital echo cancellation for ISDN

A CMOS analog front-end which contains a novel pulse-shaping circuit, an extremely linear-line-driver state, an oversampling second-order noise-shaping coder, and a wake-up signal detector is discussed. An analog front-end for 4B 3T coded signals is realized in a 2.5- mu m CMOS technology and operates up to 4.5 km with 0.4-mm-diameter lines, needing only one 5-V power supply. It is possible to transmit 2B 1Q coded signals also, using a modified pulse-shaping circuit.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A single-chip CMOS analog front-end for high-speed modems : B. Fotouhi, R. Gregorian and W. Kline. Microelectron. J.15 (4), 5 (1984)

A single-chip CMOS analog front-end for high-speed modems : B. Fotouhi, R. Gregorian and W. Kline. Microelectron. J.15 (4), 5 (1984)