CMOS Amplifier Research Articles

Issues and Challenges in Small-Signal Low-Power Amplifiers: A Review

Background: Contemporary linear electronic circuit designs frequently include small-signal low-power amplifiers as a fundamental building block. These amplifiers are widely used as LNAs (Low Noise Amplifiers) in the pre-amplifier stages of both low-frequency and high-frequency featured electronic circuits. Objectives: To review the recent advances in the design of small-signal low-power amplifiers based on device configuration of BJTs, JFETs and MOSFETs for low (≤1KHz) and high frequencies (≥1MHz) at smaller input voltage (<1 Volt). Methods: The articles published between 2010 to 2024 are shortlisted from IEEE Xplore, Springer, Science Direct Elsevier, Google Scholar, and MDPI databases and the outcomes of the different techniques are compared on various parameters. Findings: It is found that four-stage CMOS amplifier at TSMC 40nm process technology emerges with highest 84.59dB gain, InP (Indium Phosphide) Distributed Amplifier Using 3-D Interdigital Capacitors carries widest bandwidth of 160 GHz, two stage darlington pair amplifier at 0.18μm under dual input and dual output topologies and four stage CMOS amplifier at 40nm technology realizes lower power consumption of 0.5mW and 0.00086 mW respectively. Small Signal Amplifier based on single stage BJT-JFET Sziklai pair operates at lowest frequency of 11.36 Hz, single stage LNA at 180nm CMOS technology using inductive degenerate topology works at very low supply voltage at +0.5V and, recently reported complementary sziklai based small signal amplifier under CC mode works at lowest -15V supply voltage. Novelty: The review proposed on ‘Small Signal Low Power Amplifier’ is first time reported in this paper. Moreover, it discusses low power small signal amplifiers at both low (≤1KHz) and high (≥MHz) frequencies considering gain enhancement technique, power dissipation reduction technique, and noise reduction technique whereas other review papers emphasize on the general discussion of different topologies only at high frequencies. Keywords: Small-Signal Amplifiers, Low Power Amplifiers, BJTs, JFETs, MOSFETs

Bandwidth Extension of CMOS Amplifier Using Mutually Coupled Three-Inductor Coil

Bandwidth Extension of CMOS Amplifier Using Mutually Coupled Three-Inductor Coil

Comparison of Si CMOS and SiC CMOS Operational Amplifiers

In this study, we numerically compare the characteristics of Si and SiC CMOS operational amplifiers (OpAmp) using LTspice. According to prior researches, we set the device parameters for Si and SiC MOSFETs. The OpAmp consists of three stages: the input stage, the gain stage, and the output stage. We established three criteria for the OpAmp's operation: (1) a unity gain frequency of 1MHz, (2) an open-loop gain of at least 75dB, and (3) a phase margin of more than 60° when a load capacitance is 300pF. To achieve a unity gain frequency of 1MHz, we adjusted the values of the resistor and capacitor used for phase compensation. The supply voltage was set to be ±5V for the Si OpAmp and ±15V for the SiC one. Our numerical analysis of the frequency response shows that the Si OpAmp met all three criteria. In contrast, the SiC OpAmp, when faced with a load capacitor of 300pF, had a phase margin of 43.4°, falling below the 60° mark. For the SiC OpAmp, the frequency response declined rapidly when the supply voltage dropped to 10V or below.

Preliminary Characterization of an Active CMOS Pad Detector for Tracking and Dosimetry in HDR Brachytherapy.

We assessed the accuracy of a prototype radiation detector with a built in CMOS amplifier for use in dosimetry for high dose rate brachytherapy. The detectors were fabricated on two substrates of epitaxial high resistivity silicon. The radiation detection performance of prototypes has been tested by ion beam induced charge (IBIC) microscopy using a 5.5 MeV alpha particle microbeam. We also carried out the HDR Ir-192 radiation source tracking at different depths and angular dose dependence in a water equivalent phantom. The detectors show sensitivities spanning from (5.8 ± 0.021) × 10-8 to (3.6 ± 0.14) × 10-8 nC Gy-1 mCi-1 mm-2. The depth variation of the dose is within 5% with that calculated by TG-43. Higher discrepancies are recorded for 2 mm and 7 mm depths due to the scattering of secondary particles and the perturbation of the radiation field induced in the ceramic/golden package. Dwell positions and dwell time are reconstructed within ±1 mm and 20 ms, respectively. The prototype detectors provide an unprecedented sensitivity thanks to its monolithic amplification stage. Future investigation of this technology will include the optimisation of the packaging technique.

High Sensitivity Temperature Measurements to Track and Compensate Aging Effects on CMOS Amplifiers

High Sensitivity Temperature Measurements to Track and Compensate Aging Effects on CMOS Amplifiers

Research on Noise Optimization of CMOS Amplifier Used in ECG Signal

Electrocardiography has a wide range of applications in monitoring heart health and diagnosing diseases, among which how to efficiently and accurately reduce noise of electrocardiogram (ECG) signals is of great significance. This paper first writes the processing flow of ECG signals and the theoretical basis of low-noise CMOS amplifiers, then analyzes the difficulties of noise optimization of CMOS amplifiers in ECG scenarios, and then proposes feasible solutions for each difficulty. Considering these influencing factors comprehensively and using a variety of noise reduction methods in a reasonable combination will actively help the noise optimization of the ECG signal. Linking the CMOS amplifier with the noise reduction processing of the entire ECG circuit can reduce the interference of noise and improve the quality of the signal, so that the ECG signal can more accurately reflect the electrical activity of the heart. This is of great significance for the monitoring and research of heart health.

Research on Improving Amplifier Used in Brain-Computer Interface Technology

With the rapid development of science and technology, the demand for human-computer interaction in many fields is increasing, and the requirements are getting higher and higher. As the most important part in human-computer interaction, the demand for Brain-Computer Interface (BCI) technology in medicine, games, military fields, etc. is increasing. Therefore, more and more scholars and institutions have begun to study BCI technology. In this paper, an experiment is designed to improve the performance of two-stage CMOS amplifiers, an important component of BCI technology. The experiment uses CoolSpice to build a basic model of the two-stage CMOS amplifier for simulation, replacing brain waves with a small signal, and adjusting the performance of the two-stage CMOS amplifier by adding a compensated capacitor and resistor. Through experimentation, it can be concluded that selecting an appropriate compensated capacitor can significantly improve the performance of the amplifier. Improving the performance of amplifiers can help improve the efficiency of BCI technology and help people collected the information emitted by brain waves more accurately in the future.

Recycling folded cascode two-stage CMOS amplifier

In this work, we propose a highly efficient two-stage CMOS amplifier that is based on an improved recycling folded cascode design. The circuit was simulated using TSMC 0.18 μm and HSPICE circuit simulator at a voltage of 1.8 V. The first stage of the circuit utilizes a supper recycling folded cascode design, while the second stage employs a simple cascode amplifier. Additionally, we have utilized a small 1 pF Miller capacitor to stabilize the amplifier response. Based on simulation results, the proposed amplifier demonstrates a DC gain of 110 dB, GBW of 15 MHz, and power consumption of 359 μW. Finally, we conducted Monte Carlo simulations to verify the robustness of the proposed circuit against the process, temperature, supply voltage, and device dimension mismatch variations.

Circuit design of a three-stage CMOS amplifier by circuit theory and analysis miller compensation network

This paper establishes a single Miller capacitor-based frequency compensation network for a three-stage amplifier. Nodal equations are solved symbolically and a linear transfer function is obtained. Poles and zeros formulations are extracted while circuit-level implementation is suggested and simulated using 0.18 μm CMOS technology. The compensation network shares the Miller capacitor at two negative loops simultaneously leading to improving frequency response. According to the simulation results, theoretical linear calculations are in acceptable agreement. The proposed amplifier shows 115 dB, 151 MHz, and 55 as DC gain, GBW, and PM respectively while consuming 320 μW as power dissipation.

Fully active frequency compensation analysis on multi-stages CMOS amplifier

An enhanced three-stage CMOS transconductance amplifier attached to a novel frequency compensation network is proposed. Two differential stages are attached with Miller capacitors and the Miller effect is boosted accordingly. In this way, four negative loops intensify the Miller effect virtually. The structure is designed at the transistor level using 0.18 μm CMOS library and the SPICE simulator while a symbolical transfer function is extracted and analyzed to obtain circuit dynamics. Leveraging both concept and method, the proposed amplifier shows unconditional stability with acceptable accuracy regarding the symbolic description and simulation results. Ample sensitivity analysis is also provided to show the reliability of the amplifier. By simulation responses, the presented circuit expresses competitive merits against previous works. Simulation results show 120 dB as DC gain, 18 MHz as, GBW, and 54º as phase margin while the simulated amplifier consumes only 345μW.

Design and Simulation of Two Stage Wideband CMOS Amplifier in 90 NM Technology

Design and simulation of 7 GHz CMOS wideband amplifier(CMOSWA) using a modified cascode circuit realized in 90-nm CMOS technology is presented here. The proposed system consists of two stages, namely a modified folded cascode and an inductively degenerated common source amplifier. The circuit is experimented with and without a feedback network. This work discusses the performance variation as a function of reactive components, and the initial stage results in 22 dB gain,2.6 GHz bandwidth, and 40GHz unity gain-bandwidth. The circuit without the feedback network exhibits 30.7dB gain,4.8GHz bandwidth(BW), and 10GHz unity-gain bandwidth(UGB). The reactive feedback network's inclusion helped to achieve 38.7 dB gain, 6.95GHz BW, 30GHz UGB, and 55o phase margin. The circuit consumes 1.4mW power from a 1.8V power supply. Simulation results of the proposed circuit are comparable and better than the reported wideband designs in the literature. Realization of our proposed circuit would add value to the area of wideband amplifier design.

A differential block and NCG cell based four stage CMOS amplifier

A differential block and NCG cell based four stage CMOS amplifier

Suzuki Stack Circuit With Differential Output

Suzuki stack circuits, a type of latching high-voltage driver circuit, are widely used in Josephson–CMOS hybrid memories. The existing Suzuki stack designs utilize only single-ended signaling when connected to a CMOS amplifier. In this article, a Suzuki stack circuit with a differential output is proposed by producing both the positive and negative output voltages. The negative output voltage is produced by using a negative biasing network and a negative single-flux quantum (SFQ) input pulse, which is generated by the proposed positive-to-negative SFQ converter. As compared to a conventional single-ended Suzuki stack circuit, the proposed differential design can provide two times higher output voltage swing and better immunity to noise without degrading the operating margins. Potential advantages and drawbacks of the proposed circuit are explored in this article.

On Noise Modeling of Capacitive Feedback Transimpedance Amplifiers in CMOS

The work reports on the development of a detailed noise current model for a low-noise capacitive feedback transimpedance amplifier (TIA) in CMOS. The proposed TIA circuit implements the programmable-gain using an array of discretely controlled feedback capacitors and resistances in the biasing circuit and is originally designed bearing in mind low-noise requirements for optical time-domain reflectometer (OTDR) applications with the base gain of 10 kΩ at 1 GHz bandwidth and noise levels below 5.0 pA/Hz. The newly developed model for input-referred noise current spectral density complements the previously suggested transimpedance gain model and takes into account both the primary and secondary noise sources so far ignored in the models known in the literature. The proposed noise model consists of five terms and includes the effects caused by biasing components of the input stage and the noise shaping from the source follower. The performance of the developed noise model is evaluated using the post-layout simulation in 0.18 μm CMOS and 0.25 μm BiCMOS technologies, and a close match of the proposed model is demonstrated in the results of the post-layout simulation with the noise level below 1.8 pA/Hz for the base gain configuration in CMOS. A comparison to available noise models from the literature confirms that previously known noise models for this promising TIA architecture omitted important noise components present in practical and physically realizable circuits and, therefore, resulted in underestimating the base noise level by a factor of two to three, while completely ignoring the flicker noise mapping in the low-frequency range.

A Multi-Band LNA Covering 17–38 GHz in 45 nm CMOS SOI

This paper presents a multi-band low-noise amplifier (LNA) in the 45-nm CMOS silicon-on-insulator (SOI) process. The LNA consists of three stages, with the differential cascode amplifier as the core structure. The first stage is mainly responsible for input matching to ensure favourable noise characteristics and bandwidth, while the subsequent stages increase the gain. Moreover, the LNA utilizes baluns for input/output and interstage impedance matching. Switch capacitances are added to switch the three operating bands of the LNA, which cover 17–38 GHz overall. Measurement results show that the proposed LNA achieves a gain (S21) of 23.0 dB and a noise figure (NF) of 4.0 dB.

Investigation of Four-Port Characteristic Dependence on Gate Length for MOSFETs in the Breakdown Region

In this article, gate length-dependent RF four-port characteristics of MOSFETs are investigated in the avalanche regime by using the double feedback and chain rule methods for the first time. The obvious decline of the imaginary part of source input impedance at high drain voltage for short-channel MOSFETs is investigated through the double feedback instead of only the series feedback for the origin of the inductive source impedance. The dominant terms causing the reduction of inductive source impedance due to parallel feedback are determined by this chain rule method. When compared with the conventional analysis due to short-channel effects on the direct-current (DC) characteristics of threshold voltage and substrate current, short-channel MOSFETs resulting in the aspect of RF characteristics are further analyzed by using different gate length MOSFETs. Besides, as gate length reduces, drain-to-source transmission raises significantly in the avalanche regime due to the RF avalanche network according to this analysis. This mechanism results in lower isolation at the breakdown for the shorter gate length MOSFETs. Good agreement of the four-port scattering parameter (S-parameter) between simulation and measurement is obtained for the MOSFETs operating in the both breakdown and saturation regions. The methods can be utilized for other advanced technology nodes and are helpful for the design of RF CMOS amplifiers in the impact ionization region.

MmWave Spatial–Temporal Single Harmonic Switching Transmitter Arrays for High Back-Off Beamforming Efficiency

This paper presents a spatial-temporal single harmonic switching (STHS) transmitter array architecture with enhanced efficiency in the power back-off (PBO) region. STHS is an electromagnetic and circuit co-designed and jointly optimized transmitter array that realizes beamforming and back-off power generation at the same time. The temporal dimension is originally added in STHS to achieve back-off efficiency enhancement, which can be combined with conventional power back-off enhancement methods such as Doherty amplifiers and envelope tracking. The design is validated through a simulation of a two-stage power amplifier in 65-nm CMOS at 77 GHz, which achieves a peak drain efficiency (DE) of 24.2%, a 22% DE at 3-dB PBO, 16% DE at 6-dB PBO, and 10.2% at 9-dB PBO. The efficiency exhibits a 57% improvement at 3-dB PBO, 100% improvement at 6-dB PBO, and 190% improvement at 9-dB PBO compared with class A/B amplifier.

Double Differential Blocks Based Frequency Compensation: A Four-Stage CMOS Amplifier

In this paper, an efficient frequency compensation method is investigated for a four-stage CMOS amplifier. The frequency compensation network includes two sets of capacitors at the differential block output. The proposed compensated amplifier is described symbolically to obtain the transfer function. Meanwhile, the proposed configuration is designed at the circuit level and is simulated via 0.18[Formula: see text][Formula: see text]m CMOS technology. Compared to the other existing methods, the proposed amplifier satisfies the figure of merits considerably. This stems from the fact that lower capacitor values are used to perform compensation, leading to lower die occupation, and reach boosted gain bandwidth products. Leveraging both the configuration and design procedure, a high-performance four-stage is presented in this paper.

Noise Measure Revisited for Design of Amplifiers Close to Activity Limits

This article revisits the concept of “noise measure” and its importance in designing high-frequency low-noise amplifiers. A new derivation is offered which is simpler than the original derivation of Haus and Adler. Several examples are used to calculate the minimum noise measure of a CMOS amplifier. It is also shown that “noise cancellation” techniques cannot improve the minimum noise measure.

A Full Ka-Band CMOS Amplifier Using Inductive Neutralization with a Flat Gain of 13 ± 0.2 dB

This paper presents a CMOS wideband amplifier operating in the full Ka-band, with a low gain variation. An inductive neutralization is applied to the amplifier to compensate for the gain roll-off in the high-frequency region. Neutralization inductance is carefully determined considering the tradeoff between stability and gain. To achieve a low gain variation over the full Ka-band, the amplifier employs the frequency staggering technique in which impedance matching for three gain stages is performed at different frequencies of 26, 34, and 42 GHz. The experimental results show that a peak gain of 13.2 dB is achieved at 39.2 GHz. The 3 dB bandwidth is from 23.5 to 41.7 GHz, which fully covers the Ka-band. Especially, the gain ripple of the amplifier is only 13 ± 0.2 dB over a wide bandwidth from 26.2 to 40.2 GHz. The input and output return loss values are better than −10 dB from 26.3 to 40.1 GHz and from 25.3 to 50 GHz, respectively. The DC power consumption is 18.6 mW.