CML Driver Research Articles

Development of a serial link transmitter for monolithic active pixel sensors

In this paper, a 5-Gbps serial link transmitter has been designed for monolithic active pixel sensor. The serial link is designed in a commercial 130-nm CMOS technology with a power supply of 1.2 V. The transmitter consists of a 16b/20b encoder, a three-stage 20:1 serializer core, the CML driver with pre-emphasis function, and a high-speed receiver to deal with the external clock. The root mean square jitter of this serial link transmitter is 2.2 ps, indicating a bit error rate of 1 × 10−14. This paper will discuss the design and performance of this serial link transmitter.

A 25 Gbps VCSEL driving ASIC: an attempt for ultra-high-speed front-end readout applications

This paper presents the design and the test results of a 25 Gbps VCSEL driving ASIC fabricated in a 55 nm CMOS technology as an attempt for the future very high-speed optical links. The VCSEL driving ASIC is composed of an input equalizer stage, a pre-driver stage and a novel output driver stage. To achieve high bandwidth, the pre-driver stage combines the inductor-shared peaking structure and the active-feedback technique. A novel output driver stage uses the pseudo differential CML driver structure and the adjustable FFE pre-emphasis technique to improve the bandwidth. This VCSEL driver has been integrated in a customized optical module with a VCSEL array. Both the electrical function and optical performance have been fully evaluated. The output optical eye diagram has passed the eye mask test at the data rate of 25 Gbps. The peak-to-peak jitter of 25 Gbps optical eye is 19.5 ps and the RMS jitter is 2.9 ps.

A 3.2-Gb/s serial link transmitter in [formula omitted] CMOS technology for CMOS Monolithic Active Pixel Sensors application

We present a 3.2-Gb/s serial link transmitter for MAPS application in future subatomic physics experiments. The transmitter features the inclusion of Reed–Solomon codes to achieve low transmission error rate. A CML driver with pre-emphasis in the transmitter allows serial transmission over low mass cables. The critical digital circuits are triplicated to resist SEU. The transmitter is fabricated in a 0.18μm CMOS Technology. A power consumption of 135 mW was measured at a typical setting. A frame data rate of 3⋅10−12 with confidence level of 94.5% was obtained through a FPGA based receiver, corresponding to a payload BER of 1.2⋅10−14 with confidence level of 94.9%. The transmitter functions well after being irradiated with 4.5 Mrad TID.

A 32 Gb/s, 201 mW, MZM/EAM Cascode Push–Pull CML Driver in 65 nm CMOS

This brief presents a 32 Gb/s driver for a Mach–Zehnder modulator (MZM) and an electro-absorption modulator (EAM). A push–pull current-mode logic driver is chosen to achieve a better power efficiency and a large voltage swing. A double cascode with thin oxide transistors is employed to mitigate the over-voltage stress associated with a large output voltage swing. At the same time, shunt-peaking inductors are incorporated in a compact way to extend the bandwidth and to have a flat group delay. The proposed driver has been fabricated using 65 nm CMOS technology with an active area of 0.086 mm2. The electrical measurement result shows that the driver exhibits a differential output swing of 4 ${\text V}_{\text {pp}}$ at 10 Gb/s. The measured extinction ratios of the driver using the MZM and EAM are 4.53 dB and 4.17 dB, respectively, at 32 Gb/s. The power consumption is 201 mW at 32 Gb/s, which corresponds to an energy efficiency of 6.28 mW/Gb/s.

A low-power 12.5 Gbps serial link transmitter ASIC for particle detectors in 65 nm CMOS

This paper presents a 12.5 Gbps serial link transmitter application-specific integrated circuit (ASIC) designed in a 65-nm CMOS technology. The ASIC mainly includes an LC-VCO phase-locked-loop (PLL), a 16:1 serializer and a CML driver. Simulation results show that the PLL achieves a 7-to-14 GHz frequency tuning range and an RMS jitter of 0.4 pS. The serializer has a deterministic jitter of 9 pS and a programmable output swing from 200 mV to 1.0 V. The PLL and the serializer consumes 39.6 mW and 73 mW from a 1.2 V power supply, respectively.

Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver

This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip transmission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.