Clock Recovery System Research Articles

Synchronized source of indistinguishable photons for quantum networks

We present a source of indistinguishable photons at telecom wavelength, synchronized to an external clock, for the use in distributed quantum networks. We characterize the indistinguishability of photons generated in independent parametric down-conversion events using a Hong-Ou-Mandel interferometer, and show non-classical interference with coalescence, C = 0.83(5). We also demonstrate the synchronization to an external clock within sub-picosecond timing jitter, which is significantly shorter than the single-photon wavepacket duration of ≈ 35 ps. Our source enables scalable quantum protocols over multi-node, long-distance optical networks using network-based clock recovery systems.

Single-photon-based clock analysis and recovery in quantum key distribution

Quantum key distribution is one of the first quantum technologies ready for the market. Current quantum telecommunication systems usually utilize a service channel for synchronizing the transmitter (Alice) and the receiver (Bob). However, the possibility of removing this service channel and exploiting a clock recovery method are intriguing for future implementation, both in fiber and free-space links. In this paper, we investigate criteria to recover the clock in a quantum communication scenario and experimentally demonstrated the possibility of using a quantum-based clock recovery system in a time-bin quantum key distribution protocol. The performance of the clock recovery technique, in terms of quantum bit error rate and secret key rate, is equivalent to using the service channel for clock sharing.

A 10-Gb/s 275-fsec Jitter Cryo-CMOS Charge-Sampling CDR for Quantum Computing Application

This letter presents the first clock and data recovery (CDR) system operating at 4.2 K designed for quantum computing (QC) applications. By considering the benefits and challenges of cryogenic operation, a dedicated analog CDR structure is employed so as to maintain high performance at 300 and 4.2 K. The CDR incorporates a new complementary charge-sampling phase detector (PD) that achieves low power and low jitter. Fabricated in 40-nm CMOS, the proposed CDR operates at 10 Gb/s, achieving a recovered clock jitter of 260 fs and a jitter tolerance of 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\rm UI}_{{\rm PP}}$</tex-math> </inline-formula> at a 5-MHz jitter frequency while consuming 4.7 mW at room temperature (RT). At 4.2 K, the power consumption reduces to 3.1 mW with a recovered clock jitter of 275 fs and a jitter tolerance of 0.85 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\rm UI}_{{\rm PP}}$</tex-math> </inline-formula> at a 5-MHz jitter frequency, demonstrating its functionality for a high-speed cryogenic wireline link.

Robust Timing Error Detection for Multilevel Baud-Rate CDR

Baud rate timing recovery, for which the Mueller-Muller approach is the most prominent, has become the mainstay of high speed serial links because of the simplicity of its implementation. The foundations of Mueller-Muller - Type A timing function and its propensity to lock to erroneous sampling points when applied to high order pulse amplitude modulation is studied. Using the timing error detector characteristics, the probability of the Mueller-Muller - Type A phase detector (PD) to settle to undesirable lock points is investigated. The impact of prevailing approaches to mitigate the effect of this behavior on the performance of clock and data recovery (CDR) systems is quantified, and a new low-overhead PD approach without any of their drawbacks is proposed. Simulink simulations of the CDR phase acquisition, jitter tolerance and timing margins are used to demonstrate the effectiveness of the proposed PD in achieving superior CDR performance while avoiding any of the convergence issues.

Loop Dynamics Analysis of PAM-4 Mueller–Muller Clock and Data Recovery System

Loop Dynamics Analysis of PAM-4 Mueller–Muller Clock and Data Recovery System

FPGA Implementation of an NCO Based CDR for the JUNO Front-End Electronics

This article describes a design of an field-programmable gate array (FPGA) implementation of a clock and data recovery (CDR) system. The core will be integrated in the FPGA configuration for the front-end electronics (FEE) board of the Jiangmen underground neutrino observatory (JUNO) experiment. The front-end will be placed on the main detector, underground and underwater, making the electronics not accessible after installation. The timing and trigger system relies on a synchronous link connection over CAT5e cable (up to 100 m long) between the front-end and the back-end electronics (BEE), where a twisted-pair is dedicated to clock-forwarding. The robustness of the recovery clock system is essential for the stability of the FPGA firmware. The proposed project is intended to improve the clock recovery operation by increasing the immunity of the link to sudden electromagnetic interference (EMI). On top of this, the core allows to free a twisted-pair in the link, since the clock can be recovered from the data and there is no more need for a clock-dedicated transmission. This will optimize the link granting the possibility to implement other features. The design is based on two components: a numerically-controlled oscillator (NCO), in order to create a controlled frequency clock signal, and a digital phase detector (PD) to match the clock frequency with the data rate. NCOs are often coupled with a digital-to-analog converter (DAC) to create direct digital synthesizers (DDSs), which are able to produce analog waveforms of any desired frequency. In the presented case instead, the NCO generates a digital clock signal of an arbitrary frequency, while the PD manages this frequency by intercepting any shifting on the relative phase between the clock and the data. A phase aligner (PA) module guarantees that data are sampled in the middle of the eye pattern, which represents the optimal sampling point. The article presents an overview of the NCO-based CDR design and implementation, together with some tests and results in order to verify the CDR reliability. Moreover, in the last section, some other possible applications of the core are illustrated.

High-speed Clock and Data Recovery System with Segmented Slew-rate Control Circuit for High-linearity in 65 nm CMOS Process

High-speed Clock and Data Recovery System with Segmented Slew-rate Control Circuit for High-linearity in 65 nm CMOS Process

Design and Implementation of Low Power Delay Locked Loop using Multiplexer Based Phase Frequency Detector

This paper proposes design and implementation of low power Delay Locked Loop Architecture, with dynamic Multiplexer based Phase Frequency Detector with minimum locking time. Clock and data recovery systems are employed to derive the clocking information to correctly decode the transmitted data at the receiver. Delay Locked Loop is one of the most important clock recovery systems. The DLL architecture is designed using Cadence Virtuoso 180nm Technology with 1.8V power supply. The proposed DLL with Multiplexer based phase frequency detector shows significant reduction in power dissipation by 10% compared to DLL designed using D-FF based PFD and achieves locking state within 10 clock cycles with minimum jitter of 4.84326ps, measured within clock frequency range of 100-250MHz.

On the Cross-Correlation Based Loop Gain Adaptation for Bang-Bang CDRs

This article describes the cross-correlation function as an alternative method to adapt loop gain in digital CDRs. Cross-correlation function inherent properties and their link with the cross-power spectral density help consolidating the adaptive loop gain technique, XCALG, for clock and data recovery systems that implement bang-bang phase detector. Considering the modulation of the loop gain due to jitter noise, previous works exploit the autocorrelation function at the output of the bang-bang phase detector as a proper indicator to track the system dynamics and perform loop gain adaptation. In contrast, we propose the XCALG as a new alternative to perform loop gain adaptation featuring better observability, less impact from jitter sources while keeping a safe phase margin. Theory behind the idea is enhanced, and the XCALG is demonstrated through behavioral system simulations. In addition, preliminary implementation costs of the cross-correlation function are discussed using a 65nm CMOS technology node.

A CDR System Based on Improved Second Order Digital Filter, Hysteretic Voter and Phase Interpolator

The proposed Clock and data recovery system (CDRS) has three improved parts. The second order digital filter with rounding algorithm implements fractional gain and avoids direct current quantization noise which varies between -q/2 and +q/2 while that of traditional filter varies between 0 and +q (q is quantization step). The hysteresis majority voter can combat high frequency and strong jitter especially in quasi-steady state. The improved Phase interpolator (PI) has much smaller current-switching glitch and phase glitch since the weighting current changes gradually instead of steeply. The optimized CDRS can handle up to ±6000ppm (parts per million) frequency offset and the phase resolution is 1.4º/LSB (Least significant bit) according to analysis. The simulations of jitter transfer function and jitter tolerance by Matlab, simulations of phase noise by spectre using Verilog+VeriloA model, and measurements of frequency offset and jitter tolerance all show its good performance.

A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS

The emergence of four-level pulse amplitude modulation (PAM-4) standards to increase data rates motivates the use of receiver front ends that utilize high-speed analog-to-digital converters (ADCs) followed by digital signal processing (DSP) to provide robust digital equalization. This paper presents an ADC-based PAM-4 receiver employing a 32-way time-interleaved, 2-bit/stage, 6-bit successive approximation register (SAR) ADC with a single capacitive reference digital-to-analog converter (DAC) and a digital equalizer consisting of a 12-tap feed-forward equalizer (FFE) and a two-tap decision-feedback equalizer (DFE). A new digital DFE architecture that reduces the complexity of a PAM-4 DFE to that of a binary non-return-to-zero (NRZ) DFE, while simultaneously nearly doubling the maximum achievable data rate, is presented. Partial analog equalization is provided in the receiver front end in the form of a programmable two-stage continuous-time linear equalizer (CTLE) and a three-tap FFE that is embedded in the ADC using a non-binary FFE DAC to improve the FFE coefficient coverage space. This partial analog equalization allows placement of the digital baud-rate clock and data recovery (CDR) system's Mueller-Muller phase detector directly at the ADC output to avoid excessive loop delay. Fabricated in GP 65-nm CMOS, the receiver achieves 32-Gb/s operation at a bit error rate (BER) <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> with a 30-dB loss channel and 52-Gb/s operation at a BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> with a 31-dB loss channel without utilizing any transmit equalization. The complete ADC-based receiver achieves a 52-Gb/s power efficiency of 8.06 pJ/bit, including all the front end, ADC, and DSP power.

Design of clock and data recovery system’s behavioral model for high speed transceivers of serial interfaces

This paper provides a parameterizable behavioral model of a clock and data recovery system (CDR) based on phase-locked loop (PLL) for the receiver part of a high-speed serial interfaces. The model was used to calculate parameters and characteristics of the system as well as estimate their calculation error depending on the sub-circuit characteristics taken into account. A model structure was selected based on the obtained jitter estimation error. The model complies with all the accuracy and speed requirements to calculations of the characteristics of a PLL-CDR system for a receiver block with data transmission bit rates above 3.125 Gbit/s.

Ground-Referenced Single-Ended Signaling: Applications for High-Density, Short-Haul Communication Systems

In this article, we discuss how ground-referenced signaling (GRS) avoids many of the challenges associated with SE signaling, thanks to a unique transmitter (Tx) topology, to produce a link with high reliability, high information density, and high energy efficiency for short-reach applications. GRS-based short-reach links also use a simple but robust clock-forwarding scheme to cancel jitter without the need for a clock recovery system at the receiver (Rx), thereby, saving significant power. This approach also provides high-bandwidth jitter tracking, which we take to the limit by matching circuit delay and delay sensitivity for clock and data lanes at both ends of the link. Codesign of the link circuitry and channel takes full advantage of the ability to match the insertion delays of multiple data/clock lanes within the short-reach interconnect. The low attenuation that can be achieved in a codesigned channel is leveraged to achieve a simple, robust, and low-power design.

COHERENT DETECTION OF TWO-DIMENSIONAL DIGITAL MODULATION SIGNALS

Two-dimensional digital modulations require coherent detection to eliminate phase uncertainty. The main problem is that it is necessary to exactly match the frequencies and initial phases of the carrier and reference oscillations in the two processing channels and the phase difference in the subchannels at exactly π / 2. This article proposes a joint algorithm for clock recovery and phase adjustment of the reference oscillator of a two-dimensional digital modulation demodulator. If there is a delay in the beginning of the pulse, at the moment of transition from one channel symbol to another there will be a phase jump equal to the phase difference of the transmitted channel symbols. To determine the transition from one channel symbol to another, it is necessary to clearly define the moment of the jump. To do this, it is necessary to form a signal for the difference in phase values across the sampling interval. At the time of a phase jump, a single, substantially non-zero jump will be observed. The moment of the jump will determine the beginning of the channel symbol. The error of the start pulse adjustment will not exceed the sampling interval. Algorithm adjustment of the reference generator. The proposed algorithm is intended to use for determining the phase φ0 of the intermediate results of the clock recovery system. Sampling of values is performed within certain limits of the channel symbol and averaging is performed. Then it is necessary to introduce a correction of the phase value taking into account the clock adjustment. The proposed algorithm eliminates the mutual effects on the results of the estimates of the delay and phase adjustment. That is, the phase increment due to the delay in the channel does not affect the result of evaluating the phase increment due to the mismatch between the phases of the carrier and reference oscillations, despite the fact that the adjustment is made by phase error.

Multi-rate phase interpolator for high speed serial interfaces

A flexible and all digital CMOS phase interpolator is proposed in this paper suitable for high speed multi-Gigabit serial transceivers applications. The topology is constructed by a parallel combination of identical CMOS inverters grouped in two segments, a phase multiplexer and a capacitive tank. The proposed phase interpolator is quite simple and generic and can be easily fitted in a clock and data recovery system. The circuit is designed in a 65nm CMOS technology node under 1V supply voltage. The circuit robustness is verified through its application to the most updated M-PHY serial interface standard requirements supporting multiple data rates of 1.5/3/6Gbps. It is capable to deliver two orthogonal (I/Q) output phases with 5-bit phase resolution resulting in 32 equally spaced discrete steps of 11.25°. Post-layout simulation results confirm less than 1.7° worst case phase step error, settling time less than 2 clock cycles and power consumption 0.6mW at 6Gbps.

An all-digital semi-blind clock and data recovery system

This paper presents a digitally intensive semi-blind clock and data recovery (SBCDR) system. The paper covers the theory, analysis, and system level simulation of this SBCDR. The proposed CDR is tailored to target the optical network standard OC-192. The SBCDR can provide the required jitter tolerance (JTo), and still provide enough jitter filtering to achieve the jitter transfer (JTr) requirements. Also, the recovered clock achieves a low jitter generation (JG) of 0.01 UIrms and 0.0064 UIrms for both the wide-band and high-band jitter filters defined by the standard. The proposed SBCDR provides two advantages over typical SBCDRs and PLL-based CRDs that target OC-192. First, the digitally intensive nature provides a scalable and process tolerant design. Second, the architecture provides a CDR that can pass all three jitter performance metrics, without the aid of an external clean-up phase locked loop (PLL) or a high performance clock multiplication unit (CMU) typically required by OC-192 transceivers. By utilizing a circular representation for the phase calculation in the over-sampling clock and data recovery (OSCDR), extensive pipe-lining in the implementation and higher data rate tolerance can be achieved. The simulation results of the proposed SBCRD agree closely with theoretical results.

A Clock Synchronization for M-Sequence-Based Ultra-Wideband Systems

This paper presents a cross-correlation-based synchronization architecture between the clock of the receiver and the transmitter of ultra-wideband systems. The proposed architecture is based on M-sequence signals instead of the conventional impulse signals. The M-sequence generator and the analog correlation circuit are fabricated on-chip using a low-cost 0.25 μm 95 GHz fmax SiGe-HBT-BiCMOS process technology. The chip is mounted on a printed circuit board (PCB) with a commercial voltage-controlled oscillator (VCO). The synchronization scheme obtains the clock information with a received signal as low as 2 mV peak to peak and minimum input power of -52 dBm at 10 GHz. The power spectrum measurement of the locking VCO shows a low phase noise of -69 dBc/Hz at 1 kHz offset and an rms jitter of 0.93 ps for a 10 GHz frequency and a bit rate of 20 Gb/s. The achieved mismatch between the received and the reference signals is a maximum of 25 ps at signal bandwidth of 10 GHz. The proposed clock recovery system acquires the clock information correctly with different materials placed in the transmission channel.

SiGe Clock and Data Recovery System Based on Injection-Locked Oscillator for 100 Gbit/s Serial Data Link

Clock and data recovery (CDR) systems are the first logic blocks in serial data receivers and the latter's performance depends on the CDR. In this paper, a 100 Gbit/s CDR designed in 130 nm BiCMOS SiGe is presented. The CDR uses an injection locked oscillator (ILO) which delivers the 100 GHz clock. The inherent phase shift between the recovered clock and the incoming data is compensated by a feedback loop which performs phase and frequency tracking. Furthermore, a windowed phase comparator has been used, first to lower the classical number of gates, in order to prevent any delay skews between the different phase detector blocks, then to decrease the phase comparator operating frequency, and furthermore to extend the ability to track zero bit patterns The measurements results demonstrate a 100 GHz clock signal extracted from 50 Gb/s input data, with a phase noise as low as 98 dBc/Hz at 100 kHz offset from the carrier frequency. The rms jitter of the 25 GHz recovered data is only 1.2 ps. The power consumption is 1.4 W under 2.3 V power supply.

Hybrid Clock Recovery for a Gigabit POF Transceiver Implemented on FPGA

In this paper, we present a clock recovery system implemented on field programmable gate array and integrated to the Gigabit Ethernet media converter for PMMA SI-POF developed within the framework of the POF-PLUS EU Project. We demonstrate timing synchronizing using only one sample per symbol from a highly distorted and attenuated 2-PAM signal without requiring any sort of preequalization. This is achieved by means of a hybrid analog-digital PLL with a timing error detector based on a modified version of the Muller and Mueller algorithm, a loop filter, and a VCXO.

Photo-Detectors Integrated with Resonant Tunneling Diodes

We report on photo-detectors consisting of an optical waveguide that incorporates a resonant tunneling diode (RTD). Operating at wavelengths around 1.55 μm in the optical communications C band we achieve maximum sensitivities of around 0.29 A/W which is dependent on the bias voltage. This is due to the nature of RTD nonlinear current-voltage characteristic that has a negative differential resistance (NDR) region. The resonant tunneling diode photo-detector (RTD-PD) can be operated in either non-oscillating or oscillating regimes depending on the bias voltage quiescent point. The oscillating regime is apparent when the RTD-PD is biased in the NDR region giving rise to electrical gain and microwave self-sustained oscillations Taking advantage of the RTD's NDR distinctive characteristics, we demonstrate efficient detection of gigahertz (GHz) modulated optical carriers and optical control of a RTD GHz oscillator. RTD-PD based devices can have applications in generation and optical control of GHz low-phase noise oscillators, clock recovery systems, and fiber optic enabled radio frequency communication systems.