Clock Mode Research Articles

Circuit Techniques for Immunity to Process, Voltage, and Temperature Variations in the Attachable Fractional Divider

In the automotive industry, system-on-chips are crucial for managing weak radio waves from space, known as satellite signals. Integer-N phase-locked loops have played a vital role in the operation of system-on-chips in recent history. Their clock frequencies are carefully designed to prevent electromagnetic interference. However, as global navigation satellite system becomes more prevalent, integer-N phase-locked loops face new challenges in generating clocks within the shrinking frequency bands due to large frequency steps determined using a reference clock. To address it, replacing integer-N phase-locked loops with fractional-N phase-locked loops is required. This topic has not been discussed extensively, but it is a practical issue that requires consideration due to its potential impact on development costs. This is why we developed an attachable fractional divider. Our developed divider can efficiently transform integer-N phase-locked loops into fractional-N phase-locked loops, achieving low jitter degradation of 0.35 psrms and a low fractional spur of −69.3 dBc. Thanks to its attachable design, it expedites time-to-market. Regarding mass production, ensuring immunity to process, voltage, and temperature variations is a significant concern. We introduce the circuit techniques employed in the developed fractional divider for immunity to process, voltage, and temperature variations. Subsequently, we provide a comprehensive set of measurement results. The frequency differences over process variations in fractional-N mode is 6.14 ppm. Power supply and temperature dependances are extremely small in spread-spectrum clocking mode. This article illustrates that the developed fractional divider enhances both time-to-market and product reliance.

ARCHITECTURE OF RAILWAY STATION BUILDINGS OF THE RAILWAY IVANO-FRANKIVSK–VORONENKA

The buildings of the Ivano-Frankivsk–Voronenka railway station date back to 1892–1894. The oldest of them were implemented according to three typical projects of the Imperial and Royal Austrian State Railways. They have a spatial, structural and art relationship with the railway stations of Halychyna, Bukovyna and other regions of the sub-Austrian part of the Austro-Hungarian Monarchy. In the interwar period (1921–1939), the damaged buildings of railway stations were restored and new railway stations of Delatyn and Tatariv appeared. After the Second World War railway buildings were rebuilt with a tendency towards simplification. Not seldom passenger buildings appeared on the stop platforms in forms of simple semi-open pavilions. Nowadays, some of the historical buildings are also used for residence, most of them are in good and satisfactory state. All railway stations and stopping points are of the on-bank type, connecting landing platforms with station buildings and settlements on the same ground level. 7 from the 11 original typical railway station buildings of the imperial period have been preserved up till now. They form a chain which is interspersed with the unique buildings of Delatyn, Tatariv, Yaremche and a few passenger buildings near the landing platforms. The primary compositional and stylistic integrity of the architecture of the railway buildings is preserved. All historical buildings of the railway stations of the studied group are worthy and should have the status of an architectural monument. The use of buildings may go beyond transport needs. They can accommodate hotels, restaurants, museums, exhibitions, clubs and other public institutions. This corresponds to the modern trend of understanding and using of such objects. When establishing a regular connection by daytime regional trains in clock mode of railway communication, unified landing platforms with their connection to settlements and with informational and service provision should be arranged. The resources of existing railway station buildings and other passenger facilities should be included in this process.

Studies on thermal profile measurement and fire detection in a power supply cable of a synchrotron radiation source by Raman optical fiber distributed temperature sensor system

The paper presents the work on development and application of Raman optical fiber distributed temperature sensor (ROFDTS). ROFDTS has been used for monitoring the temperature profile and detecting the progress of unforeseen fire events anywhere in a 160 m long power supply cable (current 760 A, DC) of dipole magnets in the Indus-2 synchrotron radiation source (SRS). Indus-2 is a national facility and is being operated in round the clock mode. The sensing fiber could survive in the harsh environment of Indus-2 SRS that consists of bremsstrahlung radiation of 6.7 Rad/h, high magnetic field of 1.5 T and radio frequency (RF) field of 1.27 MV at 505.812 MHz. The fire detecting capability of ROFDTS was first tested on the mock test setup in the laboratory by artificially creating the four hot zones. Each hot zone has the width of 1.0 m in the sensing fiber at the spatial locations of 26 m, 48 m, 70 m and 92 m respectively. An audio-visual alarm was generated when the temperature of the hot zones exceeded the set temperature limit of 50 °C within 30 s of the start of the fire. Finally, ROFDTS system was deployed to measure the temperature profile of power supply cable during ‘no operation’, ‘injection’ of the electron beam current (109 mA with the energy of electrons @ 550 MeV) and at ‘normal operation’ of the electron beam current (145 mA with the energy of electrons @ 2.5 GeV) in Indus-2 SRS. The peak temperature of power cable reached from 26 °C to 44 °C from ‘no operation’ to during the ‘normal operation’ condition of the Indus-2 SRS.

Power Efficient Clock Pulsed D Flip Flop Using Transmission Gate

The need for low-power sequential circuits is pushing towards the implementation of low power consuming basic memory elements like D Flip-Flop. To accomplish power efficient D Flip-Flop, 180 nm CMOS technology is utilized to develop a novel eminent performance Current-Mode Pulse Triggered D Flip-Flop. Instead of voltage utilization in clock distribution is the new idea in the developed method uses current to render low power consumption clock signal. D Flip-Flop is designed by transmission gate which is also reduces the power consumption along with Current-Mode signaling. The Cadence - Virtuoso tool is to be used to simulate all the circuits with 180nm technology. Power consumption reduction in the designed D Flip-Flop is the foremost and major aim of the project. For reducing, power consumption in D Flip-Flop we are employing two methods. They are, Use of Current Mode Clock Distribution Networks (CM-CDN) instead of Voltage Mode Clock Distribution Networks (VM-CDN). Use of Transmission Gate Logic to implement the D Flip-Flop, instead of Static CMOS Logic.

High-Accuracy Real-Time Kinematic Positioning with Multiple Rover Receivers Sharing Common Clock

Since the traditional real-time kinematic positioning method is limited by the reduced satellite visibility from the deprived navigational environments, we, therefore, propose an improved RTK method with multiple rover receivers sharing a common clock. The proposed method can enhance observational redundancy by blending the observations from each rover receiver together so that the model strength will be improved. Integer ambiguity resolution of the proposed method is challenged in the presence of several inter-receiver biases (IRB). The IRB including inter-receiver code bias (IRCB) and inter-receiver phase bias (IRPB) is calibrated by the pre-estimation method because of their temporal stability. Multiple BeiDou Navigation Satellite System (BDS) dual-frequency datasets are collected to test the proposed method. The experimental results have shown that the IRCB and IRPB under the common clock mode are sufficiently stable for the ambiguity resolution. Compared with the traditional method, the ambiguity resolution success rate and positioning accuracy of the proposed method can be improved by 19.5% and 46.4% in the restricted satellite visibility environments.

Power reduction using high speed with saving mode clock gating technique

The demand for low power consumption is motivated by several factors such as the evolution of portable design, reliability effects, and flexibility. The purpose of clock gating is inactive or suppresses change to fragments of the clock route as flip-flop, clock system and rationality under a specific condition processed by clock gating chips. Moreover, the clock is disabled when it is not necessary in clock gating to decrease power dissipation. Clock technique successfully turns off the clock any place it pointlessly expends power. By following the expressed methodology, the force utilization turns out to be less up to half without influencing the performance of the structure. The extraordinary source of power utilization is the clock. Clock signal is not used to achieve any digital calculation. It is for the most part utilized for synchronization of successive circuits. In this way, clock signal does not carry any data. In this research paper, a new sub module for high speed and saving mode is proposed. It saves more power by switch on only the target module and switch other module off. By using this technique, it may reduce power dissipation up to half. In order to execute encoder and decoder structure, the models of compression and decompression process is created by applying Verilog HDL language Quartus II 11.1 Web Edition with 32-Bit. In addition, operational simulation is executed by using ModelSim-Altera 10.0c (Quartus II 11.1 Starter Edition).

Experimental studies on the charge transfer inefficiency of CCD developed for the soft X-ray imaging telescope Xtend aboard the XRISM satellite

We present experimental studies on the charge transfer inefficiency (CTI) of charge-coupled device (CCD) developed for the soft X-ray imaging telescope, Xtend, aboard the XRISM satellite. The CCD is equipped with a charge injection (CI) capability, in which sacrificial charge is periodically injected to fill the charge traps. By evaluating the re-emission of the trapped charge observed behind the CI rows, we find that there are at least three trap populations with different time constants. The traps with the shortest time constant, which is equivalent to a transfer time of approximately one pixel, are mainly responsible for the trailing charge of an X-ray event seen in the following pixel. A comparison of the trailing charge in two clocking modes reveals that the CTI depends not only on the transfer time but also on the area, namely the imaging or storage area. We construct a new CTI model by taking into account both transfer-time and area dependence. This model reproduces the data obtained in both clocking modes consistently. We also examine apparent flux dependence of the CTI observed without the CI technique. The higher incident X-ray flux is, the lower the CTI value becomes. It is due to a sacrificial charge effect by another X-ray photon. This effect is found to be negligible when the CI technique is used.

Density Controlled Traffic Lights System using Aurdino Mega 2560

We have proposed the enhancement of Traffic Light Controller utilizing ultrasonic sensor and microcontroller. The Paper is planned for structuring a thickness based dynamic traffic signal framework where the planning of signal will change consequently on detecting the traffic density at any road junction. Traffic jams are an extreme issue in many urban areas over the world and thusly the time has come to move progressively manual mode or fixed clock mode to a robotized framework with choice making abilities. Present day traffic control framework is fixed time based which may render wasteful on the off chance that one path is operational than the others. To solve this issue, we have made a structure for a clever traffic control system. Some of the time higher traffic density at one side of the intersection requires longer green light time when compared with standard green light time. We, consequently propose here a component where the time of green light and red light is allotted based on the thickness of the traffic present around then. This is accomplished by utilizing ultrasonic sensors which are available on Top of the street.Sometime, in specific intersection of the street junctions extended periods of Red Traffic Light. In instance of any vehicle in crisis circumstance or on the other hand in emergency like VVIPs,a SMS is send to Traffic Control Authority, who has the control of microcontroller empowers microcontroller to change traffic light green for specific time on need premise.

Multi-Stable Operation of a Semiconductor Ring Laser Due to Spatial Hole-Burning

We have theoretically analyzed multi-stability of a symmetric ring laser operating in one single longitudinal mode in the presence of coherent back scattering and inversion-grating-induced mutual coupling of the clockwise and counter-clockwise modes. Our model takes into account the inversion grating created by the standing-wave pattern of the interfering counter-propagating fields and avoids the frequently used ad-hoc introduction of cross and self-saturation coefficients. Our study confirms that linear coupling due to waveguide irregularities or weak interface reflections leads to an effective pump strength below which the clock and anti-clock wise modes are symmetrically coupled whereas above which the grating-induced coupling leads to multi-stability.

An analytical model that links customer-perceived value and competitive strategies

Several authors developed predictive analytic models that link the value that represents customers to a firm (i.e., customer lifetime value) to several outcome variables, such as customer profitability, in relationship marketing. However, similar models that link the value that customers perceive and firm outcomes or customer responses are uncommon. To reduce this gap, we construct an analytic model that links customer-perceived value and a company’s competitive strategy, achieved through a multi-attribute model, analytic hierarchy processing, and a conceptualization of value that considers disparity between benefits and sacrifices. Operationalized in a context of industrial enterprise, the model predicts and orients a company’s competitive strategy and extends generic competitive strategies introduced in Bowman’s strategy clock mode by identifying when two strategies create competitive advantages.

Dual-Mode Operation of an Optical Lattice Clock Using Strontium and Ytterbium Atoms.

We have developed an optical lattice clock that can operate in dual modes: a strontium (Sr) clock mode and an ytterbium (Yb) clock mode. Dual-mode operation of the Sr-Yb optical lattice clock is achieved by alternately cooling and trapping 87Sr and 171Yb atoms inside the vacuum chamber of the clock. Optical lattices for Sr and Yb atoms were arranged with horizontal and vertical configurations, respectively, resulting in a small distance of the order of between the trapped Sr and Yb atoms. The 1S0-3P0 clock transitions in the trapped atoms were interrogated in turn and the clock lasers were stabilized to the transitions. We demonstrated the frequency ratio measurement of the Sr and Yb clock transitions by using the dual-mode operation of the Sr-Yb optical lattice clock. The dual-mode operation can reduce the uncertainty of the blackbody radiation shift in the frequency ratio measurement, because both Sr and Yb atoms share the same blackbody radiation.

Simulation of fast beam ion instability (FBII) in Indus-2 and its experimental observation

Indus-2 is a 2.5 GeV electron storage ring and a national facility for synchrotron radiation users in India providing the photon beam in round the clock mode. Recently, the electron beam emittance of Indus-2 was reduced to one third of the normal operating optics (130 nm rad) with improved beam optics. Due to this reduced emittance, likelihood of fast beam ion instability (FBII) enhances, and that was explored using simulation study. FBII is generated due to the cascading interaction of electron beam with ions that comes across in the path of the beam. This interaction induces oscillation in center of mass of bunches of electron beam and that process increases the transverse beam size, which spoils the effort made in achieving the reduction in beam emittance. For correct understanding of this instability, simulations have been performed with different ring average pressure and considering different per bunch current values. Further, studies have been carried out for two sets of beam optics used for normal emittance and reduced emittance of the electron beam. The simulation method and results are presented in this paper. To observe the signature of this instability, an experiment has been conducted in Indus-2 and its limitations due to operational gas pressure are discussed.

Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression

The clock networks of many modern circuits have to operate in multiple corners and multiple modes (MCMM). We propose to construct mode-reconfigurable clock trees (MRCTs) based on mode separation and scenario compression. The technique of scenario compression is proposed to consider the timing constraints in multiple scenarios at the same time, compressing the MCMM problem into an equivalent single-corner multiple-mode (SCMM), or single-corner single-mode (SCSM) problem. The compression is performed by combining the skew constraints of the different scenarios in skew constraint graphs based on delay linearization and dominating skew constraints. An MRCT consists of several clock trees and mode separation involves, depending on the active mode, selecting one of the clock trees to deliver the clock signal. To limit the overhead, the bottom part (closer to the clock sinks) of all the different clock trees are shared and only the top part (closer to the clock source) of the clock network is mode reconfigurable. The reconfiguration is realized using OR-gates and a one-input-multiple-output demultiplexer. The experimental results show that for a set of synthesized MCMM circuits, with 715 to 13, 216 sequential elements, the proposed approach can achieve high yield.

Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization

A dual-mode circuit is a circuit that has two operating modes: a default high-performance mode at nominal voltage and a secondary low-performance near-threshold voltage (NTV) mode. A key problem that we address is to maximize NTV mode clock frequency. Some cells that are particularly slow in NTV mode are optimized through transistor sizing and stack removal; static noise margin of each gate is extracted and appended in a library so that function failures can be checked and removed during synthesis. A new gate-sizing algorithm is proposed that takes account of timing slacks at both modes. A new sensitivity measure is introduced for this purpose; binary search is then applied to find the maximum NTV mode frequency. Clock-tree synthesis is reformulated to minimize clock skew at both modes. This is motivated by the fact that the proportion of load-dependent delay along clock paths, as well as clock-path delays themselves, should be made equal. Experiments on some test circuits indicate that NTV mode clock period is reduced by 24%, on average; clock skew at NTV decreases by 13%, on average; and NTV mode energy-delay product is reduced by 20%, on average.

Variabiity of the X‐ray broad iron spectral features in active galactic nuclei and black‐hole binaries

AbstractThe “broad iron spectral features” are often seen in X‐ray spectra of active galactic nuclei (AGN) and black‐hole binaries (BHB). These features may be explained either by the “relativistic disc reflection” scenario or the “partial covering” scenario: It is hardly possible to determine which model is valid from time‐averaged spectral analysis. Thus, X‐ray spectral variability has been investigated to constrain spectral models. To that end, it is crucial to study iron structure of BHBs in detail at short time‐scales, which is, for the first time, made possible with the Parallel‐sum clocking (P‐sum) mode of XIS detectors on board of Suzaku. This observational mode has a time‐resolution of 7.8 ms as well as a CCD energyresolution. We have carried out systematic calibration of the P‐sum mode, and investigated spectral variability of the BHB GRS 1915+105. Consequently, we found that the spectral variability of GRS 1915+105 does not show iron features at sub‐seconds. This is totally different from variability of AGN such as 1H0707–495, where the variation amplitude significantly drops at the iron K‐energy band. This difference can be naturally explained in the framework of the “partial covering” scenario. (© 2016 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Design of Current-Mode Pulsed Flip-Flop with Enable for Low power Clock Distribution

In this paper, we propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. The Current-mode (CM) signaling can be used for one-to-many clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flip-flop with enable (CMPFFE) using Tanner tool in 180nm CMOS technology. When the CMPFFE is combined with a CM transmitter, the first CM clock distribution network exhibits 32% lower average power compared to traditional voltage mode (VM) clocks. CM clocking can play an important role in low-power systems. CM signaling offers many potential advantages such as higher operating speed, low voltage operation, ease of processing and reduced power consumption compared to voltage-mode (VM) techniques.

Origin of the X-ray broad iron spectral feature in GRS 1915+105

Abstract The X-ray spectrum of GRS 1915+105 is known to have a “broad iron spectral feature” in the spectral hard state. Similar spectral features are often observed in active galactic nuclei (AGNs) and other black-hole binaries (BHBs), and several models have been proposed for explaining it. In order to distinguish spectral models, time variation provides an important key. In AGNs, variation amplitude has been found to drop significantly at the iron K-energy band at timescales of ∼10 ks. If spectral variations of black holes are normalized by their masses, the spectral variations of BHBs on timescales of sub-seconds should exhibit similar characteristics to those of AGNs. In this paper, we investigated spectral variations of GRS 1915+105 at timescales down to ∼10 ms. This was made possible for the first time with the Suzaku XIS Parallel-sum clocking (P-sum) mode, which has the CCD energy-resolution as well as a time-resolution of 7.8 ms. Consequently, we found that the variation amplitude of GRS 1915+105 does not drop at the iron K-energy band on any timescales from 0.06 s to 63000 s, and that the entire X-ray flux and the iron feature are independently variable at timescales of hours. These are naturally understood in the framework of the “partial covering” model, in which variation timescales of the continuum flux and partial absorbers are independent. The difference of the energy dependence of the variation amplitude between AGNs and BHBs is presumably due to different mechanisms of the outflow winds, i.e., the partial absorbers are due to UV-line driven winds (AGNs) or thermally driven winds (BHBs).

Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop

We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flip-flop with enable (CMPFFE) using 45 nm CMOS technology. When the CMPFFE is combined with a CM transmitter, the first CM clock distribution network exhibits 62% lower average power compared to traditional voltage mode clocks.

A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression

A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UI pp jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 ps rms . The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm 2 only. It dissipates 12.4 mW from 1 V supply.

A new clocking method for a charge coupled device.

We propose and demonstrate a new clocking method for a charge-coupled device (CCD). When a CCD is used for a photon counting detector of X-rays, its weak point is a limitation of its counting rate, because high counting rate makes non-negligible pile-up of photons. In astronomical usage, this pile-up is especially severe for an observation of a bright point-like object. One typical idea to reduce the pile-up is a parallel sum (P-sum) mode. This mode completely loses one-dimensional information. Our new clocking method, panning mode, provides complementary properties between the normal mode and the P-sum mode. We performed a simple simulation in order to investigate a pile-up probability and compared the simulated result and actual obtained event rates. Using this simulation and the experimental results, we compared the pile-up tolerance of various clocking modes including our new method and also compared their other characteristics.