Computer Architecture Classes Research Articles

Development of CPU Simulator Using Microsoft Excel and a Task of Using this Simulator for Computer Architecture

A task of using Microsoft Excel was conducted for a computer architecture class. In this task, an Excel file was used for designing an original CPU and running a program step by step for the designed CPU. First, they designed their CPU on Excel, and then they ran the program written in assembler for their original CPU. After the Excel file was used in a class, a questionnaire survey was conducted. According to the results of the questionnaire survey, almost all students understood how to use this Excel file and almost all students felt that the Excel file was very useful to understand computer architecture.

Continuum Computing - on a New Performance Trajectory beyond Exascale

The end of Moore's Law is a cliche that none the less is a hard barrier to future scaling of high performance computing systems. A factor of about 4x in device density is all that is left of this form of improved throughput with a 5x gain required just to get to the milestone of exascale. The remaining sources of performance improvement are better delivered efficiency of more than 10x and alternative architectures to make better use of chip real estate. This paper will discuss the set of principles guiding a potential future of non-von Neumann architectures as adopted by the experimental class of Continuum Computer Architecture (CCA). It is being explored by the Semantic Memory Architecture Research Team (SMART) at Indiana University. CCA comprises a homogeneous aggregation of cellular components (function cells) which are orders of magnitude smaller than lightweight cores and individually is unable to accomplish a computation but in combination can do so with extreme cost efficiency and unprecedented scalability. It will be seen that a path exists based on such unconventional methods like neuromorphic computing or dataflow that not only will meet the likely exascale milestone in the same time with much better power, cost, and size but also will set a new performance trajectory leading to Zetaflops capability before 2030.

The Integration of Cognitive Learning Strategies in an Undergraduate Computer Architecture Class

The Integration of Cognitive Learning Strategies in an Undergraduate Computer Architecture Class

Interfacing the hardware API with a feature-based operating system family

Multiprocessor systems on a chip (MPSoCs) are a popular class of course-grained parallel computer architectures, which are very useful, because they support re-use of legacy software components and application-specific tailoring of hardware structures at the same time. Furthermore, model-driven design frameworks for MPSoCs such as Xilinx' EDK or our own LavA-framework facilitate very fast system development. However, in this paper we argue that these design frameworks are not ideal from the development process perspective. Instead, we propose a software-centric approach that is based on the hardware API concept. The API is a representation of hardware components on the software level, which is generated from a hardware meta-model. It allows us to automatically derive a hardware structure based on access patterns in software, revealed by a static code analysis. This trick reduces the number of hardware details the developer needs to deal with and avoids configuration inconsistencies between the hardware and software levels by design. Furthermore, we present how the development process can benefit from the hardware API, when the API is interfaced with a configurable operating system.

Synthesizable Manycore Processor Designs with FPGA in Teaching Computer Architecture

Manycore processor architectures are currently very widely used in almost all computer systems. Furthermore, many computer science department have started to teach parallel programming on manycore system platforms. To best understand the parallel programming on those manycore processors, the classes on manycore processor architecture also have to be provided. However, most current undergraduate computer architecture classes have not yet provided. In this paper, we have design a manycore processor design using a conventional MIPS processor design that is considered as a standard processor architecture model in a traditional undergraduate computer architecture class. Synthesize manycore processor models are developed in 850 lines of Verilog-HDL together with simple parallel applications so students can understand the entire manycore processor design and can learn the basics of the manycore system including underlying communication architecture.

Teaching computer architecture through simulation

In our computer architecture class, we researched logic simulators for design of educational computers. We have regularly had students design, create and operate a simulated computer as part of thi...

Secure Digital Cashless Transactions with Sequence Diagrams and Spatial Circuits to Enhance the Information Assurance and Security Education

Often students have difficulties mastering cryptographic algorithms. For some time we have been developing with methods for introducing important security concepts for both undergraduate and graduate students in Information Systems, Computer Science and Engineering students. To achieve this goal, Sequence diagrams and spatial circuit derivation from equations are introduced to students. Sequence diagrams represent progression of events with time. They learn system security concepts more effectively if they know how to transform equations and high level programming language constructs into spatial circuits or special purpose hardware. This paper describes an active learning module developed to help students understand secure protocols, algorithms and modeling web applications to prevent attacks and both software and hardware implementations related to encryption. These course materials can also be used in computer organization and architecture classes to help students understand and develop special purpose circuitry for cryptographic algorithms.

An encryption system in assembly language

This case study discusses the incorporation of encryption systems development into the educational journey of undergraduate computer science or game development majors. We discuss the experience of first semester Daniel Webster College sophomores who attempted to develop the German WWII ENIGMA encryption system in assembly language. By incorporating a real world encryption system project into a beginning computer architecture class students become deeply immersed in numbering systems, hardware logic design, operating system services and, of course instruction set architectures. Of necessity, they also must refine and develop their programming skills to an extraordinary degree. During the past seven years we have found that most students can develop a complete software version of the complex and amazing ENIGMA encryption system. We outline in this paper the strategy that seems to lead to a successful outcome for most students.

Switching from computer to microcomputer architecture education

In the last decades, the technological and scientific evolution of the computing discipline has been widely affecting research in software engineering education, which nowadays advocates more enlightened and liberal ideas. This article reviews cross-disciplinary research on a computer architecture class in consideration of its switching to microcomputer architecture. The authors present their strategies towards a successful crossing of boundaries between engineering disciplines. This communication aims at providing a different aspect on professional courses that are, nowadays, addressed at the expense of traditional courses.

PerfPred: A web‐based tool for exploring computer architecture design space

AbstractThis paper presents a Web‐based tool for predicting the performance of computer systems. The tool can be used for teaching how the hardware configurations (processor microarchitecture, memory hierarchy, etc.) and/or software (benchmark program) characteristics can affect the system throughput. Use of the proposed tool in computer architecture classes has demonstrated its effectiveness in improving the students' understanding of the related topics. © 2009 Wiley Periodicals, Inc. Comput Appl Eng Educ 17: 305–313, 2009; Published online in Wiley InterScience (www.interscience.wiley.com); DOI 10.1002/cae.20243

Iterative scheduling algorithms based on the subdivision of the solution space into domains

Iterative multiprocessor scheduling algorithms are considered. The iterative algorithms make it possible to solve scheduling problems for a wide class of computer architectures but are very intricate from the computational point of view. To simplify the iterative algorithms, we propose an approach to their construction based on the subdivision of the space of correct schedules into disjoint domains, namely, an algorithm for constructing domains is proposed, the operations of the schedule transformations closed within the domains are introduced, and a technique for cutting off domains is developed. The approach developed also makes it possible to construct parallel algorithms with a low traffic of the exchange between parallel processes.

MarieSim

MarieSim is a computer architecture simulator based on the MARIE architecture and designed to teach beginning computer organization and architecture. It provides users with interactive tools and simulations to help them deepen their understanding of the operation of a simple computer.Through interaction with MarieSim's graphical environment, students can observe how assembly language statements affect the registers and memory of a computer system. The graphical environment for MarieSim and the accompanying data path simulator are written in Java Swing; the integrated MARIE assembler is written in Java. The software has proven useful in introductory computer organization and architecture classes. Students find MarieSim very easy to use, and anecdotal results indicate increased architectural understanding. In this article we compare MarieSim to various existing systems and explore the software's features in detail.

Dual-Level Parallel Analysis of Harbor Wave Response Using MPI and OpenMP

The authors describe their experiences converting an existing serial production code to a parallel code combining both MPI and OpenMP. Such dual-level parallel codes will be able to take full advantage of the emerging class of high performance computer architectures using small clusters of shared-memory processors connected via a message-passing network. While the focus is restricted to a harbor response simulation code, the techniques presented herein are appropriate for a broad class of applications that explore a parameter space. The code modifications reduced the execution time of one test case from 3100 minutes on a single CPU to just over 12 minutes on 256 CPUs. Results demonstrate that dual-level parallelism allows substantial increases in model resolution combined with improvements in simulation turnaround time but, contrary to conventional wisdom, requires very little source code alteration.

A VHDL synthesis model of the MIPS processor for use in computer architecture laboratories

This paper describes and contains the necessary VHDL files to synthesize and simulate a MIPS 32-bit RISC processor core for use in introductory computer architecture classes. This MIPS processor core is based on the design presented in chapters 5 and 6 of the widely used text, Computer Organization and Design the Hardware/Software Interface by David Patterson and John Hennessy. IEEE Standard Logic 1164 is used in the VHDL model and versions are provided for several popular CAD tools. Our experiences in using this model in our introductory computer architecture classes, CmpE 2510 and CmpE 3510, during the past two years are described along with typical laboratory assignments.

Using simulation with hardware verification for teaching computer architecture

AbstractMaterial for a computer architecture class based on four progressively more complex microprogrammed circuits is described. The circuits and their associated microassemblers and simulators are discussed. Interestingly, the simulators allow students to understand the workings of the hardware more fully than is possible using the hardware alone.

On the design and use of a simulator for teaching computer architecture

Most Computer Architecture classes include dicussions of machine instructions and CPU internals, but not many include input/output devices, either as part of that course, or elsewhere in the program. This paper discusses a simulator designed to allow students to work with simulated I/O devices as a part of larger machine simulator.

Providing a laboratory for instruction set design

Computer architecture classes do not provide students with laboratory experience in the design of instruction set architectures. Projects that compare designs have not been possible due to a lack of support software. The design and evaluation of a new instruction set requires an assembler, a symbolic debugger, and a statistics gatherer. Every new instruction set requires changes to all three programs. It would be unrealistic to expect that either students or instructor would (re)write such software in order to evaluate each new design. A new, flexible software package called the Instruction Set Testbed (IST) provides for the comparison of instruction set architectures without writing any of the support software. IST's table-driven assembler uses a student-supplied architecture definition to assemble programs. IST's interactive debugger and a statistics gatherer also have access to the architecture definition. This allows symbolic debugging of the assembly language programs and automatic histogramming of instruction usage in the student-defined architecture. IST has been used in both undergraduate and graduate architecture classes to investigate such topics as orthogonality, choice and number of operands, addressing modes, and RISC philosophy.

Machine instructions of a data-driven architecture — Design considerations

A major trend in the future use of computers is in the artificial intelligence (AI) field. There is a strong need for a new class of concurrent parallel computer architectures for solving complicated problems. Natural candidates for a parallel implementation are the data driven architectures. The existing data driven machines have some critical shortcomings for the implementation of AI systems. This paper deals with the design considerations of the instructions set, and their execution algorithms, of a new machine which was designed by the authors to be efficient in List processing and parallel execution even on large data structures. The proposed architecture manipulates data and instructions in a similar way which contributes to the machine's regularity and ability to execute AI programs. This paper presents the unusual concepts which were introduced into the system architecture from the viewpoints of its data structure and machine instructions.

Concurrent VLSI Architectures

This tutorial paper addresses some of the principles and provides examples of concurrent architectures and designs that have been inspired by VLSI technology. The circuit density offered by VLSI provides the means for implementing systems with very large numbers of computing elements, while its physical characteristics provide an incentive to organize systems so that the elements are relatively loosely coupled. One class of computer architectures that evolve from this reasoning include an interesting and varied class of concurrent machines that adhere to a structural model based on the repetition of regularly connected elements. The systems included under this structural model range from 1) systems that combine storage and logic at a fine grain size, and are typically aimed at computations with images or storage retrieval, to 2) systems that combine registers and arithmetic at a medium grain size to form computational or systolic arrays for signal processing and matrix computations, to 3) arrays of instruction interpreting computers that use teamwork to perform many of the same demanding computations for which we use high-performance single process computers today.