Class AB Power Amplifier Research Articles

A Compact GaN Power Amplifier Module for New Generation Cellular Basestations

This paper presents a compact class-AB Power Amplifier Module (PAM) designed for new generation massive Multiple Input Multiple Output (MiMo) cellular base stations. The module is designed at the center frequency of 3.5GHz targeting Long Term Evolution (LTE) and 5G New Radio (NR) bands. The module is a hybrid design that incorporates a Gallium Nitride (GaN) High Mobility-Electron Transistor (HEMT) die, discrete components-based input, and output matching networks. The entire design is realized on an 8.5 x 5.2 mm, 2-layer Rogers4003C substrate. The module is assembled on a PCB as an open-top for post-characterization tuning. The small signal and large signal measurements are in quite good agreement. The measurement results show that the amplifier is unconditionally stable, the input return loss is 12.2 dB, the output return loss is 7.7 dB, and the small signal gain is 13.4 dB. The saturated output power is 33.3 dBm with a Power Added Efficiency of 20.1%. The small signal gain drops to 11.2 dB at around 22 dBm of input power due to GaN technology’s intrinsic soft compression characteristics.

A 24−30 GHz 8-element dual-polarized 5G FR2 phased-array transceiver IC with 20.8-dBm TX OP1dB and 4.1-dB RX NFin 65-nm CMOS

This article presents an 8-element dual-polarized phased-array transceiver (TRX) front-end IC for millimeter-wave (mm-Wave) 5G new radio (NR). Power enhancement technologies for power amplifiers (PA) in mm-Wave 5G phased-array TRX are discussed. A four-stage wideband high-power class-AB PA with distributed-active-transformer (DAT) power combining and multi-stage second-harmonic traps is proposed, ensuring the mitigated amplitude-to-phase (AM-PM) distortions across wide carrier frequencies without degrading transmitting (TX) power, gain and efficiency. TX and receiving (RX) switching is achieved by a matching network co-designed on-chip T/R switch. In each TRX element, 6-bit 360° phase shifting and 6-bit 31.5-dB gain tuning are respectively achieved by the digital-controlled vector-modulated phase shifter (VMPS) and differential attenuator (ATT). Fabricated in 65-nm bulk complementary metal oxide semiconductor (CMOS), the proposed TRX demonstrates the measured peak TX/RX gains of 25.5/21.3 dB, covering the 24−29.5 GHz band. The measured peak TX OP1dB and power-added efficiency (PAE) are 20.8 dBm and 21.1%, respectively. The measured minimum RX NF is 4.1 dB. The TRX achieves an output power of 11.0−12.4 dBm and error vector magnitude (EVM) of 5% with 400-MHz 5G NR FR2 OFDM 64-QAM signals across 24−29.5 GHz, covering 3GPP 5G NR FR2 operating bands of n257, n258, and n261.

Development and validation of a novel bias network design method for a class AB PA

AbstractIn this paper, the impact of the bias networks on a radio frequency (RF) power amplifier (PA) is analyzed and discussed comprehensively. Both the different sizes and positions of the bias microstrip line circuit have been studied for a broadband class AB PA. Both simulations and measurements show that the performance of the PA can be greatly improved with the adjustment of the bias circuit by effecting the harmonic impedance of the whole matching circuit. Compared with the existing works, the fabricated PA based on the proposed technique provides the best performance, thereby demonstrating the effectiveness of the developed bias circuit optimization method.

Nonlinear Capacitance Compensation Technique in a Linearity-Enhanced and Broadband GaN PA MMIC for Ku-/K-Band Applications

This article reports on exploiting a nonlinear capacitance compensation technique to achieve high linearity for power amplifier (PA) designs in III–V semiconductor technologies. High linearity is achieved by implementing multiple transistors with deliberate sizes and biasing to compensate for each nonlinear input capacitance behavior. Therefore, the composed PA core acts as one large device where each subdevice is biased individually. Moreover, this approach proves to be a reliable and easy way to improve PA linearity in III–V semiconductor technologies. The viability of this compensation is demonstrated by comparing it to other analog linearity improvement techniques such as derivative superposition. As a proof-of-concept prototype, a 17.2–20.2-GHz class-AB PA is designed in a space-evaluated 150-nm gallium nitride (GaN)-on-silicon carbide (SiC) process. Its capabilities are validated for various modulation bandwidths up to 500 MHz at several frequencies while delivering 32 dBm of output power. The measured third-order intermodulation distortion (IMD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_3$</tex-math> </inline-formula> ) and the fifth-order intermodulation distortion (IMD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_5$</tex-math> </inline-formula> ) are improved by 18 and 25 dB, respectively, compared to a class-AB design. The measured amplitude-to-phase (AM–PM) distortion of less than 0.07 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^\circ$</tex-math> </inline-formula> is obtained over the entire bandwidth. Finally, noise-to-power ratio (NPR) results prove the linearity enhancement concept with values better than 15 dB up to maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\rm out}$</tex-math> </inline-formula> . All the results were measured without any applied digital predistortion (DPD).

Meta Analytic Review on Recent Advancements of Class AB Power Amplifiers

The ever-increasing complexity and prohibitive fabrication costs associated with VLSI circuits necessitate the development of techniques that prioritize low power consumption and high-speed analog blocks. In today’s era of smart IoT devices, which are pervasive and heavily reliant on efficient battery backups, the demand for low power architectures is paramount to preserve battery life and reduce weight. Simultaneously, maintaining high-speed performance and incorporating additional features is crucial in the wireless industry. Amplifiers, being fundamental front-ends in transceiver design, significantly impact the overall performance of transceivers. Consequently, this study aims to provide a comprehensive and systematic review of amplifier techniques, with a specific focus on low-power and high-speed approaches, following the Preferred Reporting Items for Systematic Review and Meta-Analysis (PRISMA) methodology. The findings presented herein identify the current state of research in the defined area and highlight potential avenues for future exploration.

Selective Algorithm for Expanded Group Method of Data Handling Applied to Power Amplifier Modeling

Power amplifiers (PAs) are electronic devices commonly used in telecommunications that need to transmit information with high energetic efficiency. For this, it is necessary to use data manipulation methods that assist in the linearization of the output signal. Our previous conference paper presented two codes constructed based on the Group Method of Data Handling (GMDH) and which differ in their way of selecting the best coefficients to be used in the calculations of the neural network. The first method, called Embracing, assumes greater availability of data, while the second, called Selective, selects information from the beginning of the code. This work extends the previous GMDH models by expanding the PA inputs into Laguerre basis functions with a single real pole. The comparison among the different approaches employs experimental data collected from a GaN HEMT class AB PA and a Si LDMOS class AB. The most selective and computationally more complex structure, when searching for identification since from the first layers, expresses minor errors and the best results in the output for both Conventional and Expanded GMDH models, becoming a reasoned option for use in PAs. A normalized mean square error (NMSE) of -35.44 dB was obtained by Expanded GMDH with Selective algorithm and 5 inputs when using the GaN PA, whereas a NMSE of -40.35 dB was obtained by the Expanded GMDH with Selective algorithm and 4 inputs when calculated with the Si LDMOS PA data.

A 24–29.5-GHz Highly Linear Phased-Array Transceiver Front-End in 65-nm CMOS Supporting 800-MHz 64-QAM and 400-MHz 256-QAM for 5G New Radio

This article presents a four-element phased-array transceiver (TRX) front-end for millimeter-wave (mm-Wave) 5G new radio (NR). The effects of amplitude-to-phase (AM–PM) and amplitude-to-amplitude (AM–AM) distortions on error vector magnitude (EVM) are detailed. A three-stage highly linear wideband class-AB power amplifier (PA) is described, mitigating AM–PM and AM–AM distortions without degrading other performances. A matching network embedded transmitting/receiving (T/R) switch is proposed to support time division duplex (TDD). With the proposed technique, RF switch insertion losses are reduced in both transmitter (TX) and receiving (RX) modes. In each TRX element, phase and gain controls are achieved by a 6-bit vector-modulated phase shifter (VMPS) with a phase tuning range of 360° and a 6-bit attenuator with a gain tuning range of 31.5 dB, respectively. Fabricated in 65-nm bulk CMOS, the proposed packaged TRX demonstrates the measured peak gains of 25.5/14.2 dB with the gain ripples of less than 2.5/1.9 dB across 24–29.5 GHz in the TX/RX mode. The measured peak <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {1 dB}}$ </tex-math></inline-formula> is 17.6 dBm with a power added efficiency (PAE) of 20.4%. The measured minimum noise figure (NF) is 4.3 dB. The TRX achieves an output power of 7.9–8.9 dBm and an EVM of −25 dB with 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 100-MHz 5G NR frequency range 2 (FR2) orthogonal frequency division multiplexing (OFDM) 64-quadrature amplitude modulation (QAM) signals across 24–29.5 GHz, covering 3rd generation partnership project (3GPP) 5G NR FR2 operating bands (i.e., n257, n258, and n261) around 26 GHz.

High linear low voltage CMOS power amplifier for 2.4 GHz applications

ABSTRACT Wireless technology is a growing technology in which lot of attention move towards 2.4 GHz frequency applications. In transceiver front end, power amplifier is an important block of a transmitter. A low voltage power amplifier is proposed using 0.13 µm TSMC CMOS process. In this proposed work, single-ended two stage class AB power amplifier is designed and RF distortion technique is applied to improve linearity. The high linearity low voltage power amplifier is designed and simulated using ADS simulator. The optimised power amplifier produces 18 dB gain, 21.6% PAE, 21.7 dBm of OIP3 and 5.86 mA current consumption at 0.8 V supply voltage.

Review of Efficiency CMOS Class AB Power Amplifier Topology in Gigahertz Frequencies

This paper reviewed the efficiency of CMOS class AB power amplifier topology especially in gigahertz frequencies. CMOS class AB power amplifier is a compromise between class A and class B in terms of linearity and efficiency between 50% to 78.5%. However, CMOS class AB power amplifier cannot have good linearity and efficiency simultaneously due to the breakdown in gate-oxide voltage and effects from hot carrier. The breakdown of oxide prevents optimum drain signal and the effect from hot carrier will reduce the quality of the overall PA design. Several works from year 1999 to 2019 with different topology such as multiple gated transistor, cascode, feedforward linearization, differential circuit, transformer combining method with common source harmonic termination and combination of a dual-switching transistor with a third harmonic tuning technique are discussed and the performances of the power amplifier are compared. The best three CMOS class AB power amplifier topologies were chosen in terms of high efficiency. The topologies are two stages with integrated input and interstage matching, Doherty amplifier combined with drain modulation based architectures and self-biased cascode topology that obtained power added efficiency of 45%, 43% and 42%, respectively. Key performance indicators for class AB power amplifier include frequency, power added efficiency, gain and output power are also discussed in this paper.

Behavioral modeling and digital predistortion of RF power amplifiers based on time-delay kernel ridge regression

This paper, investigates and presents the behavioral modeling and digital pre-distortion (DPD) of radio frequency power amplifiers (RFPAs) using a time-delay kernel ridge regression (KRR) algorithm. The KRR is an advanced machine learning algorithm that can be effectively used for modeling the baseband characteristics of the RFPA considering both the effects of memory and transistor non-linearity. Compared to the traditional artificial neural network (ANN) based approach which is computationally intensive, the proposed approach using KRR with radial basis kernel function and min-max normalization method, extracts the PA behavioral and DPD model in a short time and yield consistently better results. The performance of the proposed approach in extracting PA and DPD model is demonstrated experimentally on a GaN based class AB power amplifier. The experimental results illustrates that, when compared to ANN based model, the proposed approach yields more accurate PA and DPD models, with an improvement in modeling performance by 2 dB in terms of normalized mean square error (NMSE). In addition, compared to the ANN based approach, the DPD model developed using the proposed approach exhibit improved linearization performance in suppressing spectral regrowth due to PA non-linearity.

High‐efficiency broadband power amplifier design via ideal de‐embedding and direct compensation of GaN‐HEMTs parasitics

In this work, a design approach for broadband high-efficiency power amplifiers is presented. The proposed technique is based on deductive de-embedding of the nonlinear parasitics of packaged GaN-HEMT devices. A new transistor parasitics equivalent network is proposed that utilises a model-based extraction flow. A simple two-element compensation network is then used to accurately compensate the extracted nonlinear device parasitics; this enables optimum load resistance to be presented to the device current generator using a real-to-real matching network. In order to validate the proposed concept, a single-ended Class-AB power amplifier is designed and fabricated using a Wolfspeed 25-W GaN HEMT ‘CGH40025F’ transistor. At a centre frequency of 2.35 GHz, a fractional bandwidth of 55% is achieved. The measured average drain efficiency and power gain of the designed power amplifier are 71% and 10.4 dB, respectively.

A 24-GHz Fully Integrated CMOS Transceiver for FMCW Radar Applications

A 24-GHz fully integrated frequency-modulated continuous wave (FMCW) direct conversion transceiver, implemented in a 55-nm low-power CMOS technology with a maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm {T}}$ </tex-math></inline-formula> of 190 GHz in typical operating conditions and packaged in a 5-mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 5-mm 32-lead quad-flat no-leads (QFN) package, is presented in this article. The single-chip transceiver uses a single 2.5-V supply while all the core circuits are powered by integrated regulators. The complex low-noise transductor in the receiver uses a quadrature hybrid to generate quadrature signals in the receiving front-end. The analog signal processing circuits including high-pass filters, low-pass filters, and programmable amplifiers are implemented following the receiver front-end circuitry. The FMCW signals are generated by an on-chip 24-GHz fractional-N frequency synthesizer. The synthesizer is completely integrated with the transceiver and provides built-in digital frequency modulation to generate chirping signals for the down-conversion local oscillator (LO) and the transmitted signals. The transmitter is composed of a balanced class-AB power amplifier driven by the FMCW signals from the frequency synthesizer.

A Bivariate Volterra Series Model for the Design of Power Amplifier Digital Predistorters.

The operation of the power amplifier (PA) in wireless transmitters presents a trade-off between linearity and power efficiency, being more efficient when the device exhibits the highest nonlinearity. Its modeling and linearization performance depend on the quality of the underlying Volterra models that are characterized by the presence of relevant terms amongst the enormous amount of regressors that these models generate. The presence of PA mechanisms that generate an internal state variable motivates the adoption of a bivariate Volterra series perspective with the aim of enhancing modeling capabilities through the inclussion of beneficial terms. In this paper, the conventional Volterra-based models are enhanced by the addition of terms, including cross products of the input signal and the new internal variable. The bivariate versions of the general full Volterra (FV) model and one of its pruned versions, referred to as the circuit-knowledge based Volterra (CKV) model, are derived by considering the signal envelope as the internal variable and applying the proposed methodology to the univariate models. A comparative assessment of the bivariate models versus their conventional counterparts is experimentally performed for the modeling of two PAs driven by a 30 MHz 5G New Radio signal: a class AB PA and a class J PA. The results for the digital predistortion of the class AB PA under a direct learning architecture reveal the benefits in linearization performance produced by the bivariate CKV model structure compared to that of the univariate CKV model.

A Low-Loss Load Correction Technique for Self-Healing Power Amplifiers Using a Modified Two-Tap Six-Port Network

This article presents a low-loss correction technique for a self-healing load-insensitive power amplifier (PA) using a modified two-tap six-port network, wherein the varying (complex) load is first compensated for its unwanted susceptance part, followed by adjustment of the transistor output stage to the ohmic load variation, by modifying its supply voltage and drive level. This two-step approach avoids the high-Q conditions that occur in tunable matching network solutions, which aims to correct for both the real and imaginary load deviations, such as providing lower insertion loss and voltage stress. Next, to facilitate a fully automated load mismatch correction without the need for calibration, a modified two-tap six-port network for impedance detection and control loop approach is proposed. As proof of principle, a prototype 900-MHz class-AB PA featuring the proposed correction technique, as well as, the six-port reflectometer and the control loop, has been implemented as a PCB demonstrator. Measurement results show that the self-healing load-insensitive PA in the events of load mismatch significantly improves the performance and approaches the 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> performance. On a 2:1 VSWR 360° mismatch trajectory and driven by a 64-QAM 3.86-MHz signal, the PA achieves a linear output power of 22 dBm with only ±0.1-dB variation and better than −45-dBc adjacent channel power ratio (ACPR).

High Efficiency, Good phase linearity 0.18 µm CMOS Power Amplifier for MBAN-UWB Applications

This paper presents the design of 3.1-10.6 GHz class AB power amplifier (PA) suitable for medical body area network (MBAN) Ultra-Wide Band (UWB) applications in TSMC 0.18 µm technology. An optimization technique to simultaneously maximize power added efficiency(PAE) and minimize group delay variation is employed. Source and Load-pull contours are used to design inter and output stage matching circuits. The post-layout simulation results indicated that the designed PA has a maximum PAE of 32 % and an output 1-dB compression of 11 dBm at 4 GHz. In addition, a small group delay variation of ± 50 ps was realized over the whole required frequency band . Moreover, the proposed PA has small signal power gain (S21) of 12.5 dB with ripple less than 1.5 dB over the frequency range between 3.1 GHz to 10.6 GHz, while consuming 36 mW.

Upgrading Behavioral Models for the Design of Digital Predistorters.

This work presents a strategy to upgrade models for power amplifier (PA) behavioral modeling and digital predistortion (DPD). These incomplete structures are the consequence of nonlinear order and memory depth model truncation with the purpose of reducing the demand of the limited computational resources available in standard processors. On the other hand, the alternative use of model structures pruned a priori does not guarantee that every significant term is included. To improve the limited performance of an incomplete model, a general procedure to augment its structure by incorporating significant terms is demonstrated. The sparse nature of the problem allows a successive search incorporating additional terms with higher nonlinear order and memory depth. This approach is investigated in the modeling and linearization of a commercial class AB PA operating at a compression point of about 6 dB, and a class J PA operating near saturation. Results highlight the capabilities of this upgrading procedure in the improvement of linearization capabilities of DPDs.

A Reduced-Complexity Direct Learning Architecture for Digital Predistortion Through Iterative Pseudoinverse Calculation

In this letter, a novel approach is proposed for digital predistortion (DPD) with direct learning architecture (DLA). Regression of a Volterra behavioral model requires the pseudoinverse of a matrix, which needs many resources due to the inverse operation when the Moore–Penrose pseudoinverse is used. This work substitutes the pseudoinverse calculation by a polynomial expansion (PE) method to obtain a polynomial expansion direct learning architecture (PE-DLA), which attains a pseudoinverse in an iterative fashion avoiding the inverse operation and consequently reducing the algorithm computational complexity. Experimental results show that the number of iterations in the PE-DLA affects the convergence speed. The proposal is benchmarked against other state-of-the-art approaches such as the classic DLA and the covariance matrix DLA (CM-DLA) in the DPD of a commercial class AB power amplifier, concluding that the linearization performance of the current proposal is equivalent to others while featuring simple operations.

Group Digital Predistortion With Step Uniformization for Hybrid Beamforming Transmitters

This letter proposes a group digital predistorter with step uniformization (SU-GDPD) for massive multi-input multi-output (MIMO) transmitters with hybrid beamforming architecture. Analog predistorters (APDs) are employed to iteratively adjust the nonlinear character of the power amplifiers (PAs) that are sharing one radio frequency (RF) chain. The shared digital predistortion (DPD) parameter and the APD control voltage (ACV) are optimized alternately to achieve the best linearity. This step optimization process avoids extensive search of the ACV combination, which causes much time and calculation resource consumption. Furthermore, SU-GDPD has the adaptability to handle the nonlinearity variation of each PA. Two class-AB PAs with the peak output power of 42 dBm are tested to verify the validation of the proposed SU-GDPD. With the stimulation of the 100-MHz long-term evolution advanced (LTE-A) signal, the two PAs have an average output power of 31 dBm. The adjacent channel power ratio (ACPR) of the two PAs is improved by 19.8-22 dB simultaneously by the proposed SU-GDPD.

A Reconfigurable Class-AB/F Power Amplifier for 0.1–4.2 GHz Multistandard Applications

In this paper, a reconfigurable multi-mode Class-AB/F power amplifier (PA) is proposed for 0.1–4.2 GHz multistandard applications. The PA operates in linear mode (class-AB) for variable-envelope modulated signals and switching mode (class-F) for constant-envelope modulated signals. The proposed linear mode PA design is suitable for multi-band LTE, IOT, WSN and multi-standard RF transmitter, while switching mode PA design can be used in multi-band IOT-LPWA and BLE (Bluetooth Low Energy) RF transmitter. The proposed PA has a reconfigurable off-chip inter-stage and output matching networks over the specified frequency band, while the input stage is Complementary Current-Reuse common-gate with active shunt feedback configuration to achieve Ultra-Wideband (UWB) input matching. The proposed multi-mode PA is designed using a 130 nm CMOS process. Class-AB PA has a saturated output power of 23.5 dBm ± 1 dB over 0.1–4.2 GHz, a power-added efficiency (PAE) of 41%, a third-order intercept point (OIP3) of 17 dBm, and adjacent channel power ratio (ACPR) of − 29.3 dBc for LTE 15 MHz channel bandwidth. The maximum PAE of 62.1% under the class-F operation is achieved at output power of 24.5 dBm. The PA occupies 0.64 mm2 of chip area, while the estimated off-chip area is 13.3 mm2. The proposed PA consumes 164 mW, and 16 mW in class-AB and class-F, respectively.

Design of a 60 GHz 32% PAE Class-AB PA with 2ndHarmonic Control in 45-nm PD-SOI CMOS

This paper presents a 60 GHz highly efficient singlestage differential stacked Class-AB power amplifier (PA) with second harmonic control (HC) for short range applications using mm-wave radar. The circuit is realized in a 45nm partially depleted sillicon-on-insulator (PD-SOI) CMOS technology. Measurement results show that the power amplifier achieves a saturated output power (Psat) of 16.4dBm with a competitive maximum power-added efficiency (PAEmax) of 32% at 60 GHz. The output-referred 1-dB compression point (OP1dB) is 9.5 dBm. Furthermore, the circuit draws 40mA from a single 1.8V supply and the chip core size is 0.36mm $\times\,\,0.35$ mm.