class-AB Operational Amplifier Research Articles

A design approach for class-AB operational amplifier using the gm/ID methodology

A design approach for class-AB operational amplifier using the gm/ID methodology

Rail-to-rail input/output bulk driven class AB operational amplifier with improved composite transistors

Rail-to-rail input/output bulk driven class AB operational amplifier with improved composite transistors

A 10-Bit 20 Channel LCD Column Driver Using Compact DAC

A 20-channel liquid crystal display (LCD) driver architecture is implemented with [Formula: see text]m CMOS technology. This work presents a novel design of 10-bit compact and high-resolution two-stage DAC to improve the linearity and uniformity of each channel performance. A complete column driver, including a compact DAC, low power buffer, global R-string and multiplexing circuit design, is implemented, and the layout of this 20-channel, 10-bit LCD driver is generated using [Formula: see text]m CMOS technology. All the circuit blocks of the proposed LCD column driver were simulated using the EDA tool HSPICE and layout generation by Laker. This work also realizes a high-performance class AB operational amplifier with a gain of 140[Formula: see text]dB for the proposed LCD driver. The 10-bit compact LCD driver has a 1.4 mV LSB and an output voltage of 1.7 V is achieved for the input range of 0.25–1.7[Formula: see text]V. The compact DAC voltage selector with decoder in this design uses fewer switches in comparison to conventional tree-type RDAC, occupying a smaller chip area with fast response. The proposed design is sufficiently robust for high-color depth and resolution LCD driver applications. The experimental results exhibit maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.065 LSB and −0.12 LSB, respectively. The one channel area is [Formula: see text]m and the settling time is [Formula: see text]s for the [Formula: see text] and 20[Formula: see text]pF driving load.

A Review of Techniques to Enhance an Amplifier’s Performance Using Resistive Local Common Mode Feedback

A review of some of the most common applications of the resistive local common mode feedback technique to enhance amplifier’s performance is presented. It is shown that this simple technique offers essential improvement in open loop gain, gain-bandwidth product, slew rate, common mode rejection ratio, power supply rejection ratio, etc. This is achieved without increasing power dissipation or supply voltage requirements and with small additional silicon area and circuit complexity. It is also shown that it is especially appropriate to improve amplifiers’ performance in current fine-line submicrometer CMOS technology. Some of the applications discussed are GB enhanced, class AB and super class AB operational amplifiers, gain boosted op-amps, bulk-driven circuits, sample and hold circuits and power management circuits, among others.

High current operational amplifier with current limiting protection circuit

In this work, a class-AB operational amplifier is to be presented, which is developed in a 0.5 μm CDMOS technology. The proposed amplifier is composed of a folded cascade input stage and a class-AB output stage. Owing to the special design of the operational amplifier, the robustness of the whole circuit has been enhanced. The proposed system can drive a wide resistance load range from 10 Ω to 100 kΩ with a 10 pF capacitance load without distortion and stability problems. In addition, a current-limit technique that stems from the design of a low dropout linear regulator is adopted to protect the output stage of the operational amplifier from being damaged by a huge transient current under unexpected conditions (when the output terminal is shorted to ground or V DD). Measurement results show that the maximum output current is nearly 390 mA with an 800 mA DC current limiting protection circuit on the single 5 V power supply at room temperature. This design can stably work at the industrial temperature range from −40 to 125°C. What is more, the total static current consumption of the whole circuit is 624 μA and the chip area is 0.419 mm2.

Multi-Path Class AB Operational Amplifier with High Performance for SC Circuits

In this paper, a single-stage multi-path operational transconductance amplifier (OTA) with fast-settling response for high performance applications is designed. The produced amplifier uses current-shunt technique, double recycling structure, cross-coupled positive feedback configuration and all idle devices in the signal path to enhance transconductance of the conventional folded cascode (FC) amplifier. These transconductance boosting techniques lead to higher DC gain, gain bandwidth (GBW), slew rate and lower settling time compared to the previous FC structures while phase margin is degraded. Simulation results are presented using 90 nm CMOS technology which show 1,800% increment in GBW and a 33.2 dB DC gain improvement in the approximately same power consumption compared to the conventional FC amplifier.

A three-stage class AB operational amplifier with enhanced slew rate for switched-capacitor circuits

In this paper, a three-stage class AB operational transconductance amplifier (OTA) with large slew rate is presented. The reversed nested Miller compensation technique is used to stabilize the proposed OTA, allowing the slew rate enhancement to be achieved by using class AB input and output stages. A flipped-voltage follower cell in the first stage in combination with a switched-capacitor level shifter in the last stage are utilized to implement the class AB operation. Circuit level simulation results are provided using HSPICE and a 90 nm CMOS technology which show 306 % enhancement in the large-signal FoM with approximately the same power dissipation compared to the class A OTA. The achieved settling time with 0.02 % accuracy for the proposed class AB and conventional class A OTAs are 7.5 and 15.3 ns, respectively.

A high-performance 1.2 V–99 μW rail-to-rail CMOS class AB amplifier

This paper presents a compact, reliable 1.2V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated battery powered systems which require rail-to-rail input/output swing and high slew-rate while maintaining low power consumption. The OpAmp, fabricated in a standard 0.18μm CMOS technology, exhibits 86dB open loop gain and 97dB CMRR. Experimental measurements prove its correct functionality operating with 1.2V single supply, performing very competitive characteristics compared with other similar amplifiers reported in the literature. It has rail-to-rail input/output operation, 5MHz unity gain frequency and a 3.15V/μs slew-rate for a capacitive load of 100pF, with a power consumption of 99μW.

Distortion Modeling of Class-AB Opamp with Nonlinear Coefficients Derived by Least Square Method

The distortion of class-AB operational amplifier is modeled in this paper. The signal path of the class-AB amplifier is approximated by two third-order polynomials with different coefficients. These coefficients can be obtained by exploring the DC characteristics. With the help of Fourier transform, the analytical expressions of harmonic components and distortion factors are derived also. The agreement between simulated results and theoretical analyses validated the modeling in this paper.

An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator With Assistant Push–Pull Output Stage

An output capacitor-free low-dropout regulator (LDO) using a class-AB operational amplifier and an assistant push–pull output stage (APPOS) circuit to enable fast-transient response with ultralow-power dissipation is presented in this brief. The APPOS circuit is proposed to deliver an extra current that is directly proportional to the output current of the class-AB operational amplifier during transient state with an automatic on/off feature. Moreover, the small-signal and large-signal responses of LDO can be separately optimized. As a result, transient performances of LDO are improved significantly without requiring an area-consuming on-chip capacitor anymore. The proposed LDO has been implemented in a standard 0.35- $\mu\hbox{m}$ CMOS process. Experimental results show that the LDO can regulate the output voltage at 1.0 V from a 1.2-V supply voltage for the maximum load current of 100 mA. The output voltage fully recovers within 2.7 $\mu\hbox{s}$ with the load current switching from 100 $\mu\hbox{A}$ to 100 mA at a 1.2- $\mu\hbox{A}$ quiescent current.

An Ultralow-Power Low-Voltage Class-AB Fully Differential OpAmp for Long-Life Autonomous Portable Equipment

This brief presents an ultralow-power class-AB operational amplifier (OpAmp) designed in a low-cost 0.18- μm CMOS technology. The proposed circuit uses transistors biased in the subthreshold region for low-voltage low-power operation. For a 0.8-V single supply, this OpAmp has 51-dB open-loop gain, 57-kHz unity-gain frequency, 60° phase margin, and 65-dB common-mode rejection ratio for 8-pF loads with a power consumption of only 1.2 μW. Experimental results illustrate performances such as a 0.14-V/μs slew rate and a 750-mV linear output swing, demonstrating its correct functionality.

Low Power, High Dynamic Range Analogue Multiplexer for Multi-Channel Parallel Recording of Neuronal Signals Using Multi-Electrode Arrays

Low Power, High Dynamic Range Analogue Multiplexer for Multi-Channel Parallel Recording of Neuronal Signals Using Multi-Electrode ArraysIn the paper we present the design and test results of an integrated circuit combining a sample&hold circuit and an analogue multiplexer. The circuit has been designed as a building block for a multi-channel Application Specific Integrated Circuit (ASIC) for recording signals from alive neuronal tissue using high-density micro-electrode arrays (MEAs). The design is optimised with respect to critical requirements for such applications, i.e. short sampling time, low power dissipation, good linearity and high dynamic range. Presented design comprises sample&hold circuits with class AB operational amplifier, novel shift register, which allows minimising cross-coupling of the clock signal and control logic. The circuit has been designed in 0.35μm CMOS process and has been successfully implemented in a prototype multi-channel ASIC.

Low Voltage Differential Input Stage With Improved CMRR and True Rail-to-Rail Common Mode Input Range

A scheme for low voltage rail-to-rail operation with improved common mode rejection ratio is introduced. It can operate with single supply voltages close to a transistor's threshold voltage and it is very compact and power efficient. It is based on a differential amplifier with floating gate input transistors featuring dynamical adjustment of a floating gate biasing voltage. This reduces significantly common mode voltage variations at the input terminals of the differential pair. The implementation of single ended two stage class AB operational amplifiers based on this scheme is discussed. Experimental results of a test chip in 0.5 mum CMOS technology that validates the proposed scheme are presented.

A 1.2-V 140-nW 10-bit Sigma–Delta Modulator for Electroencephalogram Applications

This paper presents a second-order Sigma-Delta modulator for electroencephalogram applications with 10 bits of resolution, 1.2 V of supply voltage, and only 140 nW of power consumption over a bandwidth of 25 Hz. Low-voltage operation has been achieved using quasi-floating-gate-based circuits. The use of a new class-AB operational amplifier in weak inversion allows very low power consumption. Experimental results show an energy efficiency of 1.6 pJ per quantization level, making it the most energy-efficient converter reported to date in the very low signal bandwidth range.

1 V fully balanced differential amplifiers: Implementation and experimental results

We report a novel low voltage fully differential class AB operational amplifier and a fully balanced preamplifier, which are based on Dynamic Threshold voltage MOSFET (DTMOS) transistors. Pseudo P type DTMOS transistors are used to enhance the differential input common-mode range. The proposed circuits were fabricated using standard CMOS 0.18 μm CMOS process technology. The fully differential class AB amplifier is implemented to enhance the noise performance of low voltage high precision switched capacitor circuits, the fully balanced preamplifier is implemented to drive the differential inputs of the analog to digital converter used in the analog front-end of a near-infrared spectroreflectometry (NIRS) receiver of a multi-wavelength wireless brain oxymeter apparatus. The power consumption of the proposed preamplifier is only 80 μW. The minimum experimental supply voltage is roughly 0.8 V.

1-V DTMOS-Based Class-AB Operational Amplifier: Implementation and Experimental Results

In this paper, we describe a novel low-voltage class-AB operational amplifier (opamp) based on dynamic threshold voltage MOS transistors (DTMOS). A DTMOS transistor is a device whose gate is tied to its bulk. DTMOS transistor pseudo-pMOS differential input pairs are used for input common-mode range enhancement, followed by a single ended class-AB output. Two versions of the proposed opamp (opamp-A and opamp-B) were fabricated in a standard 0.18-mum CMOS process technology. Measurements under 5 pF and 10 kOmega load conditions gave, for opamp-A, a DC open-loop gain of 50.1 dB, and a unity gain bandwidth (GBW) of 26.2 MHz. A common-mode rejection ratio (CMRR) of 78 dB, and input and output swings of 0.7 V and 0.9 V, respectively, were achieved. Opamp-B has been optimized for biomedical applications, and is implemented to build the analog front-end part of a near-infrared spectroreflectometry (NIRS) receiver of a multi-wavelength wireless brain oxymeter apparatus. A DC open-loop gain of 53 dB, a GBW of 1.3 MHz, and input and output swings of 0.6 V and 0.8 V, respectively, were measured. Opamp-A consumes 550 muW with an input referred noise of 160 nV/radicHz at 1 kHz. Opamp-B consumes only 40 muW and exhibits a lower input referred noise of 107 nV/radicHz at 1 kHz

A low voltage, rail-to-rail, class AB CMOS amplifier with high drive and low output impedance characteristics

This paper describes a CMOS rail-to-rail class AB operational amplifier designed to have extremely low output impedance and large current-drive capability. The amplifier uses an innovative output stage, having both source follower and common source stages working simultaneously throughout the output common-mode range. The source follower ensures low output impedance, which enables it to drive relatively large load capacitors, while the common-source gain stage provides high current drive. Furthermore, the circuit is fully functional with supplies as low as 1.5 V. The amplifier is capable of driving a maximum output current of /spl plusmn/7 mA with only 140 /spl mu/A of total quiescent current, making it power efficient, and thus appropriate for low voltage battery-powered applications.

A 1-GHz bipolar class-AB operational amplifier with multipath nested Miller compensation for 76-dB gain

A 1-GHz operational amplifier with a gain of 76 dB while driving a 50-/spl Omega/ load is presented. The equivalent input noise voltage is as low as 1.2 nV//spl radic/Hz. This combination of extremely high bandwidth, high gain, and low noise is the result of a three-stage all-n-p-n topology combined with a multipath nested Miller compensation. Using 10-GHz f/sub T/ n-p-n transistors, the realizable bandwidth could be of the order of 2-3 GHz. However, bond-wire inductances restrict the useful bandwidth to 1 GHz. The amplifier occupies an active area of 0.26 mm/sup 2/ and has been realized in the bipolar part of a 1-/spl mu/m BiCMOS process.

A programmable 1.5 V CMOS class-AB operational amplifier with hybrid nested Miller compensation for 120 dB gain and 6 MHz UGF

The paper presents a rail-to-rail class-AB operational amplifier in a standard v/sub th/=0.6 V CMOS technology operating at 1.5 V. A hybrid nested Miller compensation technique yields 6 MHz unity gain frequency at 300 /spl mu/A supply current, 120 dB gain and programmability. Operation down to 1.0 V at 15 /spl mu/A is possible with 300 kHz UGF. The die area of the chip is 0.05 mm/sup 2/ (70 mil/sup 2/).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An analytical model for the transient response of CMOS class AB operational amplifiers

An analytical study of the transient response of a CMOS class AB opamp operating in a voltage follower configuration is presented. As with class A opamps, we identify nonlinear and linear regions of operation corresponding to slewing and settling periods in the transient response. But in contrast with class A opamps, it is shown that the feedback configuration should be considered for the entire duration of the transient response. It is shown that doublets (pole-zero pairs) have significant impact on the transient response of the class AB opamps in both nonlinear and linear regions of operation. One result is that in order to prevent overshoot in the transient response due to the doublets, the pole of the double should be located at a frequency higher than about four times the unity-gain bandwidth. The proposed analytical model is valid for any location of the doublets. It agrees well with the results of HSPICE computer simulations, and has the advantage over the latter of providing circuit designers with a clear relationship between the design goals and the device parameters.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>