Class AB Operation Research Articles

A 0.6 V Bulk-Driven Class-AB Two-Stage OTA with Non-Tailed Differential Pair

This work presents a two-stage operational transconductance amplifier suitable for sub-1 V operation. This characteristic is achieved thanks to the adoption of a bulk-driven non-tailed differential pair. Local positive feedback is exploited to boost the equivalent transconductance of the first stage and the quasi-floating gate approach enables the class AB operation of the second stage. Implemented in a standard 180 nm CMOS technology and supplied at 0.6 V, the amplifier exhibits a 350 kHz gain bandwidth product and a phase margin of 69° while driving a 150 pF load. Compared to other solutions in the literature, the proposed one exhibits a considerable performance improvement, especially for large signal operation.

Impedance-mode capacitance multiplier with OTA-based flipped voltage follower for high accuracy and large multiplication factor

A capacitance multiplier with large multiplication factor, increased accuracy, and class AB operation is presented. The multiplier is an impedance mode implementation consisting of a Flipped Voltage Follower based on Operational Transconductance Amplifiers (OTA). This gives the possibility to offer rail-to-rail operation and class AB operation to drive demanding loads depending on the application. In addition, one of the OTAs is designed to offer a transconductance gain based on passive resistors and achieve increased accuracy in the multiplication factor by means of proper layout techniques. The circuit was implemented in a 0.5µm technology and has multiplication factors of 10, 100, 1k and 10k, a power dissipation of 0.56mW and a silicon area of 0.059mm2. Simulation and experimental results of the multiplier demonstrate the proper operation.

Optimization of linearity at high electrical field for dual threshold coupling AlGaN/GaN HEMT applied in Ka-band applications

In this work, a high linearity AlGaN/GaN HEMT integrated dual threshold coupling (DT) technology and Schottky–Ohmic drain (SOD) were fabricated and analyzed. Since the architecture of DT synthesized planar- and recess-HEMT periodically along the gate width, SOD alleviated the peak electric field (E-field) around the gate region and the peak transconductance (Gm-max) of 248 mS/mm with the associated transconductance plateau of ∼4.0 V at Vds = 28 V was obtained, which is evidently flatter than that of HEMT without the SOD structure. Attributed to the improved Gm linearity at high E-field, the DT-SOD HEMT exhibits the predicted linearity figure of merit of 5–13 dB when biased at class AB operation, which is ∼10 dB higher than that of DT-HEMT. Moreover, the fabricated device yields a nearly constant fT/fmax of 47/118 GHz over a wide gate voltage, and load-pull measurements at 30 GHz reveal that these devices deliver output power density (Pout) of 7.8 W/mm with the associated 1-dB compression point (P1dB) of 28.5 dBm at Vds = 28 V. The experimental results indicate that the employment of DT technology and SOD structure is an attractive approach to enhance the linearity at high E-field for millimeter wave devices.

0.4-V Tail-Less Quasi-Two-Stage OTA Using a Novel Self-Biasing Transconductance Cell

This work presents a tail-less fully differential bulk-driven transconductance amplifier without using a common-mode feedback (CMFB) circuit. The proposed amplifier employs two P-type and N-type current mirrors to form two self-biasing positive feedback loops resulting in a double transconductance. The bulk terminals of the P-type current mirrors are used as the input nodes to provide a high input dynamic range. The diode-connected topologies of the current mirrors adaptively bias other transistors to cover the lack of the CMFB circuit. To ensure stability, additional current sources are paralleled with the positive feedback structures. A high output voltage swing and a high DC gain are achieved by adding an adaptively biased common-source amplifier as the output stage leading to a class-AB operation. A large signal analysis, in weak inversion, is also done to mathematically describe both small- and large-signal characteristics. The proposed circuit was fabricated using TSMC <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18 \mu \text{m}$ </tex-math></inline-formula> CMOS technology occupying a silicon area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$113\,\,\mu \text{m}\,\,\times 70\,\,\mu \text{m}$ </tex-math></inline-formula> . Experimental results at a supply voltage of 0.4 V show a gain bandwidth of 7 kHz, a DC gain of 60 dB, and a slew rate of 79 V/ms with just 24 nW power dissipation while driving a capacitive load of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 15$ </tex-math></inline-formula> pF.

±0.3V Bulk-Driven Fully Differential Buffer with High Figures of Merit

A high performance bulk-driven rail-to-rail fully differential buffer operating from ±0.3V supplies in 180 nm CMOS technology is reported. It has a differential–difference input stage and common mode feedback circuits implemented with no-tail, high CMRR bulk-driven pseudo-differential cells. It operates in subthreshold, has infinite input impedance, low output impedance (1.4 kΩ), 86.77 dB DC open-loop gain, 172.91 kHz bandwidth and 0.684 μW static power dissipation with a 50-pF load capacitance. The buffer has power efficient class AB operation, a small signal figure of merit FOMSS = 12.69 MHzpFμW−1, a large signal figure of merit FOMLS = 34.89 (V/μs) pFμW−1, CMRR = 102 dB, PSRR+ = 109 dB, PSRR− = 100 dB, 1.1 μV/√Hz input noise spectral density, 0.3 mVrms input noise and 3.5 mV input DC offset voltage.

Fully Differential Miller Op-Amp with Enhanced Large- and Small-Signal Figures of Merit

A highly power-efficient, fully differential Miller op-amp with accurately controlled output quiescent current is introduced. The op-amp can drive both capacitive and resistive load due to the presence of the auxiliary amplifier. This amplifier helps to achieve class AB operation of the proposed op-amp. The fully differential auxiliary amplifier is compact and uses a resistive local common-mode feedback network. It consumes only 6% of the total current of the op-amp. The proposed op-amp has several innovative features. Incorporating the auxiliary amplifier helps to improve the unity gain frequency, power efficiency, slew-rate, and common-mode rejection ratio of the proposed op-amp. It can drive a wide range of resistive (200 Ω–1 MΩ) and capacitive loads (5 pF–300 pF). The op-amp has a large signal dynamic current efficiency of 8.6 and a large signal static current efficiency of 7.9. The small-signal figure of merit is 8.7 for RL = 1 MΩ and 7.3 for RL = 200 Ω.

The Influence of Fe Doping Tail in Unintentionally Doped GaN Layer on DC and RF Performance of AlGaN/GaN HEMTs

In this work, the performance of AlGaN/ gallium nitride (GaN) high-electron mobility transistors (HEMTs) with different Fe doping tails was systematically investigated and compared. It is illustrated that the combination of the unintentionally doped (UID) GaN layer and a thinner Fe doping buffer layer would result in a faster slope rate of Fe concentration in the UID GaN layer. The devices with the fastest slope rate of Fe concentration in the UID GaN layer exhibited excellent large signal performance, including the saturated power density ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{sat}$ </tex-math></inline-formula> ) of 9 W/mm and the power-added efficiency (PAE) of 65.6%. In addition, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{sat}$ </tex-math></inline-formula> and the PAE of the device with the fastest slope rate of Fe concentration in UID GaN layer are 27.7% and 14.7%, which are higher than that of the device with the slowest slope rate of Fe concentration under the class AB operation conditions. Pulse <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula> ,– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> measurement results demonstrated that the buffer-related current collapse was more effectively suppressed in the 0.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> Fe doping buffer layer because of faster slope rate of Fe concentration in UID GaN layer. Moreover, the frequency-dependent capacitance and conductance measurement results indicated that the current collapse was relevant to deep traps in the UID GaN layer introduced by Fe doping. By reducing the concentration of the deep traps caused by Fe doping, the device showed excellent characteristics of dc and RF. Furthermore, controlling the Fe doping tail was important for designing the GaN-based power amplifier with high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{sat}$ </tex-math></inline-formula> and PAE.

0.5 V CMOS Inverter-Based Transconductance Amplifier with Quiescent Current Control

A two-stage CMOS transconductance amplifier based on the inverter topology, suitable for very low supply voltages and exhibiting rail-to-rail output capability is presented. The solution consists of the cascade of a noninverting and an inverting stage, both characterized by having only two complementary transistors between the supply rails. The amplifier provides class-AB operation with quiescent current control obtained through an auxiliary loop that utilizes the MOSFETs body terminals. Simulation results, referring to a commercial 28 nm bulk technology, show that the quiescent current of the amplifier can be controlled quite effectively, even adopting a supply voltage as low as 0.5 V. The designed solution consumes around 500 nA of quiescent current in typical conditions and provides a DC gain of around 51 dB, with a unity gain frequency of 1 MHz and phase margin of 70 degrees, for a parallel load of 1 pF and 1.5 MΩ. Settling time at 1% is 6.6 μs, and white noise is 125 nV/Hz.

High Output Power Density of 2DHG Diamond MOSFETs With Thick ALD-Al2O3

This article reports on the high operation voltage large-signal performance of two-dimensional hole gas diamond metal-oxide semiconductor field-effect transistors (MOSFETs) with thick atomic-layer-deposition (ALD)-Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> formed on high purity polycrystalline diamond with a (110) preferential orientation. MOSFETs with a 1- μm gate-length having a gate oxide layer of 200-nm-thick Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , formed by ALD and asymmetric structures, to withstand high-voltage operations. The large-signal performances were evaluated at a quiescent drain voltage of greater than -60 V for the first time in diamond field-effect transistor (FET). As a result, an output power density of 2.5 W/mm under class-A operation at 1 GHz, which is higher than that of diamond FETs fabricated by a self-aligned gate process, was obtained. Moreover, an output power density of 1.5 W/mm was exhibited by the MOSFET when biased at a quiescent drain voltage of -40 V under class-AB operation at 3.6 GHz using an active load-pull system. This is the highest recorded value for diamond FETs at a frequency greater than 2 GHz, owing to the high-voltage operation. These results indicate that diamond p-FETs under high-voltage operations are the most suitable for high-power amplifiers with complementary circuits.

A very low output resistance and wide-swing class-AB level-shifted folded flipped voltage follower cell

The paper presents a class-AB flipped voltage follower (FVF) cell. In contrast to previous works in the literature, FVF cell, level shifter and folded FVF cell are merged in the proposed FVF cell to offer class-AB operation along with wide input/output voltage swing and low output resistance. In the proposed FVF cell, the level shifter increases the input/output voltage swing while the folding transistor provides an alternate path for sourcing current, which results in low output resistance. The proposed FVF cell offers wide input/output voltage swing of 0.80 V/0.67 V, high gain of 0.84, wide bandwidth of 54 MHz for the worst case load capacitance of 50 pF and low output resistance of 10 Ω. The proposed FVF cell is simulated using Cadence Virtuoso Analog Design Environment in 180 nm CMOS technology. The physical layout has been designed using Cadence Virtuoso Layout XL editor and post-layout simulation results are presented to demonstrate the performance of the proposed FVF cell. The corner analysis has also been performed to show the robustness of the proposed FVF cell.

A DTMOS-based power efficient recycling folded cascode operational transconductance amplifier

The focus of the present study is on a recycling folded cascode (RFC) operational transconductance amplifier (OTA) in which the transconductance, as well as the slew rate of OTA, are enhanced. RFC OTA, proposed in this study, is employed using a Dynamic Threshold Voltage MOSFET (DTMOS) based differential pair with class AB operation. To achieve class AB operation, an adaptive biasing technique comprising a flip voltage follower is used which boosts the dynamic current and gain-bandwidth product of OTA. Conventional current mirrors are replaced with source degenerated non-linear current mirrors to achieve a better slew rate. The conventional and proposed RFC structures are designed and simulated in a standard 180 nm CMOS process at 1 V supply voltage. The proposed RFC OTA demonstrates a significant enhancement in the performance parameter as 11 dB improvement in the gain as well as 290% more GBW and achieves a slew rate that is nine times better compared to the conventional RFC.

Analysis of Low Voltage RF Power Capability on AlGaN/GaN and InAlN/GaN HEMTs for Terminal Applications

In this work, low voltage RF power capability on AlGaN/GaN and InAlN/GaN HEMTs is analyzed from the perspective of DC and pulse characteristics, for terminal applications whose operating voltage is usually in the range of 3 to 15 V. Device fabrication is performed on mature AlGaN/GaN heterojunction as well as strongly polarized InAlN/GaN heterojunction, to make a comparison of low voltage RF power capability between two devices. Although it suffers from relatively severe RF dispersion, InAlN/GaN HEMT delivers higher output power density (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) than its opponent, benefiting from the lower parasitic resistance and knee voltage as well as higher output current density. At 8 GHz, P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> of 1.62 W/mm and 1.10 W/mm are achieved for InAlN/GaN and AlGaN/GaN HEMT, respectively, both of which are biased at class AB operation and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> of 9 V. However, the tremendous degradation of power added efficiency (PAE) occurs as the higher drain voltage is applied on InAlN/GaN HEMT, as the result of the severe gate leakage. What is more, a higher PAE is more necessary than P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> for terminal applications. Either InAlN/GaN HEMT or AlGaN/GaN HEMT has its own specific voltage range to deliver higher PAE. Concretely, InAlN/GaN HEMT is more suitable to applications with operating voltage not exceeding 6 V, and AlGaN/GaN HEMT is preferred for ones with relatively higher voltage, accompanied by the decent PAE as high as 62% to 66% and moderate P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> to meet the demand of various low voltage terminal applications.

A Two-Stage X-Band 20.7-dBm Power Amplifier in 40-nm CMOS Technology

For higher integration density, X-band power amplifiers (PAs) with CMOS technology have been widely discussed in recent publications. However, with reduced power supply voltage and device size, it is a great challenge to design a compact PA with high output power and power-added efficiency (PAE). In the proposed design, a 40-nm standard CMOS process is used for higher integration with other RF building blocks, compared with other CMOS PA designs with larger process node. Transistor cells are designed with neutralization capacitors to increase stability and gain performance of the PA. As a trade-off among gain, output power, and PAE, the transistor cells in driving stage and power stage are biased for class A and class AB operation, respectively. Both transistor cells consist of two transistors working in differential mode. Furthermore, transformer-based matching networks (TMNs) are used to realize a two-stage X-band CMOS PA with compact size. The PA achieves an effective conductivity (EC) of 117.5, which is among the highest in recently reported X-band PAs in CMOS technology. The PA also attains a saturated output power (Psat) of 20.7 dBm, a peak PAE of 22.4%, and a gain of 25.6 dB at the center frequency of 10 GHz under a 1 V supply in 40-nm CMOS.

A wide swing, high drive current output stage

ABSTRACT In this paper, a novel current output stage (COS) is introduced. Deliberately compose of class AB operation and a special voltage sense and current compensation scheme enables the structure to operate at extreme voltage beyond the triode limits to achieve wide voltage dynamic range and grants it such following ever demanded merits at power supplies of 1.8V: low power consumption of 40 µW, high drive to bias current ratio of 100. The results are verified by Spectre post-layout simulation using 0.18 µm CMOS standard technology of TSMC. The process, the stability and robustness of the proposed COS are verified by stepwise response and Monte Carlo and corner simulations, respectively.

Pseudo-Three-Stage Miller Op-Amp With Enhanced Small-Signal and Large-Signal Performance

A simple technique to implement highly power efficient class AB–AB Miller op-amps is presented in this paper. It uses a composite input stage with resistive local common mode feedback that provides class AB operation to the input stage and essentially enhances the op-amp’s effective transconductance gain, the dc open-loop gain, the gain-bandwidth product, and slew rate with just moderate increase in power dissipation. The experimental results of op-amps in strong inversion and subthreshold fabricated in a 130-nm standard CMOS technology validate the proposed approach. The op-amp has $9~\text {V} \cdot \text {pF}/\mu \text {s}\cdot \mu \text{W}$ large-signal figure of merit (FOM) and $17~\text {MHz}\cdot \text {pF}/\mu \text{W}$ small-signal FOM with 1.2-V supply voltage. In subthreshold, the op-amp has $10~\text {V}\cdot \text {pF}/\mu \text {s}\cdot \mu \text{W}$ large-signal FOM and $92~\text {MHz}\cdot \text {pF}/\mu \text{W}$ small-signal FOM with 0.5-V supply voltage.

84 dB DC‐gain two‐stage class‐AB OTA

Operational trans-conductance amplifiers (OTAs) are an essential building block in analogue and mixed-signal circuits. In this study, a new two-stage class-AB OTA is proposed. The class-AB operation is obtained without extra power dissipation, and without unity-gain bandwidth or noise degradation. The circuit was fabricated using 1P6M 180-nm CMOS technology under 1.8 V supply voltage. The measurement results indicate 13 dB enhancement in DC-gain and 1.8 times improvement in slew rate compared to its conventional counterpart. Comparison results indicate that the proposed OTA demonstrates better performance than the state-of-the-art designs.

A Highly Efficient Composite Class-AB–AB Miller Op-Amp With High Gain and Stable From 15 pF Up To Very Large Capacitive Loads

In this paper, a highly power-efficient class-AB–AB Miller op-amp is discussed. The structure uses $g_{m}$ enhancement based on local common-mode feedback to provide class-AB operation with enhanced effective $g_{m}$ , open-loop gain, unity-gain frequency, and slew rate ( $SR$ ) without significant increase in quiescent power consumption. Utilization of a nonlinear load leads to large symmetric positive and negative $SR\text{s}$ . Stability over an extremely wide range of capacitive loads is achieved through a combination of Miller and phase-lead compensations. The unity-gain frequency does not show sensitivity to capacitive load values. A test chip prototype fabricated in 0.18- $\mu \text{m}$ CMOS technology shows 90.8-dB open-loop gain, 12.5-MHz bandwidth for a 25-pF load capacitance, and a factor $60~SR$ enhancement with maximum output current close to 1-mA and 43- $\mu \text{A}$ total static current.

A 0.6 V class‐AB rail‐to‐rail CMOS OTA exploiting threshold lowering

A class-AB OTA (operational transconductance amplifier) topology with rail-to-rail input common-mode range is proposed for application in very low-voltage applications. High efficiency is achieved by reusing transistors both for class-AB operation and for mirroring the output currents, and a threshold lowering technique is applied to allow supply voltages less than two threshold voltages. Simulations in 40 nm CMOS technology show 41 dB gain at ±0.3 V supply voltage, a unity-gain frequency of 8.8 MHz on a 5 pF load, class-AB behaviour and full rail-to-rail operation when closed in unity-gain buffer configuration.

Power‐efficient class‐AB telescopic cascode opamp

A micropower telescopic cascode opamp is described. It employs an adaptive bias current source to obtain class-AB operation and dynamic biasing of the cascode transistors to improve output swing and common-mode rejection ratio (CMRR), and to avoid slew rate degradation. Measurement results for a 0.5 μm CMOS test chip prototype validate the proposal.

Enhanced Single-Stage Folded Cascode OTA Suitable for Large Capacitive Loads

An enhanced single-stage folded cascode operational transconductance amplifier able to drive large capacitive loads is presented. Circuits that adaptively bias the input differential pair and the current folding stage are employed, which provide class AB operation with dynamic current boosting and increased gain-bandwidth (GBW) product. Measurement results of a test chip prototype fabricated in a 0.5- $\mu$ m CMOS process show an increase in slew rate and GBW by a factor of 30 and 15, respectively, versus the class A version using the same supply voltage and bias currents. Overhead in other performance metrics is small.