Class-1 Generation-2 Protocol Research Articles

Efficient Tag Grouping RFID Anti-Collision Algorithm for Internet of Things Applications Based on Improved K-Means Clustering

Dynamic Frame Slotted ALOHA (DFSA) is a de facto algorithm in the EPC Global Class-1 Generation-2 protocol for Radio Frequency Identification (RFID) tag collision problem. DFSA fails when the UHF RFID tag deployment becomes dense like in Internet of Things (IoT). Existing works do not provide readers prior tag estimates. Most algorithms assume a collision slot means two tag collision. But in dense IoT applications, much more than two tags can constitute a collision slot. Moreover, research proves collision slot might occur due to other reasons such as error-prone channel. This paper proposes a RFID anti-collision algorithm, kg-DFSA that equips the reader with prior information on accurate tag estimate. In kg-DFSA, tag identification is divided into two stages – initialization and identification. In the initialization stage, the reader uses improved K-means clustering running concurrently with a tag counter algorithm to cluster tags into K groups using tags’ RN16 while the counter returns an accurate tag number estimate. In the identification stage, the tags are read only in frame chunks that match their group IDs while a new frame size look up table is developed to boost efficiency. Variants of the proposed kg-DFSA, traditional DFSA and another grouping based DFSA algorithm (FCM-DFSA) were implemented in MATLAB. Extensive Monte Carlo simulation shows the proposed kg-DFSA edges DFSA in terms of success rate 50%, system efficiency 65% and identification time 28%. The proposed model is useful in enhancing the existing MAC protocol to support dense IoT deployment of RFID.

Design and Implementation of a Low-Cost Universal RFID Wireless Logistics Terminal in the Process of Logistics Traceability

The logistics traceability system can cover the whole process of the product from the source of production to the consumption cycle. By distinguishing the key nodes of the product in the logistics sales process, the data information of the production and storage of the corresponding product is collected and entered at the corresponding node, so that the entire process is visible and controllable. On the basis of determining the overall system plan, this paper designs and develops the UHF RFID reader system and traceability system platform. In terms of the reader system, by analyzing its core functions and performance index requirements, the overall design scheme and frame structure of the reader system’s software and hardware are determined. The main control circuit is based on the STM32F103RET6 single-chip microcomputer; the RF transceiver circuit is based on the MagicRF M100. Simultaneously, we design a variety of communication circuits including LoRa and RJ45 to facilitate wireless communication with the traceability platform. In terms of software, through the research and analysis of the EPC Class-1 Generation-2 protocol standard, the multitag anticollision algorithm—Q algorithm—is adopted. This algorithm has the advantages of high recognition efficiency and a large number of successfully recognized tags per unit time. According to the design plan, the system is wirelessly networked in the B/S mode and the product information collected through RFID technology is transmitted to the management level to dynamically understand the information dynamics of logistics in real time. Using radio frequency, computer network, communication, and other technologies, the hardware and software systems of the system are integrated. The performance indicators of the hardware system are tested through experiments, and the design indicators are compared to prove the feasibility of the equipment application. After setting up the local area network and configuring the server configuration, the traceability system was accessed and the verification of the basic functions of the system was completed. The test results show that the low-cost universal RFID wireless logistics terminal has high accuracy and real-time performance in the process of logistics traceability.

Close-Proximity Detection for Hand Approaching Using Backscatter Communication

Smart environments and security systems require automatic detection of human behaviors including approaching to or departing from an object. Existing human motion detection systems usually require human beings to carry special devices, which limits their applications. In this paper, we present a system called APID to detect hand approaching behaviors by analyzing backscatter communication signals from a passive RFID tag on the object. APID does not require human beings to carry any device. The idea is based on the influence of hand movements to the vibration of backscattered tag signals. APID is compatible with commodity off-the-shelf devices and the EPCglobal Class-1 Generation-2 protocol. In APID, a commercial RFID reader continuously queries tags through emitting RF signals and tags simply respond with their IDs. A USRP monitor passively analyzes the communication signals and reports the approach and departure behaviors. We have implemented the APID system for both single-object and multi-object scenarios. Extensive evaluations demonstrate that APID can achieve high detection accuracy in both scenarios.

NQA

Radio frequency identification (RFID) systems, as one of the key components in the Internet of Things (IoT), have attracted much attention in the domains of industry and academia. In practice, the performance of RFID systems rather relies on the effectiveness and efficiency of anti-collision algorithms. A large body of studies have recently focused on the anti-collision algorithms, such as the Q-algorithm ( QA ), which has been successfully utilized in EPCglobal Class-1 Generation-2 protocol. However, the performance of those anti-collision algorithms needs to be further improved. Observe that fully exploiting the pre-processing time can improve the efficiency of the QA algorithm. With an objective of improving the performance for anti-collision, we propose a Nested Q-algorithm ( NQA ), which makes full use of such pre-processing time and incorporates the advantages of both Binary Tree ( BT ) algorithm and QA algorithm. Specifically, based on the expected number of collision tags, the NQA algorithm can adaptively select either BT or QA to identify collision tags. Extensive simulation results validate the efficiency and effectiveness of our proposed NQA (i.e., less running time for processing the same number of active tags) when compared to the existing algorithms.

LILAC: computable capabilities based high performance protocol for CRFID

Compared with traditional radio frequency identification (RFID), computational RFID (CRFID) tag has more powerful computing capability, but it shows poor performance when it follows EPC Class-1 Generation-2 protocol especially transmitting large amounts of data. In fact, the operation of the CRFID tag entirely depends on the state of energy. For this point, this study proposes an optimised protocol called LILAC. LILAC allows tags to select the communication time slot according to their current voltage value measured by using an analogue-to-digital converter rather than randomly selecting, the authors proposed a more reasonable time slot mapping algorithm for LILAC that increases the success rate of tag responding. In addition, they design a data transmission format that can be retransmitted to improve the uplink throughput. Finally, they implemented LILAC on a CRFID platform and practically measured several parameters to compare with the existing well-known protocol. The results of experiments show that LILAC increases the maximum communication distance by more than half in the access phase and doubles the goodput of the backscatter link in both the inventory and access phase.

A Fast Anticollision Algorithm for the EPCglobal UHF Class-1 Generation-2 RFID Standard

In this letter, a fast anticollision algorithm has been proposed to improve the read performance of the EPCglobal UHF Class-1 Generation-2 protocol. Our algorithm is based on the early adjustment of frame length. To reduce the computation complexity of interrogators, the proposed algorithm resorts to only one examination of current frame length in each read round. As compared with the case of examining at every time slot, the proposed method can dramatically reduce the number of examinations from about 1425 to 14. The normalized throughput of our method can reach a value of up to 35%, which is very close to the theoretical maximum of 36% for the EPCglobal UHF Class-1 Generation-2 anticollision scheme.

A Improved EPC Class 1 Gen 2 Protocol with FCFS Feature in the Mobile RFID Systems

In all anti-collision protocols of RFID standards, EPCGlobal Class 1 Generation 2 (C1G2) protocol has been most widely used in RFID systems since it is simply, efficient and safety. Similar to most existing anti-collision protocols, The C1G2 protocol initially aims at tag identification of static scenarios, where all tags keep still during the tag identification process. However, in many real scenarios, tags generally move along a fixed path in the reader coverage area, which implies that tags stay the coverage area only for a limited time (sojourn time). The scenarios are usually called mobile RFID systems. Because the multiple tag identification based on a shared wireless channel is random, tags entering the reader coverage area earlier may be identified later (random later identification phenomenon). The phenomenon and the limited sojourn time may let some tags lost. In this paper, we propose an improved C1G2 protocol with first come first served feature in mobile RFID systems. The protocol can overcome the RLI phenomenon effectively and retains good initial qualities of C1G2 protocol by modifying it slightly. Simulation results show that the proposed protocol can significantly reduce the numbers of lost tags in mobile RFID systems. The idea of the paper is beneficial for redesigning other existing tag anti-collision protocols so as to make these protocols adapt to mobile RFID systems.

Robust digital receiver for EPC sensor network

A robust digital receiver based on a matched filter (MF) is proposed for the radio frequency identification (RFID) reader system to enhance the reliability of signal processing in the electronic product code (EPC) sensor network (ESN). The performance of the proposed receiver is investigated by examining the anti-collision algorithm in the EPC global Class1 Generation2 protocol. The validity and usefulness are demonstrated by both computer simulations and experiments. Based on the verification results, comparing with the conventional zero crossing detector (ZCD) based receiver, the proposed receiver is very robust against strong amplitude distortions and considerable frequency deviations happening on the backscattered signal from a passive tag.

Design of a semi-passive UHF RFID tag IC with freight security monitoring function

A semi-passive ultra-high-frequency-band radio frequency identification tag IC with freight security monitoring function is proposed. The tag can record the number of times a container has been opened during transport and is compatible with Electronic Product Code Class-1 Generation-2 protocol. A switch-state monitoring unit is presented with power control logic that makes the tag return to sleep mode after each recording operation. An optimized differential rectifier is designed after the analysis and comparison of the different rectifier architectures. The rectifier is designed along with a voltage regulator and a wake-up circuit to comprise a power management unit for generating two output voltages of 1 and 1.8 V at 915 MHz. A baseband processor with a jitter suppression module is employed to improve system reliability. The tag chip is designed in TSMC 0.18m CMOS process and simulated with Spectre. According to the simulation results, the power consumption of the tag is 9.56W under activation mode, and the sleep current is only 645 pA under the typical condition.

An Ultralow-Power Mixed-Signal Back End for Passive Sensor UHF RFID Transponders

This paper describes the design of mixed-signal back end for an ultrahigh-frequency sensor-enabled radio-frequency identification transponder in full compliance with the Electronic Product Code Class-1 Generation-2 protocol, defined in the standard ISO 18000-6C. The chip, implemented in a low-cost 0.35- μm CMOS technology process, includes a baseband processor, an analog-to-digital converter (ADC) to digitize the signal acquired from the external sensor, and some auxiliary circuitry for voltage regulation and reference generation. The proposed solution uses two different supply voltages, one for the processor and the other for the mixed-signal circuitry, and defines a novel communication protocol between both blocks so that analog readouts are minimally affected by the digital activity of the tag. The whole system was first functionally validated by exhaustively testing with external dc power supplies ten prototype samples, and then, the two main blocks, processor, and ADC were individually tested to assess their performance limits. Regarding the baseband processor, experiments were performed toward the calculation of its packet error rate (PER) under two typical biasing configurations of passive tags, using either crude clamps or regulators. It was found that the regulated biasing outperforms the clamping solution and obtains a PER of 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> with a supply voltage of 0.75 V. The current consumption of the processor during the reception and response to a Read command at maximum backward rate is only 2.2 μA from a 0.9-V supply. Regarding the ADC, it is a 10-b successive approximation register converter which obtains 9.41 b of effective resolution at 2-kS/s sampling frequency with a power consumption of 250 nW, including the dissipation of a current generation cell and the clock generation circuitry, from 1-V supply.

Ultra High-Speed and Low-Power Flexible Architecture using State Transition Matrix Model for EPC Gen-2 Communication Protocol Processor

In modern electronics, communication between systems is progressing towards wireless technology [1]. The rapid adaptation of the Wi-Fi technology across the world is a good example of the trends to come [2]. The IEEE 802.11 protocol [3], with its different layers of communication (information transfer), is obviously not ideal for applications that are time and energy sensitive. The EPCglobal Class-1 Generation-2 Protocol [4] (adapted by the International Organization for standards as the ISO 18000-6 [5]) is an impressive alternative that is slowly gaining global recognition as not just an RFID protocol, as it was primarily intended for, but as a front-end (communication link) for several identification and sensor applications [6]. This paper reports the design of a low-power processor specific for the Gen-2 instruction set with high emphasis on speed optimization at low power consumption. A novel approach in processor design as an asynchronous state machine is introduced, making the architecture extremely flexible and adaptable to changes in the protocol. Given that the full Gen-2 state transition matrix is available with direct linkage to the published standard, changes in the protocol can be directly effected through this matrix. Thus, the generation or the original and updated VLSI chips with the design flow disclosed is simply a matter of using the original or updated matrix. The design of the processor from a hardware description language (VHDL) level makes the final implementation possible either as an ASIC or on a suitable FPGA. The ASIC design flow is considered in this paper reporting the three fundamental characteristics—speed, power and area, of the post layout design. Industry standard Mentor Graphics ModelSim SE, Synopsys Design Compiler and Cadence Encounter are used in this research.