Circular Transfer Length Method Research Articles

The study on influence factors of contact properties of metal-MoS2 interfaces

The metal and two-dimension (2D) semiconductor contact interfaces have a more considerable contact resistance hindering carrier injection, which makes the performance of 2D semiconductor devices less than the theory. The contact properties of Ni, Au, and Mo with MoS2 are simulated by the first-principles method. The interface dipole caused by the interface charge redistribution changes the work function difference at the metal-MoS2 interface, so the interface charge redistribution is one of the important factors for correctly evaluating the contact properties. Due to the metal-induced gap states (MIGS) at metal-monolayer (ML) MoS2 interfaces, the Fermi level is strongly pinned to fixed energy, and the Schottky barrier height (SBH) cannot be regulated efficiently by the metal work function. Although the work function of Au is bigger than Ni, the Fermi level of Au is pinned at a higher position. In the meantime, the bandgap of MoS2 narrows and metallization occurs due to the larger MIGS. In the Mo-MoS2 interface, the Fermi level is pinned near the conduction band minimum of MoS2. The contact resistances (Rc) of the three structures are tested by the Circular Transfer Length Method (CTLM), which is consistent with the prediction of the simulation. The Mo-MoS2 has the smallest Rc. The results indicate that contact resistance of 2D semiconductors cannot be simply predicted by soled work functions or Fermi level pinning, but is determined by several factors.

Effect of Dry Etching to Improve Ohmic Contacts on Bulk, Lightly-Doped β-Ga2O3

Ti/Au is a typical Ohmic metal contact stack to n-type β-Ga2O3 but there have been few systematic studies of the use of pre-exposure of the surface to plasmas prior to metal deposition in order to lower the contact resistance. The effects of Cl2/Ar Inductively Coupled Plasma exposure of Ga2O3 surfaces prior to deposition of Ti/Au (20/80 nm) contacts were examined through circular transfer length method (CTLM) measurements to determine both the contact resistance and specific contact resistivity. ICP source power, which controls ion density in the plasma is found to be more important than ion energy (∼165–490 eV in these experiments). The plasma exposure improved specific contact resistivity by more than a factor of 2 in all cases for lightly n-type (1017 cm−3) Ga2O3 and a minimum value of 2 × 10−4 Ω.cm2 was obtained after heating at 550 °C.

Pseudo‐Vertical Schottky Diode with Ruthenium Contacts on (113) Boron‐Doped Homoepitaxial Diamond Layers

Electrical properties of pseudo‐vertical Schottky barrier diodes (pVSBDs) prepared on (113)–oriented boron‐doped diamond (BDD) layers using ruthenium (Ru) for both the ohmic and Schottky contacts are investigated. First, Ru ohmic contacts are evaporated on homoepitaxial BDD layers with different resistivity, and their specific contact resistance is measured using circular transfer length method structures after annealing at various temperatures up to 750 °C. Then, pVSBD structures are fabricated on the boron‐doped bilayer consisting of a lower, heavily boron‐doped layer ensuring an ohmic contact and an upper, lightly doped layer providing a rectifying Schottky contact. After necessary mesa etching, both contacts are formed by the Ru evaporation. The results show that Ru forms a stable ohmic contact with very low contact resistance (10−5–10−6 Ω cm2) when deposited on BDD layers with metallic conductivity. It also provides an acceptable Schottky contact on low‐doped (113) homoepitaxial BDD. Both contacts, which are made simultaneously, realize pVSBDs with low on‐state resistance and low forward voltage drop. However, the lower barrier of the ruthenium contacts results in higher leakage. Ru pVSBDs thus show a lower rectification ratio, higher leakage, and a worse ideality factor compared to analogical pVSBDs using molybdenum contacts.

Scrutinizing pre- and post-device fabrication properties of atomic layer deposition WS2 thin films

In this work, we investigate the physical and electrical properties of WS2 thin films grown by a plasma-enhanced atomic layer deposition process, both before and after device fabrication. The WS2 films were deposited on thermally oxidized silicon substrates using the W(NMe2)2(NtBu)2 precursor and a H2S plasma at 450 °C. The WS2 films were approximately 8 nm thick, measured from high-resolution cross-sectional transmission electron imaging, and generally exhibited the desired horizontal basal-plane orientation of the WS2 layers to the SiO2 surface. Hall analysis revealed a p-type behavior with a carrier concentration of 1.31 × 1017 cm−3. Temperature-dependent electrical analysis of circular transfer length method test structures, with Ni/Au contacts, yielded the activation energy (Ea) of both the specific contact resistivity and the WS2 resistivity as 100 and 91 meV, respectively. The similarity of these two values indicates that the characteristics of both are dominated by the temperature dependence of the WS2 hole concentration. Change in the material, such as in sheet resistance, due to device fabrication is attributed to the chemicals and thermal treatments associated with resist spinning and baking, ambient and UV exposure, metal deposition, and metal lift off for contact pad formation.

Temperature-Dependent Sheet and Contact Resistivity Measurements on Ag and Ag-Ni Circuit Pastes

Here, a van der Pauw method was used to compare the 25-450oC sheet resistivity of Ag-Ni electrical contacts to those made from commercially-available Heraeus C8710 and DAD-87 silver circuit pastes. In addition, a circular transfer length method was used to compare the 25-600oC contact resistivity of Ag-Ni, Heraeus C8710, and DAD-87 on lanthanum strontium manganate (LSM). After 10 hours at 750oC in air, the Ag-Ni sheet resistivity was nearly double that of the commercial Ag pastes. However, after 10 hours at 750oC in air, the Ag-Ni to LSM contact resistivity was between that of Heraeus C8710 and DAD-87. The low Ag-Ni sheet resistivity of ~10-6 ohm-cm, the low Ag-Ni to LSM contact resistivity of ~10-4 ohm-cm2, and the previously-observed >10 times higher adhesion strength of Ag-Ni (compared to Heraeus C8710 or DAD-87) on ceramic substrates, suggests that Ag-Ni may be useful for a variety of high-temperature electronic circuit/current collector applications.

Study of contact resistance of α-Ga2O3 on m-plane sapphire substrate with respect to Sn concentration using the circular transfer length method

In this study, the Sn concentration dependence of the sheet and contact resistances of the m-plane α-Ga2O3 were analyzed and the corresponding current mechanism was determined. The measurements were performed using samples by systematically varying the Sn concentration from 1 × 1017 to 1 × 1019 cm–3. The circular transfer length method pattern was then fabricated, and the sheet and contact resistances were calculated. The Sn concentration dependence was determined for both the sheet and contact resistances. The thermionic field emission model was applied as a current mechanism for the contact resistance, and its results were compared with the values calculated using the Schottky barrier as a parameter. The effect of light illumination on the contact resistance was also analyzed.

Differences in electrical responses and recovery of GaN p+n diodes on sapphire and freestanding GaN subjected to high dose 60Co gamma-ray irradiation

We investigate the effects of high-rate and high total doses of 60Co gamma rays on the current–voltage (IV) characteristics of GaN p+n diodes grown by metal-organic chemical vapor phase epitaxy on Ga-face (0001) sapphire and hydride vapor phase epitaxy freestanding GaN substrates. We show that diodes grown on sapphire undergo more permanent changes upon irradiation at doses up to 3900 kGy than those grown on freestanding GaN. By combining diode and circular transfer length method measurements, we show that the p-type contact interface and adjacent p++ Mg-doped layer are sensitive to irradiation. In initial experiments, diodes grown on sapphire exhibited p-type contacts with Schottky characteristics, while those on freestanding GaN were Ohmic. Serendipitously, we identified and subsequently irradiated a freestanding sample with a pre-irradiation spatial gradient of p-contact Schottky vs Ohmic behavior across the die. This sample allowed the root cause of induced change to be identified as differences in the p++ contacting layer. We show that the p-type contact's pre-irradiation Schottky behavior is predictive of diodes' IV characteristics changing significantly upon gamma-ray irradiation. Further, we observe that the IV curves of diodes on freestanding GaN recover fully over several weeks at room temperature to be indistinguishable from pre-irradiation. IV curves from diodes on sapphire do not fully recover; we thus hypothesize that interactions between radiation-induced point defects and threading dislocations affect the evolution of radiation damage.

Improvement of ZnO/Si Heterojunctions With a Coaxial Circular Transmission Line Model Applicable to Both Ohmic and Schottky

Investigating heterointerfaces with test structures is crucial for fabricating electronic and photonic devices. Recently, we proposed and developed a PbS colloidal quantum dot/ZnO/Si hybrid infrared detector for infrared-sensitive optoelectronic devices on silicon-based large-scale integrated circuits. The conventional circular transfer length method (CTLM) is commonly used for evaluating Ohmic contact. To apply the CTLM to a heterointerface junction, we propose a coaxial CTLM (CCTLM) that includes a circular electrode in the middle and doughnut-shaped outer contact electrodes. The proposed test structure can be identified and quantitatively analyzed for the junction type (Ohmic or Schottky) by changing the electrode area. By using the CCTLM test structure for n-type ZnO/n-type Si heterojunctions and X-ray photoemission spectroscopy measurements, we identified the heterojunction as the Schottky type via the CCTLM and estimated the band diagram of the heterojunction.

Impact of high-dose gamma-ray irradiation on electrical characteristics of N-polar and Ga-polar GaN p–n diodes

We investigate the impact of high-dose gamma-ray irradiation on the electrical performance of Ga-polar and N-polar GaN-based p–n diodes grown by metalorganic chemical vapor deposition. We compare the current density–voltage (J–V), capacitance–voltage (C–V), and circular transfer length method characteristics of the p–n diodes fabricated on Ga-polar and N-polar orientations before and after irradiation. The relative turn-on voltage increases for the Ga-polar diodes with an increasing irradiation dose, while it increases initially and then starts to decrease for the N-polar diodes. The p-contact total resistance increases for Ga-polar and decreases for N-polar samples, which we attribute to the formation of point defects and additional Mg activation after irradiation. The J–V characteristics of most of the tested diodes recovered over time, suggesting the changes in the J–V characteristics are temporary and potentially due to metastable occupancy of traps after irradiation. X-ray photoelectron spectroscopy and photoluminescence measurements reveal the existence of different types of initial defects and surface electronic states on Ga-polar and N-polar samples. Gallium vacancies (VGa) are dominant defects in Ga-polar samples, while nitrogen vacancies (VN) are dominant in N-polar samples. The presence of a higher concentration of surface states on Ga-polar surfaces than N-polar surfaces was confirmed by calculating the band bending and the corresponding screening effect due to opposite polarization bound charge and ionized acceptors at the surface. The difference in surface stoichiometry in these two orientations is responsible for the different behavior in electrical characteristics after gamma-ray interactions.

Wafer-scale mono-crystalline GeSn alloy on Ge by sputtering and solid phase epitaxy

Germanium-tin (GeSn) alloys are of great interest for electronic as well as photonic applications, and their integration on a group-IV (Si or Ge) platform. This letter describes a low deposition temperature, process integration-friendly, high throughput and low cost approach for growing device-quality GeSn epilayers on Ge substrates. Mono-crystalline, wafer-scale GeSn alloy with 3.4% Sn content was grown on Ge (100) substrates by sputtering an amorphous GeSn layer followed by solid phase epitaxy (SPE) at . Deposition of amorphous layers at room temperature enables incorporation of high bulk Sn content in GeSn epilayers. SPE of the amorphous layer at leads to a strained, high quality GeSn epilayer having a low full width half maximum of , root mean square surface roughness of 0.3 nm and a good GeSn/Ge interface as confirmed through extensive x-ray diffraction measurements, atomic force microscopy and transmission electron microscopy imaging. Additionally, an SiO2 capping layer employed during SPE is shown to prevent Sn out-diffusion and segregation at the surface. To examine electrical properties for potential applications of the GeSn/n-Ge heterostructure, metal/GeSn/n-Ge vertical contact diodes and metal/GeSn circular transfer length method contact structures were fabricated and electrically characterized.

Improvement of Ti/Al ohmic contacts on N-face n-type GaN by using O2 plasma treatment

The effect of O2 plasma treatment on the electrical properties of Ti/Al (20/200 nm) contact to N (Nitrogen)-face n-GaN of vertical light-emitting diodes (VLEDs) has been investigated by varying the O2 plasma treatment power and time. Both photolithography and chemical lift-off methods are used to prepare the circular transfer length method (CTLM) patterns on the N-face n-GaN for measuring the contact and sheet resistances. Both total and sheet resistances are decreased with the increase in plasma treatment power up to 250 W. It is found that the Ti/Al-based Schottky contact layer transforms to ohmic characteristics after plasma treatment. GaN chemical bonds on the n-GaN surface are broken due to O2 plasma treatment; thus, resulting in formed GaO bonds which are interactively understood by using X-ray photoelectron spectroscopy characteristics. After plasma treatment, the forward voltage of VLED is not only reduced owing to decrease in total resistance but also both the light intensity distribution and the light-output-power are improved because of increase in current spreading through the contact layer.

Effects of Annealing Temperature and Ambient on Metal/PtSe2 Contact Alloy Formation.

Forming gas annealing is a common process step used to improve the performance of devices based on transition-metal dichalcogenides (TMDs). Here, the impact of forming gas anneal is investigated for PtSe2-based devices. A range of annealing temperatures (150, 250, and 350 °C) were used both in inert (0/100% H2/N2) and forming gas (5/95% H2/N2) environments to separate the contribution of temperature and ambient. The samples are electrically characterized by circular transfer length method structures, from which contact resistance and sheet resistance are analyzed. Ti and Ni are used as metal contacts. Ti does not react with PtSe2 at any given annealing step. In contrast to this, Ni reacts with PtSe2, resulting in a contact alloy formation. The results are supported by a combination of X-ray photoelectron spectroscopy, Raman spectroscopy, energy-dispersive X-ray spectroscopy, and cross-sectional transmission electron microscopy. The work sheds light on the impact of forming gas annealing on TMD–metal interfaces, and on the TMD film itself, which could be of great interest to improve the contact resistance of TMD-based devices.

A Comprehensive Methodology to Evaluate Losses and Process Variations in Silicon Solar Cell Manufacturing

Novel, high-throughput metrology methods are used in this paper for detailed performance loss analysis of approximately 400 industrial crystalline silicon solar cells, all coming from the same production line. The characterization sequence combines traditional global cell measurements (e.g., current–voltage, Suns- ${V}_{\text{OC}}$ ) with camera-based cell imaging of voltage distribution and power dissipation from photoluminescence and lock-in thermography, respectively. Spatial variations in current collection are visualized using a high-speed external quantum efficiency and reflectance measurement technique. A nondestructive transfer length method (TLM) measurement technique is also implemented, featuring circular TLM structures hidden within the busbars of the cells. The variance of individual loss parameters and their impact on cell performance are quantified for this large group of cells. Based on correlations performed across parameters, recombination losses in the bulk and rear surface of the cell are shown to be the primary limiting factor for the cell efficiency. The nature of these distributions and correlations provide important insights about loss mechanisms in industrial solar cells, helping to prioritize efforts for optimizing the performance of the production line. Additionally, many of the parameters extracted from these techniques can be tied back to incoming material quality issues (e.g., poor bulk carrier lifetime, nonuniform wafer doping) and to individual unit processes (e.g., texturing, phosphorus diffusion, silicon nitride deposition, metallization), allowing the data to be used directly for process control in manufacturing. All of the datasets are made available for download.

Exploring conductivity in ex-situ doped Si thin films as thickness approaches 5 nm

Silicon (Si) has been scaled below 10 nm in multigate and silicon-on-insulator (SOI) device technologies, but clearly Si thickness cannot be reduced indefinitely, as we will run out of atoms eventually. As thickness approaches 5 nm, surfaces and interfaces will significantly impact the electrical behavior of Si, and surface physics cannot be discounted. Below that, bulk material properties will be altered considerably in the few-monolayer limit. One of the most basic defining properties of a semiconductor is its conductivity. To improve conductivity, while inducing a channel by appropriate biasing, it is necessary to define an accurate impurity doping strategy to reduce parasitic resistance. In this paper, we investigated the changing electrical conductivity of SOI films as a function of the Si thickness, in the range of 3–66 nm. SOI films were ex situ doped using three different approaches: liquid/vapor phase monolayer doping of phosphorus using allyldiphenylphosphine, gas-phase doping of arsenic using arsine (AsH3), and room-temperature beam-line ion implantation of phosphorus. The circular transfer length method and micro-four-point probe measurements were used to determine the resistivity of the Si films, mitigating the contribution from contact resistance. The resistivity of the Si films was observed to increase with decreasing Si film thickness below 20 nm, with a dramatic increase observed for a Si thickness at 4.5 nm. This may drastically impact the number of parallel conduction paths (i.e., nanowires) required in gate-all-around devices. Density functional theory modeling indicates that the surface of the Si film with a thickness of 4.5 nm is energetically more favorable for the dopant atom compared to the core of the film.

Low-Temperature RF Plasma Treatment Effect on Junctionless Pd-Al2O3-Ingaas Misfet Operation

The junctionless (JL) device concept for silicon-on-insulator MOSFETs was introduced by Colinge et al. in 2010 [1], demonstrating considerable gains in terms of process simplicity when compared to conventional inversion-mode MOSFETs. The objective of this work is to implement the JL device concept in an In0.53Ga0.47As channel, where the SiO2 insulator in [1] is replaced by a wider bandgap p-type In0.52Al0.48As barrier layer and to investigate the effect of low-temperature RF hydrogen plasma treatment on the main electrical parameters of such devices. The JL device architecture is particularly well suited to III-V channel materials. Firstly, the high doping concentration (Nd) present in the channel of a JL MOSFET is less problematic for In0.53Ga0.47As than it is for Si. Indeed, the bulk electron mobility in Si is ~100 cm2/V·s at Nd = 1×1019 cm-3, while in In0.53Ga0.47As the bulk mobility is ~4,000 cm2/V·s at a similar Nd level. Moreover, the JL architecture circumvents the difficulties associated with the implantation or regrowth techniques generally used to form the source/drain (S/D) regions of III-V inversion-mode MOSFETs. However in order to form a good Ohmic S/D contacts it is necessary to anneal the device at 350-400°C that could lead to diffusion of In atoms into the gate dielectric. In this work low-temperature RF plasma treatment (RFPT) [2] is proposed to improve S/D contacts and enhance the properties of JL MOSFETs. A structure consisting of a 32-nm-thick n- In0.53Ga0.47As (Nd = 2×1018 cm-3) on a 500-nm-thick p-In0.52Al0.48As (Na = 8×1015 cm-3) barrier was grown by metal organic vapour-phase epitaxy (MOVPE) on a p+-InP wafer (Fig. 1 (a)). In order to form a channel for the JL devices, the In0.53Ga0.47As layer was thinned using a 10% H2O2/10% HCl digital wet etching process to achieve channel thicknesses of 24, 20 and 16 nm. A gate enclosed device layout was employed to simplify the fabrication process flow (Fig. 1(b-e)). A surface passivation in 10% (NH4)2S for 30 min was performed before atomic layer deposition (ALD) of an 8.5-nm-thick Al2O3 gate oxide. A Pd gate was formed by e-beam evaporation and lift-off. The Al2O3 on the S/D contact areas was etched in dilute HF. The S/D contact formation was performed by e-beam evaporation of a Au/Ge/Au/Ni/Au stack and lift-off. The RFPT (13.6 MHz) was performed in forming gas (10%H2+90%N2) with additional heating of the sample holder (up to 200°C). Temperature of the samples at the RFPT did not exceed 250°C [2]. Well behaved Id-Vg characteristics measured on the 24-nm-thick In0.53Ga0.47As channel device are shown in Fig. 2. A threshold voltage (VT) of -0.55 V was extracted using the second-derivative method. Scaling the In0.53Ga0.47As channel thickness down to 16 nm improved the subthreshold swing (SS) but degraded the maximum Id and ION/IOFF due to the combined effect of S/D series resistance (RSD) and mobility degradation. As a result, the lowest SS value (115 mV/dec) was extracted on the 16-nm-thick In0.53Ga0.47As channel device and 190 mV/dec - on the 24-nm-thick In0.53Ga0.47As channel one, but the highest ION/IOFF value (1.5×105) was obtained on the 20-nm-thick In0.53Ga0.47As channel device and 2.0×104 - on the 24-nm-thick In0.53Ga0.47As channel one. The gate-to-channel Cgc-Vg characteristic featured a low frequency dispersion near the accumulation region, suggesting a low density of interface traps (Dit) in the upper part of the In0.53Ga0.47As bandgap. Moreover, the conductance analysis yielded low Dit values ranging from 1.5×1012 to 3.5×1012 cm-2×eV-1 from the conductance band edge to midgap, correspondingly. Measurements of RSD on circular transfer length method (CTLM) structures yielded the value of 12 kOhm on the 20-nm-thick In0.53Ga0.47As channel devices and contacts were strongly rectifying. RF plasma treatment with power 0.5 W/cm2 at 150°C resulted in Ohmic SD contact, a strong decrease of RSD down to 45 Ohm (Fig. 3) and increases the ION by two orders of magnitude (Fig. 2). Additionally, SS for the plasma treated devices decreases from 190 mV/dec to 150 mV/dec, and the threshold voltage shifts to positive values by 0.4 V (Fig.2). This is associated, correspondingly, with a decrease of Dit and negative charge in the gate dielectric. The conductance analysis yielded reduction of Dit at midgap down to 1.0×1012 cm-2×eV-1. [1] Colinge J.-P., Lee C.-W., Afzalian A., Akhavan N.D., Yan R., Ferain I., Razavi P., O'Neill B., Blake A., White M., Kelleher A.-M., McCarthy B., Murphy R. Nanowire Transistors Without Junctions. Nature Nanotechnology. Vol. 5, P. 225-229 (2010). [2] Nazarov A.N., Lysenko V.S., Nazarova T.M. Hydrogen Plasma Treatment of Silicon Thin-film Structures and Nanostructured Layers. Semiconductor Physics, Quantum Electronics & Optoelectronics. Vol. 11, P. 101-123 (2008). Figure 1

A comparative study of Ti and Cr based p-ohmic contacts on high power GaAs laser diodes

The present work involves a comparison of sequentially evaporated Ti/Pt/Au and Cr/Au p-ohmic contacts for high power laser diode fabrication. Subsequently, the contacts were annealed at 440 °C in furnace annealing under N2 ambient and their surfaces were evaluated by optical and electron microscopy. The specific contact resistivity of the contacts was determined by circular transfer length method (c-TLM). Secondary ion mass spectroscopy (SIMS) analysis of the annealed contacts indicates considerable intermixing of the metal and Ga atoms across the interface for Cr/Au contact. On the other hand, insignificant intermixing of atoms was observed in Ti based contacts. The electrical and optical characteristics of the laser diodes formed with Ti/Pt/Au ohmic contact suggest superior performance compared to the diode formed with Cr/Au contact.

Investigation of Electromigration Degradation Mechanism in Ti/Pt/Au Ohmic Contacts to p-GaAs Under High Current Density Stress

The degradation mechanism of Ti/Pt/Au ohmic contacts to p-GaAs was identified experimentally under high direct-current density stress in detail. A revised measuring structure was designed based on the circular transfer length method (CTLM), in which the high current density of $0.8\times 10^{5}$ A/cm2 was applied vertically, while the contact resistance was measured horizontally between two contact electrodes. According to revised CTLM, the specific contact resistance was measured during stress. The results indicated that specific contact resistance showed an exponential dependence on the aging time. The depth profiling results obtained from the Auger electron spectroscopy showed that Pt penetrated into the Au layer during stress. Furthermore, some voids were observed at the Au/Pt interface, and intermixing began to form within metal layer during stress. These results demonstrated that the degradation of Ti/Pt/Au ohmic contacts to p-GaAs was attributed mainly to the electromigration and Joule heating along the current direction under high current density.

Electrical Contact Property of GeCu2Te3 Phase Change Material to Electrode

To overcome the scaling limits of flash memory, new phase change materials has been intensively studied for phase change random access memory (PCRAM). Currently, Ge-Sb-Te (GST) film has been widely studied for commercial PCRAM. However, GST shows a poor thermal stability of amorphous phase because of its low crystallization temperature (~160 °C). Consequently, GST PCRAM shows a poor data retention property in high temperature and is suppressed to show a low thermal disturbance resistance in high density array. Recently, Sutou et al. have found that GeCu2Te3 (GCT) shows higher crystallization temperature (~230 °C) than GST. Moreover, they demonstrated that the reset process in GCT memory cell exhibits lower power consumption than that in GST memory cell, which is due to a low melting point of GCT (~500 °C). Since GCT shows phase change speed as fast as GST, it is promising PCM for future PCRAM.The memory cell resistance in PCRAM is very essential factor for accuracy in data reading. As the memory cell size is scaled down, the resistance of the memory cell becomes dominated by the contact resistance between the phase change material (PCM) and electrode. Nevertheless, studies of contact resistance in PCRAM are still limited. To understand the contact resistivity and its contrast between amorphous and crystalline states is more essential for future PCRAM. Therefore, in this study, the contact resistivity of GCT to electrodes was investigated using the circular transfer length method (CTLM). A CTLM pattern was fabricated by photolithography in order to measure the contact resistivity. GCT amorphous film was deposited on SiO2/Si substrates by co-sputtering of GeTe and CuTe targets. For comparison, GST amorphous film was also prepared. GCT crystalline film was obtained by heating the as-deposited amorphous film up to 300 °C in an Ar atmosphere. After reverse sputtering of the surface of the GCT layer, a metal electrode was deposited on the GCT films in the same chamber to prevent the surface oxidation effects. Electrical resistance of the CTLM patterned samples were measured by four-point probe method. Based on the obtained results, the contact resistivity of GCT to electrode was calculated. Current (I) - Voltage (V) characteristics of GCT CTLM samples showed an Ohmic behavior in both amorphous and crystalline states. The contact resistivity could be successfully obtained from GCT CTLM samples in both states since the relationship between the total resistance of CTLM samples and the gap spacing showed a liner relation. The contact resistivity of W/amorphous GCT (as-deposited) contact was calculated to be 3.9×10-2 Ω cm2, while that of W/crystalline GCT (annealed at 300 °C) contact was found to be 4.8 ×10-6 Ω cm2. The ρ c of W/amorphous GST (as-deposited) was 3.2 ×10-2 Ω cm2, whereas that of W/crystalline GST (annealed at 300 °C) was 1.4×10-5 Ω cm2. The resistivity contrast in GCT between amorphous and crystalline state was about one order of magnitude smaller than that in GST. Meanwhile, the contact resistivity contrast in GCT between amorphous and crystalline state was slightly larger than that in GST. Based on the obtained results, we calculated the total resistance of simple memory cell model. When the PCM layer thickness, t is over 10-2 m, the resistance contrast of the GCT memory cell was 17 times smaller than that of the GST cell. This is because the cell resistance is dominated by the ρ of PCM. Meanwhile, the resistance contrast of the GCT cell becomes 4 times larger than that of the GST cell at t < 10 nm because the cell resistance is dominated by the ρ c of PCM to electrode. Therefore, GCT is expected to show not only better thermal stability but also better accuracy in data readout than GST. In the presentation, we will also discuss the electrode dependence of the contact resistivity in GCT film.

Structural and Electrical Investigation of MoS2 Thin Films Formed By Thermal Assisted Conversion of Mo Metal

Due to the performance and economic benefit obtained by scaling, future semiconductor electron devices for logic functions will progress toward ultra-thin-body channels and 2-dimensional (2D) high carrier mobility materials. The significance is that small devices can be made to yield higher performance and greater energy-efficiency. To put this trend in perspective, fin-field-effect-transistor[i],[ii] (FinFET) technology was a research topic 7-8 years ago, but is now at the heart of the microprocessor in high-end smartphones.[iii] While the positioning of TMDs in electronic products of the future is still unsure, perhaps they will be more suited to low power, it is still worthwhile to understand how a relatively undeveloped system can reach maturity in less than a decade. Graphene is semi-metallic, which makes it difficult to switch off electron devices such as FETs. Bandgap engineering is required to open a bandgap of graphene, which is not an easy undertaking. This has motivated the scientific community to search for alternate 2D layer materials with semiconducting properties and better tuneability. Many TMDs are natural semiconductors with thicknesses on the nanometre scale. TMD semiconductors are now emerging as potentially useful materials, where more research is needed, in order to explore their properties and potential applications. Large-area synthesis is of great demand for the preparation of high-performance transition-metal-dichalcogenides (TMD) devices, however reports of device operation on large-area TMDs are sparse. In this work we fabricate MoS2 devices based on Thermal Assisted Conversion (TAC) of metal layers, and characterise the thin-films with material analysis combined with electrical device parameter extraction. Specifically we perform parameter extraction for MoS2 thin-films to determine sheet resistance (Rsh), resistivity (ρ), and activation energy (EA) of on-state current flow. For undoped MoS2, ρ was determined to be 191 Ω.cm at 25 °C. EA of the on-state current found to be 0.18 eV, points to a current generation mechanism possibly linked to a deep level in MoS2.In Fig. 1 are representative images of the 10 nm sulphurised Mo, forming approximately 20 nm of MoS2. In (a) a wide view of MoS2 on a SiO2/Si substrate. On the right-hand side the Ti/Au metal contact is visible. The MoS2 layer is continuous across the surface. In (b) the layered structure of MoS2 is visible in the higher resolution image. In Fig. 2 are representative measured current versus voltage characteristic in the MoS2 circular Transfer Length Method structure as a function of contact spacing. The current is linear with respect to voltage and passes through the origin. The current increases with decreased contact spacing as expected. The inset shows an optical images of the circular TLM structure. : [i] J. –P. Colinge (Ed.), “FinFETs and other Multi-Gate Transistors” ISBN 978-0-387-71752-4, Springer (2008). [ii] N. Collaert (Ed.), “CMOS Nanoelectronics: Innovative Devices, Architectures, and Applications” ISBN 9789814364027, Pan Stanford (2012). [iii] J. Borland, ECS Transactions, 69 (10) 11-20 (2015). Figure 1

Contact resistivity of amorphous and crystalline GeCu2Te3 to W electrode for phase change random access memory

We have investigated the contact resistivity of GeCu2Te3 (GCT) phase change material to a W electrode using the circular transfer length method (CTLM). The contact resistivity ρc of as-deposited amorphous GCT to W was 3.9×10−2Ωcm2. The value of ρc drastically decreased upon crystallization and crystalline GCT that annealed at 300°C showed a ρc of 4.8×10−6Ωcm2. The ρc contrast between amorphous (as-deposited) and crystalline (annealed at 300°C) states was larger in GCT than in conventional Ge2Sb2Te5 (GST). Consequently, it was suggested from a calculation based on a simple vertical structure memory cell model that a GCT memory cell shows a four times larger resistance contrast than a GST memory cell.