A 60-GHz variable-gain active phase shifter using particular-sized digital-RF cells is proposed, which is fabricated using a 65-nm CMOS process. The phase shifter consists of an input buffer, an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I/Q$ </tex-math></inline-formula> generator, and vector-summing amplifiers with digital-RF cells. In a vector-sum phase shifter using a conventional tail current steering scheme, the operation regions of vector-summing amplifiers are changed with phase and gain states. Accordingly, their input impedances are altered significantly, which causes gain and phase imbalances of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I/Q$ </tex-math></inline-formula> generator, especially around 0°, 90°, 180°, and 270°. This makes the rms phase and gain errors of the phase shifter increase. In this article, a vector-summing amplifier that always has a constant input impedance in all phases and gain states is proposed. A circular constellation and a dynamic range of more than 15 dB are implemented by using particular-sized digital-RF cells. The proposed phase shifter shows the rms gain and phase errors of < 0.29 dB and <2.01°, respectively, in a 10-GHz bandwidth of 55–65 GHz with 3-bit gain and 4-bit phase resolutions. The chip area and power consumption are 0.38 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 25.2 mW, respectively.