Circuit-level Model Research Articles

SuperSIM: a comprehensive benchmarking framework for neural networks using superconductor Josephson devices

Abstract This paper introduces SuperSIM, a benchmarking framework tailored for neural networks using superconducting Josephson devices, specifically focusing on Adiabatic Quantum Flux Parametron (AQFP) based Processing-in-Memory (PIM) architectures. Our framework offers in-depth architecture-level simulations and performance assessments to enhance AQFP PIM chip development. It supports single and multi-bit PIM designs, various AQFP memory cell types, and diverse clocking methods. Additionally, it integrates circuit-level models for precise energy, delay, and area measurements, ensuring accurate performance evaluation. The framework includes application, device, and architectural layers for versatile configurations and cycle-accurate energy, latency, and area simulations. Experiments validate our framework, with case studies on algorithm and architecture-level features, examining data precision, crossbar size, operating frequency and clocking scheme impacts on computational accuracy, energy use, overall latency and hardware cost.

Removing direct photocurrent artifacts in optogenetic connectivity mapping data via constrained matrix factorization.

Monosynaptic connectivity mapping is crucial for building circuit-level models of neural computation. Two-photon optogenetic stimulation, when combined with whole-cell recording, enables large-scale mapping of physiological circuit parameters. In this experimental setup, recorded postsynaptic currents are used to infer the presence and strength of connections. For many cell types, nearby connections are those we expect to be strongest. However, when the postsynaptic cell expresses opsin, optical excitation of nearby cells can induce direct photocurrents in the postsynaptic cell. These photocurrent artifacts contaminate synaptic currents, making it difficult or impossible to probe connectivity for nearby cells. To overcome this problem, we developed a computational tool, Photocurrent Removal with Constraints (PhoRC). Our method is based on a constrained matrix factorization model which leverages the fact that photocurrent kinetics are less variable than those of synaptic currents. We demonstrate on real and simulated data that PhoRC consistently removes photocurrents while preserving synaptic currents, despite variations in photocurrent kinetics across datasets. Our method allows the discovery of synaptic connections which would have been otherwise obscured by photocurrent artifacts, and may thus reveal a more complete picture of synaptic connectivity. PhoRC runs faster than real time and is available as open source software.

Fractional Marcus-Hush-Chidsey-Yakopcic current-voltage model for redox-based resistive memory devices.

We propose a circuit-level model combining the Marcus-Hush-Chidsey electron current equation and the Yakopcic equation for the state variable for describing resistive switching memory devices of the structure metal-ionic conductor-metal. We extend the dynamics of the state variable originally described by a first-order time derivative by introducing a fractional derivative with an arbitrary order between zero and one. We show that the extended model fits with great fidelity the current-voltage characteristic data obtained on a Si electrochemical metallization memory device with Ag-Cu alloy.

Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T–4R structure for high-density memory

Emerging data-intensive computation has driven the advanced packaging and vertical stacking of integrated circuits, for minimized latency and energy consumption. Yet a monolithic three-dimensional (3D) integrated structure with interleaved logic and high-density memory layers has been difficult to achieve due to challenges in managing the thermal budget. Here we experimentally demonstrate a monolithic 3D integration of atomically-thin molybdenum disulfide (MoS2) transistors and 3D vertical resistive random-access memories (VRRAMs), with the MoS2 transistors stacked between the bottom-plane and top-plane VRRAMs. The whole fabrication process is integration-friendly (below 300 °C), and the measurement results confirm that the top-plane fabrication does not affect the bottom-plane devices. The MoS2 transistor can drive each layer of VRRAM into four resistance states. Circuit-level modeling of the monolithic 3D structure demonstrates smaller area, faster data transfer, and lower energy consumption than a planar memory. Such platform holds a high potential for energy-efficient 3D on-chip memory systems.

BRIEF REVIEW ON SOLAR PHOTOVOLTAIC PARAMETER ESTIMATION OF SINGLE AND DOUBLE DIODE MODEL USING EVOLUTIONARY ALGORITHMS

In modern years several researchers contribute to renewable energy specifically solar as atmosphere responsive. Solar panels are an essential and chief constituent for solar energy selecting as they are active in transformation of solar radioactivity into electrical voltage correspondent. The principal concern in optimum generation of power from these solar panels is to be contingent on numerous characteristics mostly correlated to the sizing and modelling of photovoltaic (PV) panels for the essential presentations. An array of solar cells is castoff for generation of slight to average gauge power generation in numerous cases. Sizing of panels, the storing progression and application of electrical tracks in the procedure are some vital research qualities which together regulate and describe supreme power generation from solar panel. Parameter and circuit level modelling has been occupied as major problem of examination and several state of the art practices to govern the ideal sizing with respect to many circuit models such as single diode model (SDM) and double diode models (DDM) have been inspected in an widespread way in this review article. It offers the perceptions, features, and climaxes the strength and weaknesses of PV cell models. This article debates some algorithms and methods used in both SDM and DDM and a deep learning into the investigation of parameter assessments in each diode have been studied. Based on the showed evaluation, some commendations for upcoming research are provided.

Circuit-Level Modeling and Simulation of Wireless Sensing and Energy Harvesting With Hybrid Magnetoelectric Antennas for Implantable Neural Devices.

A magnetoelectric antenna (ME) can exhibit the dual capabilities of wireless energy harvesting and sensing at different frequencies. In this article, a behavioral circuit model for hybrid ME antennas is described to emulate the radio frequency (RF) energy harvesting and sensing operations during circuit simulations. The ME antenna of this work is interfaced with a CMOS energy harvester chip towards the goal of developing a wireless communication link for fully integrated implantable devices. One role of the integrated system is to receive pulse-modulated power from a nearby transmitter, and another role is to sense and transmit low-magnitude neural signals. The measurements reported in this paper are the first results that demonstrate simultaneous low-frequency wireless magnetic sensing and high-frequency wireless energy harvesting at two different frequencies with one dual-mode ME antenna. The proposed behavioral ME antenna model can be utilized during design optimizations of energy harvesting circuits. Measurements were performed to validate the wireless power transfer link with an ME antenna having a 2.57 GHz resonance frequency connected to an energy harvester chip designed in 65nm CMOS technology. Furthermore, this dual-mode ME antenna enables concurrent sensing using a carrier signal with a frequency that matches the second 63.63 MHz resonance mode. A wireless test platform has been developed for evaluation of ME antennas as a tool for neural implant design, and this prototype system was utilized to provide first experimental results with the transmission of magnetically modulated action potential waveforms.

Systematic Design Method for Mutual Coupling Reduction in Closely Spaced Patch Antennas

In this article, a systematic design approach is presented to reduce the mutual coupling between a pair of closely spaced microstrip patch antennas (MPAs). This method can effectively overcome the main drawback of previous two-path cancellation methods, i.e., lack a systematic design guideline and heavily rely on the time-expensive trial-and-error procedure to mitigate mutual coupling in a best-effort manner. To this end, we first propose the concept and workflow of the systematic design method, and introduce the circuit-level modeling upon the proposed two coupling routes. Then, prototyped on a practical and simple physical structure, we perform certain accurate extractions and derive the rigorous conditions for both of isolation between two patches and impedance matching of a single patch based on these two paths. Afterwards, according to the circuit-level discussion on lumped elements, the corresponding decoupling structure could be implemented substantially and designed quantitatively at the antenna level for particularized closely spaced MPAs. Finally, a prototype is simulated, fabricated, and measured to validate the proposed method. The results show that the circuit-model calculation, full-wave simulation, and measurement are in good agreement. By virtue of such a simple decoupling structure, the poor 7-dB isolation is dramatically improved to 58 dB, and the isolation is enhanced beyond 20 dB in the entire impedance matching bandwidth range of 4.38 4.60 GHz (4.9%), with the closely center-to-center spacing of 0.37 λ0.

A compact circuit-level model for single-event burnout in SiC power MOSFET devices

This paper presents a compact circuit-level model for single-event burnout (SEB) in silicon carbide (SiC) metal-oxide field-effect transistors (MOSFETs). Key parameters of the equivalent circuit model of the MOSFET are analyzed and determined in detail, including nonlinear parasitic drain-source capacitance and nonlinear parasitic gate-drain capacitance. The effect of the parasitic bipolar junction transistor is considered and an iteratively optimized double-exponential current source is used to simulate the transient power current generated by incident heavy ions. The equivalent circuit model of the MOSFET is verified by comparing the SPICE simulation curves, TCAD simulation curves, and the curves in the SiC power double trench MOSFET’s datasheet (SCT3080KL). Then, the SEB is caused by heavy ions at various incident positions, linear energy transfer values, drain-source voltage (V ds), and gate-source voltage (V gs) using the TCAD and HSPICE simulations. Simulation results on the SPICE model coincide with the TCAD simulation results. Moreover, this compact model is used to predict the SEB threshold for devices with higher breakdown voltage ratings.

CEVGMM: Computationally Efficient Versatile Generic Memristor Model

A memristor is a passive circuit element that has numerous applications ranging from storage to processing. The attributes of memristor, such as low power, fast switching speed, and non-volatility, make it a promising candidate for computing applications. To deploy the memristors at the circuit level, a versatile, computationally efficient, and generic model is required to analyze the circuit performance. This article presents a computationally inexpensive, generic, and accurate phenomenological model of the memristor. The proposed model predicts an accurate current–voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> ) relationship based on the current conduction mechanism. The presented modeling technique can be incorporated into any practical memristor behavior by optimizing the fitting parameters. The model has the capability to optimize its accuracy and computational efficiency by calibrating the model parameters. The results are compared with the characterization data of numerous memristors and noteworthy models of memristors to validate the proposed approach. The results depict that the proposed model is more flexible, computationally efficient, versatile, and generic. It improves the simulation run time up to 24.47% with the relative root mean squared error of 0.4142%. The model exhibits remarkable results when compared with titanium dioxide-based devices. The proposed model can be deployed to various applications, such as logic design, memory design, and neuromorphic computing.

Comparative Pharmacology and Circuit-Level Models of the Effects of Psychedelic Drugs on the Human Brain

Comparative Pharmacology and Circuit-Level Models of the Effects of Psychedelic Drugs on the Human Brain

A ply-level electrical resistance approach to monitor crack evolution in a laminate SiC/SiC composites

In the aim of providing a reliable technique to monitor the development of damage in 0°/90° melt-infiltrated SiC-fiber reinforced prepreg laminate ceramic-matrix composites, it was hypothesized that the electrical resistivities of different layers of this material were significantly different due to their free Si content and morphology. Three distinct layers: a 0° fiber ply, a 90° fiber ply and a matrix only ply, were distinguished in the composite architecture. Free silicon is the most conductive phase in this composite system; however, the Si content and morphology were different in each of the three types of plies. Unidirectional and [0°/90°]2s specimens enabled quantification of ply-level resistivities. An electric circuit model was constructed; it consists of parallel resistors where each resistor represents a ply in the composite system. This ply-level electrical model was validated using composites of different vintages which contained different silicon contents. A room temperature stepped fatigue test was conducted and the ply level circuit model was used to discern crack morphology with the support of acoustic emission and digital image correlation.

An Equivalent Circuit Model of Passively Mode-Locked Hybrid Silicon Laser

In this letter, for the first time, we present a circuit-level model (CLM) of semiconductor mode-locked laser (MLL) based on delay differential equation (DDE). To confirm that our model is valid for different structures, the CLM of the hybrid silicon MLL is analysed for the cases without and with an intracavity filter. The ability of CLMs to replicate dynamic behavior of repetition rate is demonstrated. Furthermore, the effect of linewidth enhancement factor (LEF) on pulse width and peak power is investigated. The presented model simulates transition from mode-locking to chaotic regime by changing LEF, rigorously. The results of CLM are in good agreement with numerical and experimental results reported in other works. By a versatile procedure introduced in this letter for CLM, different type of MLLs based on DDE can be developed.

Volatile Memristor in Leaky Integrate-and-Fire Neurons: Circuit Simulation and Experimental Study

In this paper, circuit implementation of a leaky integrate-and-fire neuron model with a volatile memristor was proposed and simulated in the SPICE simulation environment. We demonstrate that simple leaky integrate-and-fire (LIF) neuron models composed of: volatile memristor, membrane capacitance and neuron resistance can mimic spatial and temporal integration, firing function and signal decay. The existing leaky term originates from the recovery of the initial resistive state in the memristor in the spontaneous reset cycle, which is essential for emulating the forgetting process in all-memristive neural networks (MNNs). Furthermore, a diffusive perovskite memristor was used to validate the model where intrinsic memristors’ capacitance acts as neuron membrane capacitance. Good agreement with experimental and simulation results was observed. Volatility, as an inherent property of specific memristors, eliminates the need for usage of an additional peripheral circuit which will reinitialize device state, thus allowing the development of energy-efficient, large scale complex memristive neural networks. The presented circuit level model of LIF neurons can facilitate the design of MNNs.

Numerical Demonstration of 800 Gbps WDM Silicon Photonic Transmitter with Sub-Decibel Surface-Normal Optical Interfaces.

We propose and numerically demonstrate an 800 Gbps silicon photonic transmitter with sub-decibel surface-normal optical interfaces. The silicon photonic transmitter is composed of eight silicon Mach–Zehnder optical modulators and an interleaved AMMI WDM device. This WDM device comprises two 1 × 4 angled MMI and a Mach–Zehnder interferometer (MZI) optical interleaver with an apodized bidirectional grating which has about −0.5 dB coupling loss. Both the Mach–Zehnder electro-optical modulators and MZI optical interleaver regard the bidirectional grating coupler as vertical optical coupler and 3-dB power splitter/combiner. By importing the S-parameter matrices of all the components which have been carefully designed in simulation software, the circuit-level model of the optical transmitter can be built up. On this basis, the static and dynamic performance characterization were carried out numerically. For NRZ modulation, the optical transmitter exhibits the overall optical loss of 4.86–6.72 dB for eight wavelength channels. For PAM4 modulation, the optical loss is about 0.5 dB larger than that of NRZ modulation, which varies between 5.38–7.27 dB. From the eye diagram test results, the WDM silicon photonic transmitter can achieve single channel data transmission at 100 Gb/s NRZ data or 50 GBaud/s PAM4 symbol rate with acceptable bit error rate.

Models of psychedelic drug action: modulation of cortical-subcortical circuits.

Classic psychedelic drugs such as psilocybin and lysergic acid diethylamide (LSD) have recaptured the imagination of both science and popular culture, and may have efficacy in treating a wide range of psychiatric disorders. Human and animal studies of psychedelic drug action in the brain have demonstrated the involvement of the serotonin 2A (5-HT2A) receptor and the cerebral cortex in acute psychedelic drug action, but different models have evolved to try to explain the impact of 5-HT2A activation on neural systems. Two prominent models of psychedelic drug action (the cortico-striatal thalamo-cortical, or CSTC, model and relaxed beliefs under psychedelics, or REBUS, model) have emphasized the role of different subcortical structures as crucial in mediating psychedelic drug effects. We describe these models and discuss gaps in knowledge, inconsistencies in the literature and extensions of both models. We then introduce a third circuit-level model involving the claustrum, a thin strip of grey matter between the insula and the external capsule that densely expresses 5-HT2A receptors (the cortico-claustro-cortical, or CCC, model). In this model, we propose that the claustrum entrains canonical cortical network states, and that psychedelic drugs disrupt 5-HT2A-mediated network coupling between the claustrum and the cortex, leading to attenuation of canonical cortical networks during psychedelic drug effects. Together, these three models may explain many phenomena of the psychedelic experience, and using this framework, future research may help to delineate the functional specificity of each circuit to the action of both serotonergic and non-serotonergic hallucinogens.

Accurate Circuit-Level Modelling of IGBTs with Thermal Phenomena Taken into Account

This paper proposes a new compact electrothermal model of the Insulated Gate Bipolar Transistors (IGBT) dedicated for SPICE (Simulation Program with Integrated Circuit Emphasis). This model makes it possible to compute the non-isothermal DC characteristics of the considered transistor and the waveforms of terminal voltages and currents of the investigated device and its internal temperature at transients. This model takes into account the nonlinearity of thermal phenomena in this device. The form of the formulated model is described and the problem of estimating its parameter values is discussed. The correctness of the proposed model was verified experimentally both at DC operation and at transients. The obtained results are compared to the results of computations performed with the use of the classical literature model. A very good agreement between the results of measurements and computations performed with the new model is obtained at different cooling conditions and in a wide range of changes of parameters characterising the electrical excitation of the tested device.

A circuit-level inverter-based switched capacitor integrator model justified by post-layout simulations of an incremental sigma-delta converter

This paper proposes a circuit-level model of an inverter-based switched-capacitor (SC) integrator involved in a previously published incremental sigma-delta analog-to-digital converter (I $$\Sigma {\Delta }$$ ADC) to explain the ADC resolution degradation observed in the post-layout simulation. A fine analysis of post-layout signals led to a new model of the integrator with parasitic capacitors. Then the model has been included in the I $$\Sigma {\Delta }$$ ADC model, which has been simulated with Matlab. To get detailed results and be able to handle comparisons, various calibration techniques have been applied to the I $$\Sigma {\Delta }$$ ADC outputs coming from post-layout simulation and from the new model so that a better resolution is achieved. The results show a good likeness of the error shapes and magnitudes for the new model compared to post-layout simulations. We deduce that the proposed model is a good representation of the degradation phenomena, this with a high level of confidence.

Algorithmic Approach of Electrically Doped Single-walled Cytosine Nanotube-based Biomolecular Logic Gate: A First Principle Paradigm

Biomolecular modeling and its associated analytical software simulation tools have a significant role in the rapid progress of bio-inspired semiconductor technologies. This paper presents the implementation of logic gates using molecular modeling of a cytosine-based single-walled nanotube. Density functional theory in and the nonequilibrium Green’s function-based first-principles approach are used to perform the quantum mechanical calculations for the electronic transmission within the nanotube. The gated cytosine single-walled nanotube shows high current-voltage response during room-temperature operation where the electrode voltage is kept at ± 0.02 V. This is a first attempt towards the circuit-level modeling of logic gates using a cytosine nanotube. The quantum transport phenomenon of this analytical model is investigated using an atomistic software simulation technique. The basic logic gates and XNOR gate are implemented with the study of the current-voltage characteristics. The maximum current observed during the simulation process is 52.6 μA. Moreover, the local device density at different energy levels proves the candidature of cytosine nanotubes as logic gates. The transmission spectrum analysis also confirms the high channel conductivity at the central scattering region of the nanotube.

An Analytical Evaluation of the Shielding Effectiveness of Enclosures Containing Complex Apertures

Analytical methods are significantly useful tools for engineers in computational modeling. These methods provide fast simulations, while preserving physical meaning. In this paper, a full analytical formulation is developed based on the circuit approach, also known as Intermediate Level Circuit Model (ILCM), to evaluate the shielding effectiveness (SE) of metallic structures. The proposal focuses on rectangular enclosures containing apertures of complex geometrical shape, illuminated by an external plane wave. The enclosure is taken as a short-circuited waveguide. The aperture is treated as a transmission line with an intrinsic impedance that depends on the aperture polarizability, according to Bethe’s theory of small holes. The formulation easily takes into account high-order resonant modes and different apertures, such as circular, elliptical, round-ended and cross-shaped apertures. The ILCM technique reveals good agreement with a numerical full-wave method for various configurations of enclosures, covering a large range of frequencies from 0.5 GHz to 2.5 GHz, thus offering perspectives for parametric and/or optimization SE studies.

On Applications of Elements Modelled by Fractional Derivatives in Circuit Theory

In this paper, concepts of fractional-order (FO) derivatives are reviewed and discussed with regard to element models applied in the circuit theory. The properties of FO derivatives required for the circuit-level modeling are formulated. Potential problems related to the generalization of transmission-line equations with the use of FO derivatives are presented. It is demonstrated that some formulations of FO derivatives have limited applicability in the circuit theory. Out of the most popular approaches considered in this paper, only the Grünwald–Letnikov and Marchaud definitions (which are actually equivalent) satisfy the semigroup property and are naturally representable in the phasor domain. The generalization of this concept, i.e., the two-sided fractional Ortigueira–Machado derivative, satisfies the semigroup property, but its phasor representation is less natural. Other ideas (including the Riemann–Liouville and Caputo derivatives—with a finite or an infinite base point) seem to have limited applicability.