Circuit-level Design Research Articles

Design of SEE-Tolerant analog switch chip with a novel diode structure *

This paper proposes a novel circuit-level design in order to enhance the radiation tolerance of an analog switch integrated circuit. After analyzing the mechanisms of single-particle sensitivity in a high-voltage analog switch chip fabricated using a commercial 1 μm complementary metal–oxide–semiconductor process, a diode unit was employed to reduce the V GS (voltage between the gate and the base) of the parasitic triode within the metal–oxide–semiconductor field-effect transistor of the switch. This reduction lowered the probability of activating the parasitic triode in response to single-event effect (SEE). Subsequently, single-particle irradiation experiments proceeded with the high-voltage analog switch chip, both with and without the diode unit. In the unreinforced device, the current of the power supply reached 100 mA within 11 s of single-particle irradiation at 75.8 MeV•cm2 mg−1. In contrast, in the reinforced device, the current of the power supply remained relatively stable under irradiation at both 37.2 and 75.8 MeV•cm2 mg−1. These findings indicate that the reinforced analog switch chip exhibits an SEE tolerance exceeding 75.8 MeV•cm2 mg−1, highlighting its potential to enhance the radiation tolerance of analog switches.

Review of Carbon Nanotube Field Effect Transistor for Nanoscale Regime

Background: The need for high performance, small size, low delay, low power consumption, and long battery backup of portable systems is increasing with the advancement of technology. Many features of portable systems can be improved using scaling methods. In the scaling process, reducing the size of devices causes serious difficulties, including the short channel effect (SCE) and leakage current, which degenerates the characteristics of the systems. Objective: In this review paper, a trending carbon nanotube field effect transistor (CNTFET) technology is discussed in detail. CNTFET can replace the conventional metal oxide semiconductor field effect transistor (MOSFET) technology to overcome the SCE problems in the nanoscale regime and also meet the requirements of portable systems. Methods: The CNTFET is an extremely good nanoscale technology due to its one-dimension band structure, high transconductance, high electron mobility, superior control over channel formation, and better threshold voltage. This technology is used to construct high-performance and low-power circuits by replacing the MOSFET technology. CNTFET in comparison to MOSFET takes the carbon nanotube (CNT) as a channel region. Results: The value of threshold voltage in CNTFET changes with the diameter of CNT. The threshold voltage of the devices controls many parameters at the circuit-level design. Hence, the detailed operation and the characteristics of CNTFET devices are presented in this review paper. The existing CNTFET-based ternary full adder (TFA) circuits are also described in this review paper for the performance evaluation of different parameters. Conclusion: CNTFET technology is the possible solution for the SCE in the nanoscale regime and is capable to design efficient logic circuits. The circuits using the CNTFET technology can provide better performance and various advantages, including fast speed, small area, and low power consumption, in comparison to the MOSFET circuits. Thus, CNTFET technology is the best choice for circuit designs at the nanoscale.

Circuit-level design of radiation tolerant memory cell

As transistors shrink in size, the integration density of memory circuits like Static Random Access Memory (SRAM) cells rises, making them increasingly susceptible to Single Event Effects (SEE). In the space environment, memory circuits face stability and reliability challenges due to the presence of various charged particles such as α-particles, neutrons, electrons, heavy ions, and photons. These high-energy particles create ion tracks when they strike the memory device, leading to upsets in the storage bits. Conventional 6 T SRAM cells are susceptible to these upsets. As a solution this paper proposes a new Radiation Tolerable (RT 13 T) SRAM cell that is better suited for deep-space applications compared to other memory cell. RT13T has been validated to withstand radiation hazards through Critical Charge (QCrit) analysis, which shows that it exhibits 1.17×, 1.1×, 1.94× and 1.06× highest QCritthan QUCCE 10 T/12 T,traditional 6 T and LIOR 13 T memory cells, respectively. As the comparison made, our Proposed RT 13 T saved by5.1 %,9.9 %, 20.1 % and 7 % of the power consumption compared to QUCCE10T/12 T/LIOR 13 T/SERSC-16 T SRAM cells at a nominal supply voltage of 0.7 V. It also exhibits shorter read delay (TRA) 10.6 %, 1.34 %, 9.6 %, 22.16 %compared to QUCCE 10 T/12 T,6T, SERSC-16Tmemory cells, respectively. In terms of stability,our proposed RT13T SRAM cell exhibits 2.32×/2.05×/2.9×/1.05×/1.01 × higher read stability as compared with QUCCE10T/12 T/6T/LIOR 13 T/SERSC-16 T memory cells during the read operation. The our proposed RT13T shows improvements in design metrics are at the expense of a longer write delay. To characterize the performances of the proposed RT13T, 16-nm CMOS predictive technology model and validated through extensive simulation with licensed PrimeSim HSPICE of Synopsys. The results of our proposed RT13T cell are compared with some other previously proposed memory cells such as 6 T, QUCCE 10 T, QUCCE 12 T, LIOR 13 T and SERSC-16 T memory cells. The obtained results are tabulated and plotted for graphical analysis. In terms of area consumption our proposed 13 T consumes 0.9×/0.6 × lesser area than QUCCE 12 T/SERSC-16 T memory cells but our proposed circuit consumes 3.1×/1.08×/1.05 × more area than QUCCE10T/conventional 6 T/LIOR 13 T because QUCCE10T and 6 T consist of less number of transistors in memory cells.The cell proposed in this paper demonstrates strong radiation-hardened capabilities and excellent overall performance, making it well-suited for aerospace electronic devices and ensuring stable operation in space radiation environments.

Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons

Computation on a large volume of data at high speed and low power requires energy-efficient architectures for edge computing applications. As a result, scientists focus on memristive circuits and systems for area and energy efficiency. Spiking neural network (SNN) with bio-inspired spike-timing-dependent plasticity learning (STDP) is a promising solution for energy-efficient neuromorphic systems than conventional artificial neural network (ANN). Previous works on SNN with STDP learning primarily use memristor macro models, which are software-based and cannot give complete insight into circuit implementation challenges. Some reported works on SNN use memristive devices, which require additional fabrication steps. This article presents a full circuit-level implementation of the SNN system featuring on-chip training and classification using memristive STDP synapse in standard CMOS technology. A new learning rule using the modified STDP is implemented to simplify the weight modification process. It does not involve FPGAs, CPUs, or GPUs to train the neural network. The approach used in this paper to modify the weights does not require any additional combinational or digital circuits attached to the memristive synapse resulting in less consumption of area, energy and time. We demonstrated the complete circuit-level design, implementation and simulation of SNN with on-chip training and pattern classification using 180 nm CMOS technology. A comprehensive comparison of the proposed SNN circuit with the previous related work is also presented. To demonstrate the versatility of the CMOS synapse circuit for application scenarios requiring rate-based learning, we have tuned the pair-based STDP circuit to obtain Bienenstock–Cooper–Munro (BCM) characteristics and applied it to heart rate classification.

A Low-Power V-Band Radar Transceiver Front-End Chip Using 1.5 V Supply in 130-nm SiGe BiCMOS

Energy-efficient, low-voltage, and low-power millimeter-wave (mm-wave) radars are gaining increasing attention for battery-powered commercial applications. In this article, the design of a low-power <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> -band radar sensor based on a transceiver (TRX) front-end chip using 1.5 V supply in an advanced SiGe BiCMOS technology with 300 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{f}\textsubscript{T}$</tex-math> </inline-formula> and 500 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{f}\textsubscript{max}$</tex-math> </inline-formula> is presented. The monostatic front-end chip utilizes low-voltage low-power circuit-level design techniques to achieve measured 9-dBm transmitter (TX) output power and 27-dB receiver (RX) gain with a simulated 3.8-dB noise figure (NF) consuming a total of only 72 mW in continuous mode. The TRX chip is used to build a radar sensor, which is experimentally verified in an anechoic chamber. The low-power sensor achieves a 46-dB dynamic range and a ranging precision better than 3.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m measured with a static target at 1 m. Phase measurements using the low-power radar in the continuous-wave (CW) mode demonstrate that submillimeter movements can be tracked, and notably main vital parameters of a human can be determined accurately. Experimental results show that the performance of the proposed low-power TRX front-end chip is very competitive with designs in modern CMOS technologies.

Copula-based risk aggregation with trapped ion quantum computers

Copulas are mathematical tools for modeling joint probability distributions. In the past 60 years they have become an essential analysis tool on classical computers in various fields. The recent finding that copulas can be expressed as maximally entangled quantum states has revealed a promising approach to practical quantum advantages: performing tasks faster, requiring less memory, or, as we show, yielding better predictions. Studying the scalability of this quantum approach as both the precision and the number of modeled variables increase is crucial for its adoption in real-world applications. In this paper, we successfully apply a Quantum Circuit Born Machine (QCBM) based approach to modeling 3- and 4-variable copulas on trapped ion quantum computers. We study the training of QCBMs with different levels of precision and circuit design on a simulator and a state-of-the-art trapped ion quantum computer. We observe decreased training efficacy due to the increased complexity in parameter optimization as the models scale up. To address this challenge, we introduce an annealing-inspired strategy that dramatically improves the training results. In our end-to-end tests, various configurations of the quantum models make a comparable or better prediction in risk aggregation tasks than the standard classical models.

A Wireless Hysteretic Controlled Wireless Power Transfer System With Enhanced Efficiency and Dynamic Response for Bioimplants

This article presents a 6.78-MHz wireless power transfer (WPT) system with system-level wireless hysteretic control technique and circuit-level designs for both the receiver (RX) and transmitter (TX) chips. The proposed system achieves RX local voltage regulation and TX global power regulation without using any off-chip components (e.g., MCU, DAC, or various controllers and decoders) nor TX current sensing coils, which were required in previous works. A higher light-load efficiency and instant load-transient response are also achieved with the proposed wireless hysteretic control because of its operation principle. To further improve the efficiency, dynamic switch timing calibrations in the active rectifier in the RX are also designed, with resolved dual steady-state operation issues during the transitions between on-/off-delay compensations. Both the RX and TX chips have been fabricated in 180-nm standard CMOS. Measurement results show a 68.9% peak end-to-end (E2E) efficiency, with an up-to-20% enhancement at light-load conditions over a previous non-linearly controlled WPT system design. When compared to the other state-of-the-art designs, this work achieves an overall higher E2E efficiency, unnoticeable under-/over-shoots with instant recovery in load transients, and a lower system complexity with a higher level of integration without using any extra components other than the LCs to close the wireless loop.

Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators

The emerging non-volatile memory (eNVM) based mixed-signal Compute-in-Memory (CIM) accelerators are of great interest in today's AI accelerators design due to their high energy efficiency. Various CIM architectures and circuit-level designs have been proposed, showing superior hardware performance for deep neural network (DNN) acceleration. However, hardware-aware quantization strategies for CIM-based accelerators are not systematically explored. Since there are a variety of design options for neural network mapping on CIM systems while improper strategies may narrow the circuit-level design space and further limit the hardware performance, it is important to make a comprehensive early-stage design space exploration and find appropriate quantization/mapping strategies to achieve better hardware performance. In this paper, we provide a joint algorithm-hardware analysis and compare the system-level hardware performance for various design options, including quantization algorithms, data representation methods and analog-to-digital converter (ADC) configurations. This work aims to propose guidelines for choosing more hardware-friendly design options for chip architects. According to our evaluation results for CIFAR-10/100 and ImageNet classification, the properly chosen quantization approach and optimal mapping strategy (dynamic fixed-point quantization + 2’s complement representation/shifted unsigned INT representation + optimized precision ADC) could achieve ∼2 × energy efficiency and 1.2 ∼ 1.6 × throughput with 5%∼25% reduced area overhead, compared to naïve strategy (fixed-point quantization + differential pair number representation + full precision ADC).

A 17.7–19.2-GHz Receiver Front End With an Adaptive Analog Temperature- Compensation Scheme

This article presents an eight-element 17.7–19.2-GHz receiver front end with 1–2 concurrent beams in a 65-nm CMOS technology. Each output beam utilizes a temperature-compensation variable-gain amplifier (TC-VGA) to minimize the temperature-induced gain variation. The concept of the proposed TC-VGA and the realization of corresponding adaptive analog control are introduced in detail. The front-end architecture and circuit-level design to enable a flat wideband gain response, precise phase and amplitude control, low power consumption, and adaptive analog temperature compensation are presented. Wafer probing is conducted to measure the performance of the receiver front end. The measured gain-temperature coefficient is ±0.005 dB/°C from −15°C to 85 °C at 17.7–19.2 GHz, while the counterpart without temperature compensation is −0.1 dB/°C. The chip demonstrates a 28-dB power gain, a 26% 3-dB fractional bandwidth, a 3.2–4.1-dB noise figure (NF), and a −27.4-dBm input 1-dB gain compression point (IP <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {1\,dB}}$ </tex-math></inline-formula> ) for each element. In addition, each channel provides 7-bit phase-shifting resolution and 6-bit attenuation for a 15.75-dB gain range with a <1.5° root-mean-square (rms) phase error, and a < 0.22-dB rms amplitude error. The chip occupies <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.65\times2.77$ </tex-math></inline-formula> mm2 area with pads, equivalent to 1.61 mm2 per element (for two beams), and consumes 37.2 mW per element per beam. To the best of our knowledge, the receiver front end demonstrates the minimum gain variation with temperature among silicon RF-beamforming front ends.

Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

Bulk silicon Complementary Metal Oxide Semiconductor (CMOS) devices have distinct single event latch-up (SEL) problems in aerospace. Therefore, it is essential that CMOS devices are designed with appropriate circuit-level methods. Traditional resistor hardness satisfies the current aerospace trend of low cost, high performance, and miniaturization. Therefore conventional resistor hardness is often applied in circuit-level designs due to the reduction of latch-up current. In circuits containing a DC-DC buck converter, the resistor is connected to the back of the converter in the traditional method. However, the traditional method is unable to take devices out of the latch-up owing to the small resistance range. To solve this problem, the paper proposes an improved design for the resistor in front of the DC-DC buck converter. The proposed method enables the devices to exit the latch-up by increasing the resistance range according to the input characteristic of the DC-DC buck converter. The paper quantifies the range of the resistor through the parametric model containing the resistor and the DC-DC buck converter. Two CMOS devices are chosen for pulsed laser experiments, verifying that the proposed method increases the resistance ranges by 300% to 400% compared to the conventional method. It is also demonstrated that the proposed method exits the devices from latch-up within the resistor ranges. That is, the resistance ranges of 34 Ω~41 Ω and 51 Ω~56 Ω reduce the latch-up currents of the devices to below holding currents of 72.1 mA and 24.2 mA, respectively.

Guest Editorial: IEEE TC Special Issue On Software, Hardware and Applications for Neuromorphic Computing

The papers in this special section focus on software, hardware, and computer applications for neuromorphic computing. Inspired by biological neural systems, neuromorphic computing has drawn much attention for its great potential of achieving machine intelligence at extremely low energy dissipation. Bio-inspired computing models have been investigated for information encoding, sparse representation, event driven communication/computation, and online learning. This new computing paradigm triggered a recent wave of innovations in software and hardware architecture and emerging device technology, which consequently enabled many novel applications. This is an exemplar of research area where the application, computing model, architecture and circuit level design are tightly coupled to deliver unprecedented functionality and energy efficiency.

Effect of Temperature on Analog Memristor in Neuromorphic Computing

In this article, the influence of the temperature instability of resistive memory switching on potential neuromorphic computing applications is extensively studied using an Intel TaOx-based analog-type memristor as a synaptic weight modulator in a neural network. Evaluation results show that the effect of ambient temperature during training and interference can degrade the neural network’s accuracy due to inefficient weight updates and inevitable resistance or conductance drifting. Our results provide additional insights into device-level physical models and simple circuit-level design guidance for potential hardware-based neuromorphic computing applications.

Reservoir computing on a silicon platform with a ferroelectric field-effect transistor

Reservoir computing offers efficient processing of time-series data with exceptionally low training cost for real-time computing in edge devices where energy and hardware resources are limited. Here, we report reservoir computing hardware based on a ferroelectric field-effect transistor (FeFET) consisting of silicon and ferroelectric hafnium zirconium oxide. The rich dynamics originating from the ferroelectric polarization dynamics and polarization-charge coupling are the keys leading to the essential properties for reservoir computing: the short-term memory and high-dimensional nonlinear transform function. We demonstrate that an FeFET-based reservoir computing system can successfully solve computational tasks on time-series data processing including nonlinear time series prediction after training with simple regression. Due to the FeFET’s high feasibility of implementation on the silicon platform, the systems have flexibility in both device- and circuit-level designs, and have a high potential for on-chip integration with existing computing technologies towards the realization of advanced intelligent systems.

Crosstalk suppression for high-density traveling-wave MZM array based on static and dynamic combined analysis and circuit-level designs.

Electrical crosstalk severely degrades the performance of Mach-Zehnder modulator (MZM) array. However, conventional crosstalk suppression techniques incur losses of large amounts of chip area for signal isolation, which becomes a bottleneck of high-density electronic-photonic integrated circuit. In this paper, the electrical crosstalk of Traveling-Wave MZM array is originally analyzed with static and dynamic combined crosstalk coefficients. Circuit-level suppression techniques of differential dual-drive electrode schemes with tightly coupled electrode pairs and a virtual ground structure with full-matching termination circuit are investigated for noise-removing effects. Simulation results show that the dynamic electrical crosstalk coefficient between two adjacent modulators is reduced to below 1.5%, which is five times lower than the baseline. The electro-optical link measurements show that the BER is significantly reduced from 1E-3 to 1E-12 for multi-channel operation, which confirms the effectiveness of the crosstalk suppression techniques.

Shared reduced ordered binary decision diagram‐based thermal‐aware network synthesis

SummaryIn this work, a multi‐objective algorithm based on nondominated sorting genetic algorithm‐II (NSGA‐II) for thermal‐aware realization of a combinational logic network has been implemented. Input variable ordering of shared reduced ordered binary decision diagram (SROBDD) is done using NSGA‐II such that resulting combinational circuit generates low hotspots by suitable power density distribution. Simultaneous co‐optimization among area, power, and temperature is important in the higher levels of electronic circuit design to reduce the cooling cost. Using a multi‐objective algorithm (NSGA‐II), an effort is made to decrease the temperature by co‐optimization between the power density, area, and power simultaneously. Microelectronics Center of North Carolina (MCNC) benchmark circuits are tested using the proposed approach and an improvement of 13.65% in the silicon area and up to 10% in power dissipation, and 2.72% peak temperature reduction is reported in comparison to existing literature. HotSpot tool and Cadence Innovus are used to determine the peak temperature, actual silicon chip area, and power dissipation of algorithmic optimized solutions.

Write Asymmetry of Spin-Orbit Torque Memory Induced by in-Plane Magnetic Fields

Write asymmetry, the significantly different write current for high-to-low and low-to-high resistance switching because of natural stochastic behaviors of magnetization, is a fundamental issue in magnetic random-access memory (MRAM). For high-performance spin transfer torque (STT) MRAM, it can be eliminated by precisely controlling atomically thin magnetic multilayers or by introducing compensation techniques in circuit-level designs, while for spin-orbit torque (SOT) MRAM, it has not been addressed. Here we systematically investigated the write asymmetry of SOT-MRAM as a function of applied magnetic fields (H) and demonstrated that the write currents are intrinsically asymmetric due to different SOT efficiencies for high-to-low and low-to-high switching. Furthermore, we found that the SOT efficiency is very sensitive to the tilt angle between H and write current, which can be tuned through H to achieve symmetric SOT switching. These results provide an additional guideline for designing SOT devices and suggest that the write asymmetry can be eliminated by adjusting the introduced effective magnetic fields within a field-free SOT-MRAM architecture.

Diagnosis of Faults Induced by Radiation and Circuit-Level Design Mitigation Techniques: Experience from VCO and High-Speed Driver CMOS ICs Case Studies

In this paper, we discuss the diagnosis of particle-induced failures in harsh environments such as space and high-energy physics. To address these effects, simulation-before-test and simulation-after-test can be the key points in choosing which radiation hardening by design (RHBD) techniques can be implemented to mitigate or prevent failures. Despite the fact that total ionising dose (TID) has slow but destructive effects overtime on silicon devices, single-event effect (SEE) impulsively disrupts the typical operation of a circuit with temporary or permanent effects. The recently released SpaceFibre protocol drives the current requirements for space applications, and the future upgrade of the LHC experiment scheduled by CERN will require a redesign of the electronic front-end to sustain a radiation level up to the 1 Grad TID level. The effects that these two environments have on two different architectures for high-radiation and high-frequency data transmission are reported, and the efficiency of the mitigation techniques implemented, based on simulations and measurement tests, in the commercial 65 nm technology, are exploited.

A Survey on Low Power Design Approaches in Nanoscale Regime

Background: The increased demand for battery operated portable systems boost up the field of low power VLSI design. Integrated circuits are enhancing the performance of the systems in terms of lesser area requirement, higher functionality, and faster response at lower technology nodes. The applied power supply and the threshold voltage of the individual device are scaled down at lower technology node. Scaling of the threshold voltage of the devices raises the issue of leakage current. Objective: Leakage current should be made recessive with the continuous scaling of technology nodes. Methods: Various leakage current mitigation methods had been employed to reduce the leakage current at different abstraction levels. This review paper demonstrates the survey of systematic arrangement of device scaling, leakage power, its causes, and various methods to overcome the leakage current at circuit level design. Results: 3 input NAND (NAND3) gate is designed and simulated at 22 nm technology node on HSPICE tool and analyzed for comparison of different leakage reduction techniques. Conclusion: INDEP approach is the most effective approach to reduce the leakage current and to improve the reliability of the circuits followed by DTCMOS technique as compared to other available techniques.

Sleepy keeper style based Low Power VLSI Architecture of a Viterbi Decoder applying for the Wireless LAN Operation sustainability

Remarkable progress in the field of wireless communication has created a research interest for Viterbi decoder with long duration of battery life, low power dissipation and portabilty in the application. Such a low power Viterbi decoder is required in the area of high speed data transfer application like communication in the convolutional coding for error free inforamtion. This article propose two strategies to enhance the execution of the decoder by circuit level design of the Viterbi decoder utilizing a sleepy keeper method with additional leakage current control transistors, which decreases the leakage power dissipation. Then at the survivor memory unit the variation is done by the usage of modified resister exchange method with search space pruning. The Simulation of the work at the semiconductor level is done with 90 nm TSMC T-SPICE and SPICE netlist is used to create the simscape application of decoder which is applied in the Matlab Communication toolbox. The outcome of the system determines that the proposed sleepy keeper Viterbi Decoder in WLAN application has a reduction of 0.24 % with QPSK and 0.13 % reduction with QAM. Also, the SNR is found to be improved at a rate of 0.5db when compared with code based Viterbi decoder.

Sizing of multi-stage Op Amps by combining design equations with the gm/ID method

Analog integrated circuit design has as integral parts both analytical reasoning and numerical validation in the process from topology construction to sizing. Given a circuit topology, different circuit sizing results can be obtained from different processes of sizing inference. Sizing methods by simulation-based numerical searching have been a continuously studied subject. However, almost all approaches in this category require an overwhelming number of circuit simulations to arrive at an optimized sizing result. On the other hand, many published manual sizing methods by using the conventional device equations also require repeated SPICE simulations to correct the equation-based sizing results. This paper proposes a systematic gm/ID-based initial sizing method specifically customized for designing multiple-stage operational amplifiers (Op Amps). A main feature of the proposal is to use circuit-level design equations as constraints on the gm/ID table lookup method to substantially reduce the uncertainty in the sizing calculations. As a result, a significant amount of SPICE based correction work can be reduced to complete an initial sizing. The proposed sizing procedure includes a few regular sizing rules customized to the configuration of multi-stage Op Amps. We validate the proposed sizing method by application to several multi-stage Op Amp examples with a capacitive load or Miller compensation. Simulations have justified that the produced initial sizing results can achieve most of the prespecified design targets.