Circuit Imperfections Research Articles

GraphiQ: Quantum circuit design for photonic graph states

GraphiQ is a versatile open-source framework for designing photonic graph state generation schemes, with a particular emphasis on photon-emitter hybrid circuits. Built in Python, GraphiQ consists of a suite of design tools, including multiple simulation backends and optimization methods. The library supports scheme optimization in the presence of circuit imperfections, as well as user-defined optimization goals. Our framework thus represents a valuable tool for the development of practical schemes adhering to experimentally-relevant constraints. As graph states are a key resource for measurement-based quantum computing, all-photonic quantum repeaters, and robust quantum metrology, among others, we envision GraphiQ's broad impact for advancing quantum technologies.

A low‐power charge‐based integrate‐and‐fire circuit for binarized‐spiking neural network

SummaryThis paper presents a charge‐based integrate‐and‐fire (IF) circuit for in‐memory binary spiking neural networks (BSNNs). The proposed IF circuit can mimic both addition and subtraction operations that permit better incorporation with in‐memory XNOR‐based synapses to implement the BSNN processing core. To evaluate the proposed design, we have developed a framework that incorporates the circuit's imperfections effects into the system‐level simulation. The array circuits use 2T‐2J Spin‐Transfer‐Torque Magnetoresistive RAM (STT‐MRAM) based on a 65‐nm commercial CMOS and a fitted magnetic tunnel junction (MTJ). The system model has been described in Pytorch to best fit the extracted parameters from circuit levels, including the cover of device nonidealities and process variations. The simulation results show that the proposed design can achieve a performance of 5.10 fJ/synapse and reaches 82.01% classification accuracy for CIFAR‐10 under process variation.

A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications

This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC’s resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply.

A 60-GHz Polar Vector Modulator With Lookup Table-Based Calibration

A 60-GHz polar vector modulator with a lookup table (LUT)-based calibration for a variable gain active phase shifter is presented. It consists of an input buffer, an I/Q generator, a vector summing amplifier, and 6-bit phase/gain digital-to-analog converters (DACs). It is very difficult to obtain accurate gain and phase characteristics of a polar vector modulator due to circuit imperfections, such as I/Q imbalance, current mismatches of DACs, and impedance variations over polar vector states. Thus, calibrations are essential to have accurate gain and phase states. This letter introduces an LUT-based calibration method to map possible 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> states (5-bit gain and 8-bit phase) onto targeted polar states, which minimizes gain and phase errors drastically. The proposed phase shifter with a generated LUT shows an rms gain and phase errors of 0.13 dB and 0.8°, respectively, at the center frequency of 60 GHz. In addition, it has an rms gain and phase errors of <; 0.47 dB and <; 3.3° in a 9-GHz bandwidth of 55-64 GHz with 4-bit gain and 5-bit phase resolutions. It was fabricated using a 28-nm bulk CMOS process. The core area and power consumption are 0.41 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 15.4 mW, respectively.

A cost-effective nonlinear self-interference canceller in full-duplex direct-conversion transceivers

Cancellation of self-interference (SI) arising due to hardware nonidealities is a key issue in the design of mobile-scale full-duplex devices in future full-duplex (FD) communications. To efficiently address this issue in the baseband, we propose a cost-effective adaptive digital SI cancellation scheme for FD direct-conversion transceivers (DCTs) in the presence of major circuit imperfections, such as frequency-dependent I/Q imbalance, power amplifier (PA) distortion, thermal noise and quantization noise. This is achieved by employing a recent complex dual channel estimation (CDC) framework which offers low computational complexity in the widely nonlinear model fitting task which underpins this problem, to yield a dual channel nonlinear complex least-mean-square (DC-NCLMS) based SI canceller. For rigor, a unified theoretical evaluation is further performed to illustrate the second order performance optimality and low computation requirements of DC-NCLMS in both the transient and steady state stages. Further, for enhanced convergence, the proposed SI cancellation structure is equipped with an affine projection based scheme and a prewhitening procedure. Simulations in practical FD DCT settings, compliant with orthogonal frequency division multiplexing (OFDM)-based IEEE 802.11ac standard, support the findings.

Analysis of Circuit Noise and Non-Ideal Filtering Impact on Energy Detection Based Ultra-Low-Power Radios Performance

With the coming of age of the Internet of Things, demand on ultra-low power (ULP) radios will continue to boost tremendously. Circuit imperfections, especially in power hungry blocks, i.e., the local oscillators (LO) and band pass filters (BPFs), pose a real challenge for ULP radios designers considering their tight power budget. This brief presents an investigation on the effects of circuit non-idealities on the bit-error rate performance of on-off keying and Gaussian frequency-shift keying energy detection (ED)-based wakeup radios. In particular, this brief analyzes the impact of phase noise and frequency offset in the LO, BPFs bandwidth and roll-off, noise figure on ULP receivers’ performance. This brief contributes to the ongoing research in designing ULP wireless nodes by demonstrating the tradeoffs between these non-idealities and the receiver’s sensitivity level and selectivity and show some design guidelines for ED-based ULP radios.

Accidental phase modulation in second-order phase-locked loops

The phase-locked loop, essential element for phase synchronization in communications and control, is studied for several types of application. However, some cases urge for more accurate models, mainly regarding to the accidental phase modulation, an unavoidable phenomenon provoked by imperfections of circuits and transmission media, causing oscillations around the synchronous state, even when this state is reached. In this work, this problem is treated by distinguishing two different cases: jitter (high frequency) and wander (low frequency). In addition, the perturbation origins are modeled, dividing the problem into deterministic and random signal perturbations showing how they affect the equilibrium even with the loop operating in the pull-in range.

A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique

In this paper, we propose a low-jitter low-power digital multiplying delay-locked loop (MDLL) with a self-calibrated double reference injection scheme. To reduce jitter, the noisy edge of the oscillator is replaced by both the rising and falling edges of the clean reference, which results in 6-dB reduction in phase noise compared with a conventional single-edge injection MDLL. Reference spur caused by a frequency error of the oscillator, duty-cycle error of the reference, and circuit imperfection, such as offset and mismatch, is removed by employing three background feedback loops with a shared analog pulsewidth comparator. Implemented in 28-nm CMOS, the proposed digital MDLL generates 2.4-GHz clock and achieves a spur of −51.4 dBc and an rms jitter of 699 ${\mathrm{ fs}}_{\mathrm{ rms}}$ while consuming 1.5 mW from 1-V supply.

An Augmented Nonlinear LMS for Digital Self-Interference Cancellation in Full-Duplex Direct-Conversion Transceivers

In future full-duplex communications, the cancellation of self-interference (SI) arising from hardware non-idealities will play an important role in the design of mobile-scale devices. To this end, we introduce an optimal digital SI cancellation solution for shared-antenna-based direct-conversion transceivers. To establish that the underlying widely linear signal model is not adequate for strong transmit signals, the impact of various circuit imperfections, including power amplifier (PA) distortion, frequency-dependent I/Q imbalance, quantization noise and thermal noise, on the performance of the conventional augmented least mean square (LMS) based SI canceller, is analyzed. In order to achieve a sufficient signal-to-interference-plus-noise ratio (SINR) when the nonlinear SI components are not negligible, we propose an augmented nonlinear LMS based SI canceller for a joint cancellation of both the linear and nonlinear SI components by virtue of a widely nonlinear model fit. A rigorous mean and mean square performance evaluation is conducted to justify the performance advantages of the proposed scheme over the conventional augmented LMS solution. Simulations on orthogonal frequency division multiplexing (OFDM)-based wireless local area network (WLAN) standard compliant waveforms support the analysis.

Development of a Compact Acquisition System for Touch Location on a Conformable Monoport Distributed Sensor

A compact acquisition system developed for a flexible large area monoport tactile surface is presented in this paper. This sensor requires a single port connection and avoids complicated matrix acquisition system and multiplexing. The tactile surface is based on a coplanar transmission line printedd on a large area flexible substrate. Touching the waveguide generates a reflected signal. A harmonic analysis of this reflected signal at the line input port allows locating the touch event. A compact and low complexity acquisition system has been developed in order to demonstrate the principle and evaluate the feasibility of its integration on the sensor. Theoretical background, design and measurements on the overall sensor are exposed. The acquisition circuit imperfections have been demonstrated experimentally and correction methods have been proposed and implemented. Results are presented, and to assess the precision of the compact acquisition system, they are compared to reference measurements made with a Vector Network Analyzer

Wideband Multimode Monostatic Spiral Antenna STAR Subsystem

A wideband, multimode, and monostatic simultaneous transmit and receive (STAR) antenna subsystem is proposed. The configuration is composed of a single four-arm spiral and two analog circuit layers designed to maximize isolation between the transmitting (TX) and receiving (RX) channels. The first layer consists of two Butler matrix beamformer networks (BFNs); one for each TX and RX. The second layer integrates four, ideally phase-matched, circulators between the spiral arms and the BFNs. Theoretically, this configuration achieves infinite isolation irrespective of circulator’s quality. However, the BFN imbalances and the dissimilarities between the four circulators degrade the overall isolation. The operational principles are discussed under the ideal conditions and in the presence of circuit imperfections. For a four-arm spiral, the utilized BFN provides orthogonal modes 1, −1, 2, and 3, allowing STAR capability with multimode and diverse radiation patterns. The subsystem isolation and far-field performances are characterized experimentally and computationally for different modes of operation. A simple approach to achieve a dual-polarized STAR operation over narrower bandwidth with the proposed subsystem is also discussed. The multimode subsystem is demonstrated over 4:1 bandwidth with high isolation, VSWR < 2, consistent patterns, axial ratio < 3 dB over a wide field of view for the broadside modes (1, −1) and < 4.2 dB for other conical modes (2, 3).

Nonlinear self-interference cancellation in MIMO full-duplex transceivers under crosstalk

This paper presents a novel digital self-interference canceller for an inband multiple-input-multiple-output (MIMO) full-duplex radio. The signal model utilized by the canceller is capable of modeling the in-phase quadrature (IQ) imbalance, the nonlinearity of the transmitter power amplifier, and the crosstalk between the transmitters, thereby being the most comprehensive signal model presented thus far within the full-duplex literature. Furthermore, it is also shown to be valid for various different radio frequency (RF) cancellation solutions. In addition to this, a novel complexity reduction scheme for the digital canceller is also presented. It is based on the widely known principal component analysis, which is used to generate a transformation matrix for controlling the number of parameters in the canceller. Extensive waveform simulations are then carried out, and the obtained results confirm the high performance of the proposed digital canceller under various circuit imperfections. The complexity reduction scheme is also shown to be capable of removing up to 65% of the parameters in the digital canceller, thereby significantly reducing its computational requirements.

Effect of Magnetic Circuit Imperfections on the Field Performance of In-Vacuum Undulators for the Taiwan Photon Source

Effect of Magnetic Circuit Imperfections on the Field Performance of In-Vacuum Undulators for the Taiwan Photon Source

A Pre-Correction Algorithm for Broadcasting Transmitter

In a terrestrial broadcasting system, a power amplifier (PA) and mask filter (MF) are utilized to extend the service area of the broadcasting network, while suppressing unwanted out-of-band emissions. However, due to analog circuit imperfection, these devices inevitably cause significant linear and nonlinear distortions which may lead to spectral re-growth and the degradation of signal-to-noise ratio (SNR) performance. In order to compensate for these distortions, an adaptive pre-correction algorithm is proposed in this paper. Unlike conventional techniques, the proposed algorithm iteratively estimates the linear and nonlinear distortions using selective feedback loops. Computer simulations and laboratory prototype test results demonstrate that the proposed algorithm provides nearly an spectral gain of 8 dB near the edge of the channel bandwidth and an SNR improvement of 20 dB. Thus, it efficiently improves the dynamic range of the PA and MF.

Analysis and Modeling of Imperfections in Multi-Bit Per Stage Pipelined ADCs

In this paper, an approach to estimate signal to noise ratio (SNR) and effective number of bits (ENOB) in nonideal multi-bit stages of pipelined analog to digital converters (ADCs) is presented. The most significant error sources in multistage ADCs are the capacitor mismatch and the finite and imprecise gain of amplifier. Output voltage of each stage in pipelined ADC is modeled by an ideal and a nonideal output, where nonideal output is the error due to circuit imperfections in each stage. Using an appropriate model, the SNR and ENOB due to circuit nonidealities and in terms of standard deviation of random errors are calculated. Simulation results show the accuracy of the analytical proposed approach in estimation of SNR and ENOB in multi-bit per stage pipelined converters.

Digital Calibration of Amplifier Finite DC Gain and Gain Bandwidth in MASH Modulators

In this brief, a digital background calibration technique is proposed to improve the resolution of discrete-time multistage noise-shaping (MASH) sigma–delta $(\Sigma\Delta)$ modulators. The circuit imperfections of switched-capacitor discrete-time integrators (DTIs) degenerate the modulator output resolution, particularly in MASH structures, due to the quantization noise leakage of the early stages at the modulator output. An accumulative error model is proposed to define the errors induced by the limited dc gain and gain bandwidth (GBW) of DTIs as a function of their outputs. Compensating for these errors is possible through two steps, which are the DTI output digital approximation and adaptive filter correction. To identify the adaptive filter parameters, 1-b pseudorandom noise test signals are injected to the inputs of the DTIs. Then, the effect of these test signals is investigated by using a correlation-based least-mean-square algorithm. Simulation results confirm the effectiveness of the proposed method to eliminate the errors associated with the finite dc gain and GBW. Consequently, relaxed amplifiers with lower power consumption can be used.

Passive and Active Electrical Balance Duplexers

Electrical balance duplexing enables simultaneous transmit and receive from a single antenna; however, the transmit-to-receive isolation depends on the ability of the balancing algorithm to determine the correct balancing impedance. A novel balancing algorithm based on in situ characterization of the duplexer self-interference channel is proposed. The algorithm requires no a priori knowledge of the antenna impedance or hybrid junction characteristics and automatically compensates for circuit imperfections. A novel balancing network implementation that uses active signal injection is also proposed. A hardware prototype implementing the proposed balancing algorithm and combining passive and active balancing techniques has achieved 81.5-dB isolation over an 80-MHz bandwidth.

Interface Circuit for Vibration Energy Harvesting with Adjustable Bias Voltage

This paper presents a new interface circuit for electrostatic vibration energy harvesting with adjustable bias voltage. An electronic switch is used to modify the circuit configuration so that the harvested energy increases the voltage across a biasing capacitor. Decrease of this biasing capacitor voltage occurs naturally due to the circuit imperfections. Such a control of the bias voltage enables to adjust the amount of energy converted by the variable capacitor on each cycle. This feature can be used to optimize the mechanical damping induced by the energy conversion process in order to maximize the harvested power. Another feature of this interface circuit is that it is capable to get high bias voltage whatever the battery voltage with low energy loss.

Analysis of circuit imperfections in BosonSampling

BosonSampling is a problem where a quantum computer offers a provable speedup over classical computers. Its main feature is that it can be solved with current linear optics technology, without the need for a full quantum computer. In this work, we investigate whether an experimentally realistic BosonSampler can really solve BosonSampling without any fault-tolerance mechanism. More precisely, we study how the unavoidable errors linked to an imperfect calibration of the optical elements affect the final result of the computation. We show that the fidelity of each optical element must be at least 1 − O(1/n^2 ), where n refers to the number of single photons in the scheme. Such a requirement seems to be achievable with state-of-the-art equipment.

Analysis of circuit imperfections in bosonsampling

BOSONSAMPLING is a problem where a quantum computer offers a provable speedup over classical computers. Its main feature is that it can be solved with current linear optics technology, without the ...