Circuit Edit Research Articles

Review of: "focused ion beam technology has become very popular for performing special tasks such as cross-sectional imaging, preparation of nanodevice layers, nanopatterning of materials, and circuit editing"

Review of: "focused ion beam technology has become very popular for performing special tasks such as cross-sectional imaging, preparation of nanodevice layers, nanopatterning of materials, and circuit editing"

Review of: "preparation of nanodevice layers, nanopatterning of materials, and circuit editing"

Review of: "preparation of nanodevice layers, nanopatterning of materials, and circuit editing"

Detour-RS: Reroute Attack Vulnerability Assessment with Awareness of the Layout and Resource

Recent decades have witnessed a remarkable pace of innovation and performance improvements in integrated circuits (ICs), which have become indispensable in an array of critical applications ranging from military infrastructure to personal healthcare. Meanwhile, recent developments have brought physical security to the forefront of concern, particularly considering the valuable assets handled and stored within ICs. Among the various invasive attack vectors, micro-probing attacks have risen as a particularly menacing threat. These attacks leverage advanced focused ion beam (FIB) systems to enable post-silicon secret eavesdropping and circuit modifications with minimal traceability. As an evolved variant of micro-probing attacks, reroute attacks possess the ability to actively disable built-in shielding measures, granting access to the security-sensitive signals concealed beneath. To address and counter these emerging challenges, we introduce a layout-level framework known as Detour-RS. This framework is designed to automatically assess potential vulnerabilities, offering a systematic approach to identifying and mitigating exploitable weaknesses. Specifically, we employed a combination of linear and nonlinear programming-based approaches to identify the layout-aware attack costs in reroute attempts given specific target assets. The experimental results indicate that shielded designs outperform non-shielded structures against reroute attacks. Furthermore, among the two-layer shield configurations, the orthogonal layout exhibits better performance compared to the parallel arrangement. Furthermore, we explore both independent and dependent scenarios, where the latter accounts for potential interference among circuit edit locations. Notably, our results demonstrate a substantial near 50% increase in attack cost when employing the more realistic dependent estimation approach. In addition, we also propose time and gas consumption metrics to evaluate the resource consumption of the attackers, which provides a perspective for evaluating reroute attack efforts. We have collected the results for different categories of target assets and also the average resource consumption for each via, required during FIB reroute attack.

The EDFAS FA Technology Roadmap Die-Level Post-Isolation Domain Technical Summary

Abstract The Electronic Device Failure Analysis Society established the Die-Level Post-Isolation Domain Council to provide an overview of the upcoming challenges in this area and guide technique developments for next-generation analytical tools. This column summarizes the findings of the council in the areas of sample preparation, microscopy, nanoprobing, circuit editing, and scanning probe microscopy. It is a preview of the full roadmap document, which is in preparation to be released to the EDFAS community.

Nanoscale direct-write fabrication of superconducting devices for application in quantum technologies

In this Perspective article, we evaluate the current state of research on the use of focused electron and ion beams to directly fabricate nanoscale superconducting devices with application in quantum technologies. First, the article introduces the main superconducting devices and their fabrication by means of standard lithography techniques such as optical lithography and electron beam lithography. Then, focused ion beam patterning of superconductors through milling or irradiation is shown, as well as the growth of superconducting devices by means of focused electron and ion beam induced deposition. We suggest that the key benefits of these resist-free direct-growth techniques for quantum technologies include the ability to make electrical nanocontacts and circuit edit, fabrication of high-resolution superconducting resonators, creation of Josephson junctions and superconducting quantum interference device (SQUIDs) for on-tip sensors, patterning of high-Tc SQUIDs and other superconducting circuits, and the exploration of fluxtronics and topological superconductivity.

침투 공격 검출을 위한 비대칭 신호 스캐닝 기법

Design-For-Security (DFS) methodology is to protect integrated circuits from physical attacks, and that can be implemented by adding a security circuit to detect abnormal external access. Among the abnormal accesses called invasive attack, microprobing and FIB circuit editing are classified as the most powerful methods because they have direct access. Microprobing deliberately inject defects into the wire of circuit through probes, or reads and changes data. FIB circuit editing is methods of reconnecting or destroying circuits to neutralize security circuits or to access data. Previous DFS methodology have responded to the attacks by detecting arrival time asymmetry between the two signals or by comparing input/output data based on encrypted communication. This study conducted to reduce hardware overhead, and the proposed circuit detects the reflected signal asymmetry generated through probe or FIB circuit editing and detects the attacks through comparison. Since the proposed security circuit reduces the size and test cycle of the circuit compared to previous studies, the cost used for security can be reduced.

Failure analysis on capacitor failures using simple circuit edit passive voltage contrast method

Capacitor is one of the most basic passive components on any integrated circuit (IC) chip, such as memory, mixed-signal, or radiofrequency (RF) devices. They can be found in either the front-end or the back-end metallization of a chip. Failure analysis (FA) on such capacitors is increasingly challenging with rising complexities in semiconductor manufacturing demands. In our previous paper, a simple circuit edit passive voltage contrast (CE-PVC) technique was introduced and applied in failure analysis. This method uses a scanning electron microscope (SEM) and a platinum deposition module that is commonly found in most FA labs SEM. CE-PVC was used to alter passive voltage contrasts (PVC) through small but reversible circuit editing. In this paper, this technique is further expanded to resolve capacitor failures in both MIM capacitors and front-end polysilicon plate capacitors. This paper successfully demonstrated and resolved three cases of capacitor related failure in both MIM and polysilicon capacitors using CE-PVC technique.

Reliable endpoint technique on Si trenching for backside circuit edit

Circuit Edit (CE) techniques have been used for debug, characterization and prototyping. in the IC industry. CE jobs have become more complex to accomplish since the adaption of FinFET technology. Backside Si trenching as part of CE process is required to have the highest success rate because once punched through Si trench floor, the IC would lose functionality. Therefore, it needs reliable and quantitative end-pointing technique. The coaxial FIB column technology [1] allows to obtain optical image simultaneously, so the optical interference fringes can be used to estimate remaining of Si thickness, to monitor planarity of trench floor and to obtain trenching endpoint. We introduce reliable end-pointing technique on backside Si trenching.

A Physical Design Flow Against Front-Side Probing Attacks by Internal Shielding

Security-critical applications on integrated circuits (ICs) are threatened by probing attacks that extract sensitive information assisted with focused ion beam (FIB)-based circuit edit. Existing countermeasures, such as active shield, analog shield, and $t$ -private circuit, have proven to be inefficient and provide limited resistance against probing attacks without taking FIB capabilities into consideration. In this article, we propose an FIB-aware anti-probing physical design flow, which considers FIB capabilities and utilizes computer-aided design (CAD) tools, to automatically reduce the probing attack vulnerability of an IC’s security-critical nets with minimal extra design effort. The floor-planning and routing of the design are constrained by incorporating three new steps in the conventional physical design flow, so that security-critical nets are protected by internal shield nets with low overhead. Results show that the proposed technique can reduce the vulnerable area exposed to probing on security-critical nets by 100% with all critical nets fully protected for both advanced encryption standard (AES) and data encryption standard (DES) modules. The timing, area, and power overheads are less than 3% per module, which would be negligible in a system-on-chip (SoC) design.

Comparison between Focused Electron/Ion Beam-Induced Deposition at Room Temperature and under Cryogenic Conditions.

In this contribution, we compare the performance of Focused Electron Beam-induced Deposition (FEBID) and Focused Ion Beam-induced Deposition (FIBID) at room temperature and under cryogenic conditions (the prefix “Cryo” is used here for cryogenic). Under cryogenic conditions, the precursor material condensates on the substrate, forming a layer that is several nm thick. Its subsequent exposure to a focused electron or ion beam and posterior heating to 50 °C reveals the deposit. Due to the extremely low charge dose required, Cryo-FEBID and Cryo-FIBID are found to excel in terms of growth rate, which is typically a few hundred/thousand times higher than room-temperature deposition. Cryo-FIBID using the W(CO)6 precursor has demonstrated the growth of metallic deposits, with resistivity not far from the corresponding deposits grown at room temperature. This paves the way for its application in circuit edit and the fast and direct growth of micro/nano-electrical contacts with decreased ion damage. The last part of the contribution is dedicated to the comparison of these techniques with other charge-based lithography techniques in terms of the charge dose required and process complexity. The comparison indicates that Cryo-FIBID is very competitive and shows great potential for future lithography developments.

Faster and More Accurate Failure Analysis: Circuit Editing and Short Localization Performed at Same Tilt Angle using Multiple Techniques

Abstract A recent trend in semiconductor failure analysis involves combining the use of different tools and techniques in order to acquire more accurate data at a faster rate. This article describes a new workflow that combines FIB, GIS, and nanoprobing, all performed at the same FIB tilt position. It also provides two examples in which the workflow is used.

Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks

Invasive attacks, such as microprobing or focused-ion-beam (FIB) circuit editing are serious threats to security-related semiconductors. To ensure that there is security against invasive attacks, an effective countermeasure is to use a protective layer as a secure shield. Previous secure shield methods can be classified into one of two categories; detection circuits based on the delay difference or block ciphers. For the former, timing asymmetries caused by the capacitance of the probe are detected. The main drawback of this method is that it is highly vulnerable to chip editing by FIB equipment. FIB circuit editing can easily cripple the detection circuits of the secure shield. In contrast, the cryptographically secure shield based on the block cipher can provide strong protection against FIB circuit editing. However, it is prone to microprobing attacks because of its inability to detect the capacitance load of the probe. In this article, we propose a robust secure shield architecture against invasive attacks, including both probe attempts and the FIB circuit editing. The proposed method is based on the detection circuits with low hardware overhead and fast-analysis time and includes protection circuits to prevent information from being leaked.

Ultra-fast direct growth of metallic micro- and nano-structures by focused ion beam irradiation

An ultra-fast method to directly grow metallic micro- and nano-structures is introduced. It relies on a Focused Ion Beam (FIB) and a condensed layer of suitable precursor material formed on the substrate under cryogenic conditions. The technique implies cooling the substrate below the condensation temperature of the gaseous precursor material, subsequently irradiating with ions according to the wanted pattern, and posteriorly heating the substrate above the condensation temperature. Here, using W(CO)6 as the precursor material, a Ga+ FIB, and a substrate temperature of −100 °C, W-C metallic layers and nanowires with resolution down to 38 nm have been grown by Cryogenic Focused Ion Beam Induced Deposition (Cryo-FIBID). The most important advantages of Cryo-FIBID are the fast growth rate (about 600 times higher than conventional FIBID with the precursor material in gas phase) and the low ion irradiation dose required (∼50 μC/cm2), which gives rise to very low Ga concentrations in the grown material and in the substrate (≤0.2%). Electrical measurements indicate that W-C layers and nanowires grown by Cryo-FIBID exhibit metallic resistivity. These features pave the way for the use of Cryo-FIBID in various applications in micro- and nano-lithography such as circuit editing, photomask repair, hard masks, and the growth of nanowires and contacts. As a proof of concept, we show the use of Cryo-FIBID to grow metallic contacts on a Pt-C nanowire and investigate its transport properties. The contacts have been grown in less than one minute, which is considerably faster than the time needed to grow the same contacts with conventional FIBID, around 10 hours.

Xe Plasma vs. Gallium FIB Delayering

Abstract Liquid metal ion and plasma beam FIB systems are widely used in the semiconductor industry for TEM lamella preparation, circuit edit, and cross-sectional analysis. This article compares the deprocessing capability of a Ga FIB with that of a Xe plasma FIB. Both systems were used to delayer an Intel 14 nm processor from M8 down to the transistor contacts. As the images in the article show, a 100 × 100 µm window was opened by the Xe plasma FIB and a 20 × 20 µm window was opened with the Ga FIB. Related issues such as processing time, end point detection, and surface roughness are also discussed.

Probing Assessment Framework and Evaluation of Antiprobing Solutions

Probing attacks against integrated circuits has become a serious concern, especially for security-critical applications. With the help of modern circuit editing tools, an attacker could remove layers of materials and expose wires carrying sensitive on-chip assets, such as cryptographic keys and proprietary firmware, for probing. Most of the existing protection methods use an active shield that provides tamper-evident covers at the top-most metal layers to the circuitry below. However, they lack formal proofs of their effectiveness as some active shields have already been circumvented by hackers. In this paper, we investigate the problem of protection against front-side probing attacks and propose a framework to assess a design’s vulnerabilities against probing attacks. Metrics are developed to evaluate the resilience of designs to bypass an attack and reroute the attack, the two common techniques used to compromise an antiprobing mechanism. Exemplary assets from a system-on-chip layout are used to evaluate the proposed flow. The results show that long net and high layer wires are vulnerable to a probing attack equipped with high aspect ratio focused ion beam. Meanwhile, nets that occupy small area on the chip are probably compromised through rerouting shield wires. On the other hand, the multilayer internal orthogonal shield performs the best among common shield structures.

Defect Localization and Nanofabrication for Conductive Structures with Voltage Contrast in Helium Ion Microscopy.

As the dimensions of feature sizes in electronic devices decrease to nanoscale, an easy method for failure analysis and evaluation of processing steps is required. Gallium-focused ion beam (Ga-FIB) or scanning electron microscope is an efficient approach to detect voltage contrast for addressing failure analysis in semiconductor devices and processing. However, Ga-FIB may cause damage or implantation to the surface of the analyzed area, and its resolution is low. Helium ion microscopy (HIM) uses a light ion beam (helium or neon) for imaging and fabrication atnanoscale. With passive voltage contrast (PVC) in HIM images, the defect localization for failure of conductive structures can be rapidly and easily detected with a sufficient voltage contrast. Furthermore, a defect gap as narrow as sub-10 nm can be investigated with HIM imaging. PVC with HIM is an efficient method for defect localization at nanoscale with a minimal damage to the analyzed area. For circuit edit and failure analysis, it may be necessary to intentionally cut the conductive connection. In this circumstance, final results can be easily verified using PVC imaging with HIM. With XeF2 gas assistance, both helium and neon ion beams can be used to perform nanofabrication for metal disconnection. XeF2 gas plays an important role in preventing deposition of conductive materials on etching region and enhancing material removal rates to achieve electrically isolated structures. The etching rate with a neon ion beam is much faster than that of a helium ion beam. PVC in HIM images with controllable operation and dimensions using a helium ion beam with XeF2 gas assistance could also be used to localize a hidden defect for a single-location-defect situation. With neon ion beam irradiation on a defective location, PVC can be used to find the defect locations in the case of a series of defects.

High-brightness Cs focused ion beam from a cold-atomic-beam ion source

We present measurements of focal spot size and brightness in a focused ion beam system utilizing a laser-cooled atomic beam source of Cs ions. Spot sizes as small as (2.1 ± 0.2) nm (one standard deviation) and reduced brightness values as high as (2.4 ± 0.1) × 107 A m−2 Sr−1 eV−1 are observed with a 10 keV beam. This measured brightness is over 24 times higher than the highest brightness observed in a Ga liquid metal ion source. The behavior of brightness as a function of beam current and the dependence of effective source temperature on ionization energy are examined. The performance is seen to be consistent with earlier predictions. Demonstration of this source with very high brightness, producing a heavy ionic species such as Cs+, promises to allow significant improvements in resolution and throughput for such applications as next-generation circuit edit and nanoscale secondary ion mass spectrometry.

In-depth circuits edit analysis to reveal the implantation-related defect

IC functional failure is always a challenge for failure analysis engineers since it needs test pattern to access the defect location and electrically trigger it. Dynamic failure analysis is the only way to be used to do this kind of analysis. But it's time consuming and complex to employ dynamic analysis, so the success rate is lower and cycle time is longer. Static failure analysis is impossible to apply on these kinds of analysis since the test pattern and design information is needed. However, in this paper, the application of advanced FIB circuit edit (CE) was employed to isolate the suspected function block, and make it accessible to the DC bias. With static FA analysis, the defect location was successfully localized. Nanoprobing was employed on the further electrical analysis, and abnormal electrical performance was successfully observed. Combined with the device physics analysis, the suspected process was identified. Further PFA Wright etch was applied to visualize the defect which was a soft failure of Bipolar Junction Transistor (BJT) device. Failure mechanism was built up to explain the electrical and physical phenomena successfully.

Focused electron beam induced deposition of copper with high resolution and purity from aqueous solutions

Electron-beam induced deposition of high-purity copper nanostructures is desirable for nanoscale rapid prototyping, interconnection of chemically synthesized structures, and integrated circuit editing. However, metalorganic, gas-phase precursors for copper introduce high levels of carbon contamination. Here we demonstrate electron beam induced deposition of high-purity copper nanostructures from aqueous solutions of copper sulfate. The addition of sulfuric acid eliminates oxygen contamination from the deposit and produces a deposit with ∼95 at% copper. The addition of sodium dodecyl sulfate (SDS), Triton X-100, or polyethylene glycole (PEG) improves pattern resolution and controls deposit morphology but leads to slightly reduced purity. High resolution nested lines with a 100 nm pitch are obtained from CuSO4–H2SO4–SDS–H2O. Higher aspect ratios (∼1:1) with reduced line edge roughness and unintended deposition are obtained from CuSO4–H2SO4–PEG–H2O. Evidence for radiation-chemical deposition mechanisms was observed, including deposition efficiency as high as 1.4 primary electrons/Cu atom.

Current density profile characterization and analysis method for focused ion beam

The most critical challenge of circuit edit is the scaling of nano-machined features to the ever-decreasing minimum dimensions of VLSI process technologies. A key enabler for achieving small nano-machined feature sizes is a narrow focused ion beam (FIB) profile. Thus, the analysis of FIB profiles and their characteristic widths yields useful criteria of suitability for advanced circuit edit and other nano-machining applications. We present herein, the details of an analysis method of ion beam profiles based on amorphization traces produced by the beam when scanned over a [001] Si single crystal sample, with increasing doses. The amorphized region widths are measured by high resolution transmission electron microscopy. The analysis, relying on TRIM simulation, yields the transverse current density of a beam as a sum of two Gaussians and an exponential, and includes error estimates. Successful beam analyses of several modern FIB columns have been performed. We believe that this methodological approach to beam profile analysis may be used to advantage by FIB column manufacturers for characterization and development.