Circuit Carrier Research Articles

Titanium Carbide-Based Spatiotemporally Selectable-Activated Entropy-Driven DNA Nanoplatform for Amplified MicroRNA Imaging and Photothermal Therapy In Vivo.

Engineering an elaborate nanotheranostic platform that can achieve spatiotemporally selective microRNA (miRNA) imaging and imaging-guided therapy in time is critical for precise cancer diagnosis and efficient treatment, yet remains a challenge. Herein, we present an on-site-activatable nanotheranostic platform (Ti3C2-NEDR) that engineers a photothermal-activated entropy-driven strand displacement reaction (NEDR) module on a photothermal conversion module (Ti3C2) for achieving spatiotemporally controlled miRNA-21 imaging in vivo and imaging-guided photothermal therapy only by varying the power of the near-infrared (NIR) laser. The upstream NIR photothermal conversion module, Ti3C2, can act not only as a DNA circuit carrier to deliver the NEDR module but also as a photothermal agent to activate the downstream NEDR module in low-power NIR laser irradiation. Once the NEDR module is activated by the NIR laser, the entropy-driven strand displacement reaction can be innated by intracellular miRNA-21 to generate an amplified fluorescence signal for the spatiotemporally selective imaging of miRNA-21 in vivo. Thereafter, the imaging-guided in vivo photothermal therapy can be achieved in time only by switching to the high-power NIR laser. It is envisioned that this strategy of NIR light-activated spatiotemporally selective miRNA imaging and imaging-guided on-demand therapy may expand the nanotheranostic platform for precise cancer diagnosis and personalized therapy in time, providing a remarkable prospect in biomedical diagnosis and therapy.

Designed wrinkles for optical encryption and flexible integrated circuit carrier board

Patterns on polymers usually have different mechanical properties as those of the substrates, causing deformation or distortion and even detachment of the patterns from the polymer substrates. Herein, we present a wrinkling strategy, which utilizes photolithography to define the area of stress distribution by light-induced physical crosslinking of polymers and controls diffusion of residual solvent to redistribute the stress and then offers the same material for patterns as substrate by thermal polymerization, providing uniform wrinkles without worrying about force relaxation. The strategy allows the recording and hiding of up to eight switchable images in one place that can be read by the naked eye without crosstalk, applying the wrinkled polymer for optical anti-counterfeiting. The wrinkled polyimide film was also utilized to act as a substrate for the creation of fine copper circuit by a full-additive process. It generates flexible integrated circuit (IC) carrier board with copper wire density of 400% higher than that of the state-of-the-art in industry while fulfilling the standards for industrialization.

Mechanical qualification and microstructural analysis of alumina produced by material extrusion

Ceramics with their advantageous properties such as high thermal conductivity and electrical insulation are attractive to circuit carrier materials in electronics production. Using material extrusion (MEX-AM) for reasons of flexible manufacturing, this work produces green bodies with low surface roughness, which is necessary for subsequent metalizing to create 3D circuit carriers. Systematic variation of post-treatment profiles (debinding, sintering) leads to different microstructures and thus influences mechanical properties. A comprehensive mechanical qualification of ceramic samples produced with MEX-AM and post-treated differently has been carried out, in which tensile, compressive and flexural strength are analyzed. Using the Anderson Darling Test, it is shown that statistical methods standardized for conventional ceramics are applicable to additively manufactured specimens. A mean bending fracture strength comparable to conventional ceramics could be achieved combining a low heating rate profile for debinding with a two-step sintering (TSS) approach, which resulted in reduction of grain size, as SEM analysis confirmed.

55‐3: Invited Paper: Flexible Hybrid Electronics Using Display Infrastructure

Flexible and stretchable circuit is the key element for the upcoming flexible hybrid electronics in addition to high performance silicon based active devices and passive components. The circuitry and structure design of the circuit carrier have to be able to withstand the stress and tolerate biometric signal variation induced by external force. These circuit carriers can be fabricated by use of the flexible display technologies and facilities. In this study, we integrated ICs, passive components and sensors to form a system upon flexible/plastic circuit carrier. Bendable and/or stretchable smart textiles and patches were successful demonstrated with the functionality of electromyography (EMG) and electrocardiography (ECG).

Evaluating thermoset resin substrates for 3D mechatronic integrated devices and packaging

AbstractMiniaturization efforts and increasing demands regarding reliability of mechatronic systems require new materials and processes for the 3D mechatronic integrated devices (3D-MID) technology. Currently, in the area of 3D-MID mostly thermoplastic materials are in use in the industry, which are metallized using the LPKF-LDS® process. This paper is supposed to demonstrate the eligibility of thermoset resins as a new material class for 3D-MID applications and as a packaging option for silicon chips which are currently encapsulated using transfer molding of thermosets. The reliability of the conductor tracks made using a LDS-additive free process as well as the adhesion forces are investigated. Different laser parameters for structuring of two different substrate materials are compared. For reliability testing a thermal shock test is applied. Furthermore, the adhesion is tested using Hot-Pin-Pull testing. The conductor tracks surpass 2000 cycles thermo-mechanical load without showing strong deterioration of the track resistivity. The incorporated approach enables electrically reliable functionalization of packaged dummy chips including vias for connection to terminals on the chips. The results of the tested injection moldable thermoset resins are comparable to state-of-the-art 3D-MID thermoplastic substrates and thus, suited as circuit carrier material in electronic packaging.

The Critical Role of AlInP Window Design in III–V Rear-Emitter Solar Cells

This article highlights the critical role of window design on short circuit carrier collection in rear-emitter solar cells, as demonstrated through modeling and experiment using metamorphic GaAs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-y</sub> . Ultimately, if the window design is not carefully considered, surface depletion caused by Fermi level pinning at the window/air interface can extend into regions of active collection resulting in a large increase in effective window/base interface recombination velocity. This was experimentally shown here to result in a potential AM1.5G photocurrent loss of 8.1 mA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , or nearly 50%, based on integrated internal quantum efficiency (IQE). Associated IQE modeling and curve fitting indicate that the effective IRV at the GaAs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.75</sub> P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.25</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.64</sub> In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.36</sub> P interface is increased by multiple orders of magnitude when the window is not sufficiently thick or doped to fully contain the surface depletion to within the window layer. Calculations of the surface depletion depth as a function of doping and the surface Fermi pinning energy level provides insight into the fundamental limits of window thickness. This allows the estimation of the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.64</sub> In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.36</sub> P surface pinning level to be at least 1.25 eV below the conduction band edge, or in the bottom half of the bandgap.

Stackable SiC-Embedded Ceramic Packages for High-Voltage and High-Temperature Power Electronic Applications

Abstract This study encompasses the development of a high-voltage and high-temperature–capable package for power electronic applications based on the embedding of silicon carbide (SiC) semiconductor devices in the ceramic circuit carrier such as the direct bonded copper (DBC) substrate. By sealing semiconductor devices into DBC substrates, high temperature, high voltage, and high current capability as well as high corrosion resistance can be achieved compared with the state-of-the-art printed circuit board (PCB) embedding technology. The power devices are attached with high-temperature stable solder and sinter material and are surrounded by thermal conductive ceramic and high-temperature–capable potting materials that enable the complete package to operate at 250°C or above. Furthermore, the single embedded packages can be stacked together to multilevel DBC topologies with increased voltage blocking characteristics. Thus, current limits of the PCB and low-temperature cofired ceramic–based multilayer solutions are exceeded and will be confirmed in the course of this study. This package is designed to carry out the maximal performance of SiC and future wide bandgap devices. It is a promising solution not only for applications in harsh ambient environments such as aerospace and turbine, geothermal well logging, and downhole oil and gas wells but also for hybrid electric/electric vehicle and energy conversion.

Stackable SiC Embedded Ceramic Packages for High Voltage and High Temperature Power Electronics Applications

Abstract This paper encompasses the development of a high voltage and high temperature capable package for power electronic applications based on the embedding of SiC (silicon carbide) semiconductor devices in ceramic circuit carrier such as direct bonded copper (DBC) substrate. By sealing the semiconductor devices into DBC substrates, high temperature, high voltage and high current capability as well as high corrosion resistance can be achieved compared to state-of-the-art PCB (printed circuit board) embedding technology. The power devices are attached with high temperature stable solder and sinter material, and are surrounded by thermal conductive ceramic and high temperature capable potting materials that enable the complete package to operate at 250 °C or above. Furthermore, the single embedded packages can be stacked together to multilevel DBC topologies with increased voltage blocking characteristics. Thus, current limits of PCB and LTCC (low-temperature co-fired ceramic) based multilayer solutions are exceeded and will be confirmed in the course of this study. This package is designed to carry out the maximal performance of SiC and future WBG (wide band-gap) devices. It is a promising solution for applications in harsh ambient environment such as aerospace and turbine, geothermal well logging, down hole-well oil &amp; gas, but also applicable for HEV/EV (hybrid electric/electric vehicle) and energy conversion.

MPPT Algorithm Development for Laser Powered Surveillance Camera Power Supply Unit

Photovoltaics (PV) cells, modules which are semiconducting materials, convert light energy into electricity. Operation of a PV cell requires 3 basic features. When the light is absorbed it generate pairs of electron holes or excitons. An external circuit carrier opposite types of electrons irrespective of the source (sunlight or LASER light). The PV arrays have photovoltaic effect and the PV cells are defined as a device which has electrical characteristics: such as current, voltage and resistance. It varies when exposed to light, that the power output is depend on direct Laser-light. In this paper Laser-light to electricity by direct conversion with the use of PV cells and its concept of Band gap Energy, Series Resistance, Conversion Efficiency and Maximum Power Point Tracking (MPPT) methods [1].

Laser-assisted Selective Activation of Injection Molded Chip Packaging Devices with Thermoset Substrate Materials for Intelligent Connectivity Systems in Automobiles

The development of sensors, such as in the automotive sector is characterized by increasing miniaturization and variety. Higher integration of functions in electrical and mechanical applications is therefore a logical consequence for further development. In this connection especially technologies can persuade, enabling high design flexibility, combination of electrical and mechanical functions and embedding of further applications. Mechatronic integrated devices are a considerable solution combining mechanical and various electrical functions in an entire component together. Specifically, the ability for insert moulding of MEMS sensor chips and the ability to create circuit carrier in nearly any shape with selective traces and laser drilled vias suite for this production method.A particular focus is on the durability of very fine conductor tracks. With increasing miniaturization especially in high temperature and high voltage applications the typical thermoplastic based substrate materials with their thin chemical plated circuits, reach boundaries in the thermal and mechanical properties. The use of thermoset materials provides a new suitable alternative in this field. The cross-linked, molecular structured thermosets obtain high temperature resistance, combined with high dimensional stability. The thermal expansion is comparative low. With appropriate selection of compound fillers, aligned laser activation parameters and suitable circuit plating system a reliable CTE composition of all materials can be achieved. Thermosetting plastic compounds with laser-activatable additives are indeed in focus of current researches. However, laser-based method for the selective activation of thermosets is currently not available on the market. As a result, it is investigated into alternative laser assisted activation methods which do not require special additives in the substrate compound for electro chemical potential. Instead an assimilated chemical palladium activation is utilized subsequently. Of particular importance is distinct and selective activation with suitable laser parameters, as well as the following electroless chemical copper and additionally galvanic copper plating with appropriate surface quality for electronic surface mount and assembly technologies.Within the article, the research results will be presented, describing the method and giving an insight into the qualified process parameters for the laser and palladium activation, their correlations among themselves as well as the implications onto the following chemical and galvanic plating.

Developments for Copper-Graphite Composite Thermal Cores for PCBs for High-Reliability and High-Temperature RF Systems

Summary System designs that have only conduction cooling available, that must operate in harsh or challenging environments, present significant challenges to the system thermal engineer. A second thermal design challenge is continued miniaturization of semiconductor devices and increased functionality per square centimeter of semiconductor die, resulting in continued increases in device heat flux. Elimination of packaging materials allows more efficient heat transfer as thermal resistances from one material to another are reduced or designed out. When possible, concurrent elimination of package materials that have low bulk thermal conductivity and replacement with high thermal conductivity materials will improve heat transfer efficiency. Attachment of the resulting unpackaged semiconductor device can then be made directly to the circuit carrier; however, care must be taken regarding increases in potential for damage or failure due to mismatched coefficient of thermal expansion (CTE). Continuing reductions in die size that result in higher heat flux exacerbate this potential failure mechanism at the die-to-substrate level. This is further worsened in harsh environment (i.e., vibration, shock, high moisture, rapid power cycling) and/or high operating temperature conditions. For aerospace, military, geothermal, and other applications where increasingly high heat flux radio frequency (RF), microwave, and processor semiconductors are attached directly (with solders, silver sintering pastes, or other joining materials) to an organic or ceramic printed circuit card, efficient and rapid heat transfer becomes critical. These are frequently also applications where forced convection (air or liquid) may be unavailable to the system design engineer. One solution for thermal management design problems of this type has traditionally been the incorporation of one or more heavy copper layers within a complex multilayer printed circuit board (PCB). This solution, however, has come under increasing scrutiny in recent years due to concerns for weight (especially in airborne and space applications) and the potential for severe CTE mismatch between semiconductor die materials with relatively low thermal expansion values and the relatively very high value of copper. Therefore, development of CTE-matched alternative materials to replace a heavy copper layer has been a focus for development activities. A suitable selection must, however, have a bulk thermal conductivity that is as close to that of copper as is practicable. Recent developments of a copper-graphite composite material in sheet form that can be employed in standardized PCB manufacturing processes are described in this presentation.

Laser Beam Activation of CNT‐Filled Polymer Blends

Abstract3D‐Molded Interconnect Devices enable the placement of electronic circuits on three‐dimensional plastic components. The following article breaks new ground in order to add reasonably to existing 3D‐MID procedures. An essential aspect was the shortening of the process chain of the conventional MID procedures through laser‐direct structuring. Thus the metallising steps are no longer necessary and a 3D circuit carrier structure can be created directly on any plastic component. The research work focused on the space‐resolved modification of the electric conductivity of non‐conductive plastic components through a newly‐developed procedure of laser beam functionalisation. The principle is based on the application of multi‐phase polymer blends with matrix‐disperse phase structures in which carbon nanotubes are located. They cross‐link on the component surface through a partial laser activation and create a conductive area.

Advanced Thermal Management Solutions on PCBs for High Power Applications

With increasing power loss of electrical components, thermal performance of an assembled device becomes one of the most important quality factors in electronic packaging. Due to rapid advances in semiconductor technology, particularly in the field of high-power components, the temperature distribution inside of a component is a critical parameter of long-term reliability and must be carefully considered during the design phase. Two main drivers in the electronics industry are miniaturization and reliability. Whereas there is a continuous improvement concerning miniaturization of conductor tracks (i.e., lines and spaces have been reduced continuously over the past years), miniaturization of the circuit carrier itself, however, has mostly been limited to decreased layer counts and base material thickness. This can lead to significant component temperature increase and thence to accelerated system degradation. Enhancement of the system reliability is directly connected to an efficient thermal management on the PCB level. There are several approaches that can be used to address this issue: optimization of the board design, use of base materials with advanced thermal performance, and use of innovative buildup concepts. The paper provides a short overview about standard thermal solutions such as thick copper, thermal vias, plugged vias, or metal core based PCBs. Furthermore, attention will be focused on the development of copper filled thermal vias in thin board construction. In another approach, advanced thermal management solutions are presented at the board level, exploring different buildup concepts (e.g., cavities). Advantages of cavity solutions in the board are shown that not only decrease the thermal path leading from the high power component through the board to the heat sink, but also have an impact concerning the mechanical miniaturization of the entire system (reduction of z axis). Such buildups serve as a favorable packaging solution with promising thermal performance. Moreover, using thermal simulations different setups are compared and a deeper insight into the thermally relevant geometry and material parameters is provided, allowing production efforts to be reduced and to offering optimized designs and board buildups.

Direct Electronic Property Imaging of a Nanocrystal-Based Photovoltaic Device by Electron Beam-Induced Current via Scanning Electron Microscopy.

Scanning electron microscopy (SEM) electron beam-induced current (EBIC) studies were performed on the cross-section of a nanocrystal-based hybrid bulk heterojunction photovoltaic device. Using these techniques, the short circuit carrier collection efficiencies are mapped with a better than 100 nm resolution. Electronically deficient and proficient regions within the photoactive layer are determined. The results show that only a fraction of the CdSe nanorod:P3HT layer (P3HT = poly-3(hexylthiophene)) at the Al cathode interface shows primary collection of charged carriers, in which the photoactivity decreases exponentially away from the interface. The recombination losses of the photoactive layer away from this interface prove that the limiting factor of the device is the inability for electrons to percolate between nanoparticles; to alleviate this problem, an interparticle network that conducts the electrons from one nanorod to the next must be established. Furthermore, the EBIC technique applied to the nanocrystalline device used in this study is the first measurement of its kind and can be applied toward other similar architectures.

Arbitrarily Shaped 2.5D Circuits Using Stretchable Interconnections and Embedding in Thermoplastic Polymers

This contribution describes considerations and very preliminary results in the technology development of thermoplastically deformable electronics and sensor circuits, with the intention to eventually achieve the low-cost fabrication of 2.5D free-form rigid smart objects. The technology is based on the one for elastic circuits, developed and characterized before, which is using soft elastic polymers as materials for the circuit carrier. For 1-time deformable circuits the elastic carrier needs to be substituted by a thermoplastic material. An additional step of thermoforming is necessary after the entire circuit is fabricated on a flat surface, which is the normal industrial practice for circuit fabrication and which thus is also pursued here. First tests have been executed and simple circuits fabricated, using meandered Cu tracks as 1-time stretchable interconnects, PET-G as the thermoplastic carrier and SMD LEDs and zero-ohm resistors as circuit components.

Adhesion Enhancement of a Plated Copper Layer on an AlN Substrate Using a Chemical Grafting Process at Room Temperature

AlN substrates have been extensively used for heat dissipation, especially in high-power light-emitting diodes (LEDs). However, the AlN substrate is an electric insulator and thus needs to be metalized to serve as an electric circuit carrier and heat conductor for LED packaging. Herein, we propose a wet process that can be performed at room temperature to metallize AlN substrates. The wet metallization process involves copper electroless deposition and copper electroplating. The catalyst used for the copper electroless deposition was PdCl2, which was chemically grafted onto the AlN surface. The chemical grafting agent was 3-(2-aminoethylamino)propyltrimethoxysilane (APTMS). Before the chemical grafting step, an etching step in KOH solution was critical for good adhesion of the plated copper layer. The electroless copper depositions were catalyzed using chemically grafted Pd and a commercial Sn/Pd colloid. An adhesion comparison test of the plated copper layers was performed to demonstrate that the copper adhesion performance obtained with the chemically grafted Pd process was substantially better than that obtained with the commercial Sn/Pd colloid process.

SCB and SMI: two stretchable circuit technologies, based on standard printed circuit board processes

PurposeIn the past 15 years stretchable electronic circuits have emerged as a new technology in the domain of assembly, interconnections and sensor circuits and assembly technologies. In the meantime a wide variety of processes with the use of many different materials have been explored in this new field. The purpose of the current contribution is for the authors to present an approach for stretchable circuits which is inspired by conventional rigid and flexible printed circuit board (PCB) technology. Two variants of this technology are presented: stretchable circuit board (SCB) and stretchable mould interconnect (SMI).Design/methodology/approachSimilarly as in PCB 17 or 35 μm thick sheets of electrodeposited or rolled‐annealed Cu are structured to form the conductive tracks, and off‐the‐shelf, standard packaged, rigid components are assembled on the Cu contact pads using lead‐free solder materials and reflow processes. Stretchability is obtained by shaping the Cu tracks not as straight lines, like in normal PCB design, but as horseshoe shaped meanders. Instead of rigid or flexible board materials, elastic materials, predominantly PDMS (polydimethylsiloxane), are used to embed the conductors and the components, thus serving as circuit carrier. The authors include some mechanical modeling and design considerations, aimed at the optimization of the build‐up and combination of elastic, flexible and rigid materials towards minimal stress and maximum mechanical reliability in the structures. Furthermore, details on the two production processes are given, reliability findings are summarised, and a number of functional demonstrators, realized with the technologies, are described.FindingsKey conclusions of the work are that: supporting the metal meanders with a flexible carrier prior to embedding in an elastic substrate substantially increases the reliability under mechanical stress (cyclic uniaxial stretching) of the stretchable interconnect and the transition areas between rigid components and stretchable interconnects are the zones which are most sensitive to failure under mechanical stress. Careful design and technology implementation is necessary, providing a gradual transition from rigid to flexible to stretchable parts of the circuit.Originality/valueTechnologies for stretchable circuits, with the same level of similarity to standard PCB manufacturing and assembly, and thus with the same high potential for transfer to an industrial environment and for mass production, have not been shown before.

Printed circuit board technology inspired stretchable circuits

Abstract

Ceramic simplifies heat dissipation

LEDs suffer heat problems limiting their success as a light source. Much attention is given to the heatsink, less to the layers and barriers between LED and the heat dissipating surface. A change of concept and material allows significant gains in thermal management and reliability as well as a simplified system. Using ceramics as heatsink, circuit carrier and part of the product design needs some fresh thinking and the willingness to overcome traditional patterns. A simulation method based on Computational Fluid Dynamics supports thermal optimization and technical product design. Altair and Ceramtec explain the theoretical approach, the proof of concept and what and how improvement with ceramic heatsinks can be achieved. In this cases the OEM get various knowledge from the industry solutions.

Horizontal and vertical integration of product data for the design of moulded interconnect devices

In this paper, a methodology for the vertical and the horizontal integration of product data fitted to the needs of Moulded Interconnect Devices (3D-MID) is presented. For that purpose, an integrated product model based on STEP and the feature technology is developed. The application objects and schemas of STEP AP210 are used and extended to support the horizontal collaboration between electronic and mechanical design. Special attention is paid to the description of the three-dimensional structure of the circuit carrier and the circuit traces running within it and on its surface. In addition, the integrated product model also supports the hierarchical collaboration between upstream MID design and downstream simulation and manufacturing. Based on this product model, an effective communication between MID design in MIDCAD and the simulation of the injection moulding process in MOLDFLOW and manufacturing utilising MID-specific automatic placement equipment could be established.