Chip Pattern Research Articles

3D alignment of distant patterns with deep-subwavelength precision using metasurfaces

Measurement of the relative positions of two objects in three dimensions with sub-nanometer precision is essential to fundamental physics experiments and applications such as aligning multi-layer patterns of semiconductor chips. Existing methods, which rely on microscopic imaging and registration of distant patterns, lack the required accuracy and precision for the next generation of three-dimensional (3D) chips. Here we show that 3D misalignment between two distant objects can be measured using metasurface alignment marks, a laser, and a camera with sub-nanometer precision. Through simulations, we demonstrate that the shot noise-limited precisions of the lateral and axial misalignments between the marks are λ0/50, 000 and λ0/6, 300 (λ0: laser’s wavelength), respectively. With its high precision and simplicity, the technique enables the next generation of 3D-integrated optical and electronic chips and paves the way for developing cost-effective and compact sensors relying on sub-nanometer displacement measurements.

Visualization of CO2-oil vanishing interface to determine minimum miscibility pressure using microfluidics

The determination of the minimum miscibility pressure (MMP) assumes paramount significance in evaluating CO2 enhanced-oil recovery strategies. We created a microfluidic method for determining the MMP of CO2 and oil samples by integrating the direct observation of the vanishing interface and the analysis of fluorescence intensity exhibited by oil samples. A microfluidic chip is designed with closed-end microchannels to mimic the blind-end fractures which contributes to reveal the complete picture of residual oil mobilization during CO2 miscible flooding. The maximum deviation of 3.83 % and 5.47 % unequivocally attested to the accuracy of our method by comparing measured MMPs with those reported in the literature and theoretically calculated in this study. The effects of alkane types, temperature and oil compositions on MMP was investigated. The MMPs for binary synthetic oils (C8 + C14) increased non-linearly with contents of tetradecane and increased significantly at C14 > 75 vol%. MMPs of nine n-alkanes, seven binary synthetic oils, four ternary synthetic oils and kerosene were provided reliably as the unprecedented new data. Such unique advantages as in-situ visualization, chip pattern customizability, user-independence, and the clear criterion render this research highly valuable for determining the MMP as well as elucidating the microscopic mechanisms underlying residual oil mobilization.

Performance evaluation of surface texturing on carbide tool under minimum quantity lubrication turning of aluminium alloy Al6061 using canola oil

Turning operation is considered an important material removal process and its performance depends largely on the machining parameters. This study presents the analysis of the effect of surface texturing on tool during MQL turning of Aluminium alloy Al6061 using canola oil. Minimum quantity lubrication possesses the benefits of flood lubrication as well as dry machining. Canola oil used in this study possesses good lubrication properties and its kinematic viscosity is 41 mm2/s at 40 °C. Tool texturing is in growing trend in the manufacturing industry and it has gained the attention of many researchers in the past few years. In this study parallel textured pattern is used in which the grooves are perpendicular to chip flow direction. Average surface roughness (Ra) and tangential cutting forces (Ft) are the responses measured. Chip patterns are also examined under different conditions. It is concluded that high spindle speed of 160 m/min along with low feeding rate of 0.2 mm/rev with MQL system using textured tool generates better results for tangential cutting force as well as average surface roughness in contrast with other machining conditions.

Semi-Supervised Learning for Simultaneous Location Detection and Classification of Mixed-Type Defect Patterns in Wafer Bin Maps

Identifying the patterns of defective chips in wafer bin maps (WBMs) in semiconductor manufacturing processes is crucial because different defect patterns correspond to different root causes of process failures. Recently, mixed-type defect patterns (i.e., multiple defect patterns in a single wafer) have become increasingly common owing to the increased complexity of semiconductor manufacturing processes. Previous methods for classifying mixed-type defect patterns in WBMs focused on outputting only the class labels of the defect patterns and not their locations, although location information of the defect patterns is useful for tracking the root causes of failure and improving processes. Moreover, most previous methods used only labeled WBM data, although a larger quantity of unlabeled WBM data are more accessible because of the costly process of label annotation. Therefore, in this paper, we propose a semi-supervised learning method for classifying mixed-type defect patterns and detecting their locations simultaneously using both labeled and unlabeled WBM data. The proposed method extends a recent unsupervised object detection method called Attend-Infer-Repeat in a semi-supervised manner to perform object detection and classification simultaneously. The performance of the proposed method is verified using WBM datasets of different sizes. The results demonstrate the effectiveness of the proposed method for classification and location detection.

The Chip Formation Process When Cutting High-Speed Steels and Ti3SiC2 Ceramics

The paper presents the microstructural characterization of the chip roots in high-speed steels and ceramic Ti3SiC2. The process of chip formation and the obtaining of adequate samples were carried out using the quick-stop method. The tests were carried out during the milling process; the “quick stop” method was carried out in order to obtain samples of the chip roots. This method was developed in-house by the authors. The chip roots were microscopically studied by means of a light microscope (LM) and a scanning electron microscope (SEM). Before the actual analysis, preparation was performed based on the standard metallographic technique. The analysis of the high-speed steels samples showed that, for the used cutting conditions, a discontinuous chip with a built-up edge (BUE) was formed. During the processing of the Ti3SiC2 ceramic, a significant difference was manifested in the chip formation process and a powder-like chip was produced. After utilizing a careful cutting process, a chip pattern was observed, from which it is evident that chip breakage during ceramic processing occurs without prior plastic deformation. In addition, the cutting force Fc was also measured during the milling process of the high-speed steels and the ceramic, and it was correlated with the cutting speed, feed per tooth and depth of cut.

Direct-sequence spread spectrum time division multiple access with direct detection for latency optimized passive optical network

To improve low-latency support of passive optical networks, direct-sequence spread spectrum time division multiple access implements bi-directional byte-interleaved transmission by encoding each bit of a bi-polar sequence with orthogonal chip pattern. Consequently, guard-interval between consecutive up-link bytes can be removed and latency caused by multi-point control protocol interaction can be reduced. However, direct-sequence spread spectrum requires bi-polar signaling, which is not possible with direct detection and several solutions exist, such as, biased and differential transmission. In this work, we investigate the performance of direct-sequence spread spectrum time division multiple access with direct detection and also analyze both up-link and down-link situations. Experimental results of transmission over a 20 km dispersion uncompensated link show: The 31-bits direct-sequence reduces required received signal power to −12 dBm and the performance is limited by dark-current. With differential transmission in up-link direction, modified duo-binary has 5 dB better performance than PAM4. Also, in up-link direction, differential transmission has 3 dB better performance than biased transmission.

Investigation on tool wear and chip morphology in hard turning of EN 31 steel using AlTiN-PVD coated carbide cutting tool

Hard turning is a well-known machining technology by which a cylindrical job of hardness above 45 HRC is machined using a single point tool. In hard turning, higher tool wear is the main issue identified by the machinist. In the hard turning activity, tool wear is severely stimulus by cutting parameters, cutting tool materials, and cutting environment. The temperature evolved in the cutting process is the prime factor to accelerate the tool wear. However, there is a requirement to control the temperature intensity by selecting suitable input turning parameters and cutting environment. However, the current research emphasizes the selection of suitable input turning parameters and suitable coated carbide tools in hard turning of EN-31 bearing steel of hardness 56 HRC in conventional flood cooling. AlTiN-PVD coated carbide insert was used to execute the turnings tests using Taguchi L16 orthogonal array, and a detailed study on tool wear and chip pattern formation is investigated. AlTiN PVD coated carbide tool performed excellently in flood cooling as maximum tool wear was found as 0.065 mm which is very less for hard turning concerns. Also, long helical and ribbon chips patterns are identified in the entire investigation. Blue color chips are identified at 240 m/min of cutting speed which confirmed the generation of higher cutting temperature in course of cutting. The present findings can be suitable for the industries that are still using a conventional cooling method in the machining of heat-treated steels having hardness 45–69 HRC.

Development of an adaptive template for fast detection of lithographic patterns of light-emitting diode chips

With the expansion in light-emitting diode (LED) lighting market and technology, control of product quality has become the focus of LED development. To achieve high online production capacity, automated quality detection with object image has been employed for comparison using mostly the standard templates. However, the resulting poor fitting causes misjudgment of the detection system. This study proposes an adaptive template method to improve the system fitting, reduce the system misjudgment, and enhance the detection efficiency. The severely damaged LED chips were screened out based on their grayscale entropy indices and related coefficient indices, which enhanced the reliability of the adaptive template system and accelerated the overall system detection process. To overcome the displacement and scale changes of the lithographic patterns, the scale-invariant feature transform (SIFT) and Harris–Laplace methods were used for comparison. The scale-invariant feature transform (SIFT) and Harris–Laplace methods were used to search and compare the feature points of the chip patterns, with the aim to overcome the displacement and scale changes of the lithographic patterns and establish the adaptive template in real conditions. The fast correlation coefficient comparison method was compared with the adaptive template comparison method proposed in this study. The results showed that the detection accuracy of the new method was 98.36%, which is 15.79% more accurate than the fast correlation coefficient comparison method. In terms of time performance, the method proposed in this study took 0.08 s less to complete the partition defect template. Moreover, the average detection time per chip was reduced by another 1.4 s, which improved the efficiency by 30.43%. The adaptive template proposed in this study exclusively establish itself based on different lithographic patterns, thus improving the detection efficiency and accuracy of the LED industry, and raising its market competitiveness in the industry.

Dicing of composite substrate for thin film AlGaInP power LEDs by wet etching

In this paper, thin film AlGaInP LED chips with a 50 μm thick composite metal substrate (Copper-Invar-Copper; CIC) were obtained by the wet etching process. The pattern of the substrate was done by the backside of the AlGaInP LED/CIC. There was no delamination or cracking phenomenon of the LED epilayer which often occurs by laser or mechanical dicing. The chip area was 1140 μm × 1140 μm and the channel length was 360 μm. The structure of the CIC substrate was a sandwich structure and consisted of Cu as the top and bottom layers, with a thickness of 10 μm, respectively. The middle layer was Invar with a 30% to 70% ratio of Ni and Fe and a total thickness of 30 μm. The chip pattern was successfully obtained by the wet etching process. Concerning the device performance after etching, high-performance LED/CIC chips were obtained. They had a low leakage current, high output power and a low red shift phenomenon as operated at a high injected current. After the development and fabrication of the copper-based composite substrate for N-side up thin-film AlGaInP LED/CIC chips could be diced by wet etching. The superiority of wet etching process for the AlGaInP LED/CIC chips is over that of chips obtained by mechanical or laser dicing.

Assessments of Process Parameters on Cutting Force and Surface Roughness during Drilling of AA7075/TiB2 In Situ Composite.

Reinforced aluminum composites are the basic class of materials for aviation and transport industries. The machinability of these composites is still an issue due to the presence of hard fillers. The current research is aimed to investigate the drilling topographies of AA7075/TiB2 composites. The samples were prepared with 0, 3, 6, 9 and 12 wt.% of fillers and experiments were conducted by varying the cutting speed, feed, depth of cut and tool nose radius. The machining forces and surface topographies, the structure of the cutting tool and chip patterns were examined. The maximum cutting force was recorded upon increase in cutting speed because of thermal softening, loss of strength discontinuity and reduction of the built-up-edge. The increased plastic deformation with higher cutting speed resulted in the excess metal chip. In addition, the increase in cutting speed improved the surface roughness due to decrease in material movement. The cutting force was decreased upon high loading of TiB2 due to the deterioration of chips caused by fillers. Further introduction of TiB2 particles above 12 wt.% weakened the composite; however, due to the impact of the microcutting action of the fillers, the surface roughness was improved.

A Unified Defect Pattern Analysis of Wafer Maps Using Density-Based Clustering

For a yield enhancement in semiconductor manufacturing, it is necessary to analyze wafer maps since they contain information gathered during the manufacturing such as test results of each chip. Especially, spatial patterns of defective chips, e.g. zone, scratch, ring patterns, etc. presented on a wafer map provide valuable information on the potential causes of malfunctions in a fabrication process. Numerous automatic analysis methods have been developed for identifying such defect patterns. We propose a defect pattern analysis method based on density-based clustering (DBC), which consists of two steps: conducting a statistical test to detect wafer maps that contain abnormal defects and clustering the defect patterns. Specifically, we develop a new statistic based on the core points from DBC for the spatial randomness test, which requires much fewer examinations to identify abnormal wafer maps than the existing joint-count based statistics. With those core points, clustering of abnormal defects can be coherently performed in the subsequent clustering step. The main advantage of our method over previous automatic detection methods is that it performs both steps simultaneously based on the core points from DBC. The proposed method is evaluated on simulated and real wafer map datasets. Experimental results show that the proposed method identifies spatial dependence among defects as accurate as the existing methods, but with much less computational effort.

Experimental Study on Wear of Indexable Coated Blades as Applied to Cutting of PCrNi3MoVA Gun Steel Workpieces

In this paper, based on the theoretical study of tool wear and the systematic analysis of the main factors affecting the tool durability, four types of PVD and CVD-coated blades from three manufacturers were subjected to cutting tests using PCrNi3MoVA gun steel workpieces. The wear morphology, fatigue curves, and chip patterns of the tested blades were comparatively analyzed. The influence of the coating type on the tool durability was investigated using a scanning electron microscopy and energy dispersive spectroscopy. The results obtained strongly indicate that TiAlN coating deposited by the PVD technology has the best thermal stability, temperature oxidation resistance, and tool durability when cutting PCrNi3MoVA gun steel workpieces under semi-finishing conditions. The wear resistance of the other three types of blades was relatively lower due to less favorable coating compositions and structures. The study findings are instrumental in the substantiated selection of cutters for practical applications and provide a reference for the design optimization of indexable coated inserts.

Impact of artificial aging by thermocycling on edge chipping resistance and Martens hardness of different dental CAD-CAM restorative materials

Statement of problemThe selection of an appropriate restorative material based on fracture behavior is important for the marginal integrity of a dental restoration. For computer-aided design and computer-aided manufacturing (CAD-CAM) restorative materials, information regarding their edge chipping resistance is scarce. PurposeThe purpose of this in vitro study was to determine the edge chipping resistance (ECR) and Martens hardness (HM) of 6 different dental CAD-CAM restorative materials before and after thermocycling. Material and methodsFour composite resin materials including Brilliant Crios; Cerasmart, an experimental material; Lava Ultimate, a polymer-infiltrated ceramic-network (PICN) material (VITA Enamic), and a glass-ceramic control (IPS Empress CAD) were tested. The specimens were tested before and after thermocycling (30 000 times, 5 °C/55 °C). The ECR was measured for each material (n=25) and related to the point of loading and to the maximum chipping depth. HM was determined for each material (n=25). The Kruskal-Wallis and Mann-Whitney U tests were used to compare materials (α=.05). The impact of thermocycling was analyzed by using the Wilcoxon test (α=.05). The correlations between all parameters were calculated by using the Spearman-Rho test (α=.05). For fractographic analysis of chip patterns, chipped surfaces were analyzed by laser scanning microscopy. ResultsFor ECR and HM, the materials showed different values. ECRmd and ECRpl showed a positive correlation, but both showed a negative correlation to HM. The materials showed a different chip size (P<.001). Chip patterns revealed brittle material behavior in all cases. ConclusionsAll tested CAD-CAM materials behaved as brittle materials, but HM and ECR differed among the materials. The control glass-ceramic material showed the highest values for HM, followed by the PICN material. ECR values revealed the opposite order of materials, with the highest for composite resins. Artificial aging by thermocycling affected all dental CAD-CAM restorative materials. Especially for composite resin materials, ECR changed after aging.

Research on Chip Shear Angle and Built-Up Edge of Slow-Rate Machining EN C45 and EN 16MnCr5 Steels

One of the phenomena that accompanies metal cutting is extensive plastic deformation and fracture. The excess material is plastically deformed, fractured, and removed from the workpiece in the form of chips, the formation of which depends on the type of crack and their propagation. Even in case of the so-called ‘continuous’ chip formation there still has to be a fracture, as the cutting process involves the separation of a chip from the workpiece. Controlling the chip separation and its patterning in a suitable form is the most important problem of the current industrial processes, which should be highly automated to achieve maximal production efficiency. The article deals with the chip root evaluation of two EN C45 and EN 16MnCr5 steels, focusing on the shear angle measuring and built-up edge observation as important factors influencing the machining process, because a repeated formation and dislodgement of built-up edge unfavorably affects changes in the rake angle, causing fluctuation in cutting forces, and thus inducing vibration, which is harmful to the cutting tool. Consequently, this leads to surface finish deterioration. The planing was selected as a slow-rate machining operation, within which orthogonal and oblique cutting has been used for the comparative chips’ root study. The planned experiment was implemented at three levels (lower, basic, and upper) for the test preparation and the statistical method, and regression function was used for the data evaluation. The mutual connections among the four considered factors (cutting speed, cutting depth, tool cutting edge inclination, and rake angle) and investigated by the shear angle were plotted in the form of graphical dependencies. Finally, chips obtained from both steels types and within both cutting methods were systematically processed from the microscopic (chip root) and macroscopic (chip pattern) points of view.

A generalised uncertain decision tree for defect classification of multiple wafer maps

Classification of defect chip patterns is one of the most important tasks in semiconductor manufacturing process. During the final stage of the process just before release, engineers must manually classify and summarise information of defect chips from a number of wafers that can aid in diagnosing the root causes of failures. Traditionally, several learning algorithms have been developed to classify defect patterns on wafer maps. However, most of them focused on a single wafer bin map based on certain features. The objective of this study is to propose a novel approach to classify defect patterns on multiple wafer maps based on uncertain features. To classify distinct defect patterns described by uncertain features on multiple wafer maps, we propose a generalised uncertain decision tree model considering correlations between uncertain features. In addition, we propose an approach to extract uncertain features of multiple wafer maps from the critical fail bit test (FBT) map, defect shape, and location based on a spatial autocorrelation method. Experiments were conducted using real-life DRAM wafers provided by the semiconductor industry. Results show that the proposed approach is much better than any existing methods reported in the literature.

Chip pattern, burr and surface roughness in laser assisted micro milling of Ti6Al4V using micro ball end mill

Chip pattern, burr and surface roughness in laser assisted micro milling of Ti6Al4V using micro ball end mill

Clustering the Dominant Defective Patterns in Semiconductor Wafer Maps

Identifying defect patterns on wafers is crucial for understanding the root causes and for attributing such patterns to specific steps in the fabrication process. We propose in this paper a system called Dominant Defective Patterns Finder (DDPfinder) that clusters the patterns of defective chips on wafers based on their spatial dependence across wafer maps. Such clustering enables the identification of the dominant defect patterns. DDPfinder clusters chip defects based on how dominant are their spatial patterns across all wafer maps. A chip defect is considered dominant, if: 1) it has a systematic defect pattern arising from a specific assignable cause and 2) it displays spatial dependence across a larger number of wafer maps when compared with other defects. The spatial dependence of a chip defect is determined based on the contiguity ratio of the defect pattern across wafer maps. DDPfinder uses the dominant chip defects to serve as seeds for clustering the patterns of defective chips. This clustering procedure allows process engineers to prioritize their investigation of chip defects based on the dominance status of their clusters. It allows them to pay more attention to the ongoing manufacturing processes that caused the dominant defects. We evaluated the quality and performance of DDPfinder by comparing it experimentally with eight existing clustering models. Results showed marked improvement.

Paper chip-based colorimetric sensing assay for ultra-sensitive detection of residual kanamycin

Abstract Kanamycin, an aminoglycoside antibiotic, is extensively used to treat bacterial infections by interrupting protein synthesis. Overuse of kanamycin can lead to undesirable outcomes such as antibiotic resistance in humans. Thus, a precise detection strategy for monitoring kanamycin in animal-derived foods is strongly required. In this study, a novel paper chip-based label-free, simple sensing assay was developed. Gold nanoparticles for colorimetric assays were synthesized and characterized, and the paper chip pattern was printed using a wax printer. Through the colorimetric sensing assay on the paper chip, kanamycin was detected at levels as low as 3.35 nM (1.95 ppb) by the naked eye and using RGB color analysis techniques. In addition, this technique was also used for detection of kanamycin in milk samples. Compared to other detection systems, the use of the presented colorimetric detection system renders further analysis unnecessary. To our knowledge, this is the first report of colorimetric detection of kanamycin using the paper chip system. This simple, equipment-free, rapid, and ultra-sensitive paper chip-based kanamycin detection system provides superior field applicability for the monitoring of food and environmental safety.

Application of resist-profile-aware source optimization in 28 nm full chip optical proximity correction

As technology node shrinks, aggressive design rules for contact and other back end of line (BEOL) layers continue to drive the need for more effective full chip patterning optimization. Resist top loss is one of the major challenges for 28 nm and below technology nodes, which can lead to post-etch hotspots that are difficult to predict and eventually degrade the process window significantly. To tackle this problem, we used an advanced programmable illuminator (FlexRay) and Tachyon SMO (Source Mask Optimization) platform to make resistaware source optimization possible, and it is proved to greatly improve the imaging contrast, enhance focus and exposure latitude, and minimize resist top loss thus improving the yield.

Chip implementation of supervised neural network using single-transistor synapses

In this work, the newly developed neural chip applied in analog inputs for on-chip training and recognition is presented. We have designed the neural chip using single-transistor synapses which are capable of storing analog weights. The neural chip includes the interface circuit, power switches, analog synaptic array (7 × 4 synapses), and transresistance amplifiers (TR_AMPs) for on-chip training and recognition. Voice signals were acquired using analog signal processing and conditioning circuits for use in verifying the chip's pattern recognition functionality. The experimental results reveal that the synaptic weights of the neural network have adapted with training and have gradually converged to the targets afterwards. Upon system convergence, the recognition rates of the targeted speaker and the three others were evaluated. By using very small amount of synapses, as few as 28 synapses, the system's successful recognition rate for the targeted speaker is 93.5% for 200 tests; whereas, the rate for the other speakers is approximately 6.3% for 600 tests.