Chip Package Interaction Research Articles

Reduction of test effort. Looking for more acceleration for reliable components for automotive applications

Experience shows that chip package interaction is a dominant cause for failures of electronic components. Optimising the technology by applying the standard temperature cycling test to detect these failures is very time consuming and not any more compatible with today’s development cycles. Early failure indicators (preferable electrically measurable) could be the key element to reduce the test effort and to guarantee the performance in an application. From the package point of view there are three main drivers to be taken into consideration: The temperature, i.e. all degradation processes with an activation energy, temperature swings, which cause thermo-mechanical stress due to different CTE (coefficient of thermal expansion) of the variety of different materials used for the assembly, and temperature gradients, especially when active cycles are applied (switching of the device) can lead to metal reconstruction and plastic deformation, reducing lifetime of the component drastically. Knowledge of the weak areas allows choosing the best test in order to make the addressed failure mode observable in the shortest time. This paper provides a decision basis to speed up technology qualification by using TS (thermal shock) instead of TC (thermal cycling). Results will be shown for different die attach materials.

Chip-packaging interaction: a critical concern for Cu/low k packaging

Chip-packaging interaction is becoming a critical reliability issue for Cu/low k chips during package assembly. With the traditional TEOS interlevel dielectric being replaced by much weaker low k dielectrics, packaging induced interfacial delamination in low k interconnects has been widely observed, raising serious reliability concerns for Cu/low k chips. In a flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we will first review the experimental techniques for package thermal deformation measurement and interfacial fracture energy measurement for low k interfaces. Then 3D finite element analysis (FEA) based on a multilevel sub-modeling approach in combination with high-resolution Moiré interferometry is employed to examine the packaging effect on low k interconnect reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low k structures. Possible solutions and future study are discussed.

Packaging effects on reliability of cu/low-k interconnects

Chip-packaging interaction is becoming a critical reliability issue for Cu/low-k chips during assembly into a plastic flip-chip package. With the traditional TEOS interlevel dielectric being replaced by much weaker low-k dielectrics, packaging induced interfacial delamination in low-k interconnects has been widely observed, raising serious reliability concerns for Cu/low-k chips. In a flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low-k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we summarize experimental and modeling results from studies performed in our laboratory to investigate the chip-package interaction and its impact on low-k interconnect reliability. We first review the experimental techniques for measuring thermal deformation in a flip-chip package and interfacial fracture energy for low-k interfaces. Then results from three-dimensional finite element analysis (FEA) based on a multilevel submodeling approach in combination with high-resolution moire/spl acute/ interferometry to investigate the chip-package interaction for low-k interconnects are discussed. Packaging induced crack driving forces for relevant interfaces in Cu/low-k structures are deduced and compared with corresponding interfaces in Cu/TEOS and Al/TEOS structures to assess the effect of ILD on packaging reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low-k structures.