Chip-level Equalization Research Articles

Single Stream HSDPA MIMO 시스템에서 Precoding Weight 적용에 따른 LMMSE 수신기 성능 고찰

최근 들어 CDMA 기반 시스템에서 고속 데이터 서비스 지원을 위한 수신 성능 개선 방법의 하나로 칩 단위에서 동작하는 선형 최소 평균 제곱 오차(LMMSE: linear minimum mean-squared error) 수신기에 대한 연구가 활발히 진행되고 있다. 본 논문에서는 D-TxAA (dual stream transmit antenna array) 방식을 사용하는 단일 스트림(single stream) HSDPA MIMO 시스템에서 선부호화 계수(precoding weight) 적용이 LMMSE 수신기의 성능에 미치는 영향을 분석하고자 한다. 우선 D-TxAA 기반 2x2 다중입력 다중출력(MIMO: multiple input multiple output) 시스템에서 수신 신호 순간 파워 (instantaneous power)의 총 합이 최대가 되도록 하는 선부호화 계수 결정 방식을 유도할 것이다. 또한 선부호화 계수의 적용 지연 시간과 단말의 이동 속도가 LMMSE 수신기의 성능에 미치는 영향을 분석하고, 컴퓨터 모의실험을 통해 검증하고자 한다.

Efficient MIMO DS-UWB Downlink Chip-Level MMSE Equalization Using Subband Adaptive Interference Mitigation Techniques

An adaptive subband chip-level equalizer is investigated for downlink multiple-input-multiple-output (MIMO) direct-sequence (DS) ultrawideband (UWB) systems to cope with intersymbol interference (ISI) and multiple-access interference (MAI) in multipath fading channels. The subband decomposition technique with multiple analysis and synthesis filter banks (FBs) is employed to substantially improve the downlink reception of mobile-terminal (MT) receivers. This chip equalizer utilizes subband adaptive interference suppression techniques based on the minimum mean square error (MMSE) criterion. A reduced-complexity chip-level MMSE equalization scheme is proposed by making full use of the reduced-rank (RR) multistage matrix Wiener filter (MMWF) and the matrix conjugate gradient (MCG) architectures in subbands. Simulations are conducted to provide a comparative evaluation of the proposed subband chip equalizer with other existing full-band and subband chip equalizers.

Area-Efficient Prefilter Architecture for a CDMA Receiver

This brief proposes an area-efficient memory-based prefilter delay line structure. A prefilter-rake chip-level equalizer is used in a code-division multiple-access receiver to deal with multiple-access interference. A prefilter, which functions as an adaptive filter, has a sparsity property, where the number of taps with nonzero coefficients is much smaller than the number of whole taps. On the basis of the sparsity property, this brief shows how a memory device can be a reasonable candidate for a prefilter delay line. After proposing a scheme to reduce the area of the memory-based delay line, this brief shows that the proposed structure provides less area than a conventional register-based structure in typical industrial cases.

Chip Equalized Adaptive Rake Receiver for DS-CDMA UWB Systems

Conventional Rake receiver is a popular and effective method of utilizing the diversity offered by a DS-CDMA and multipath communication channel. The proposed Rake receiver is useful for suppression of multiple access interference in a multipath channel. The receiver works on chip level equalization on each Rake finger to cancel multi-access interference. Simulation results show that the convergence, diversity gain and bit error probability performance of the proposed receiver is much better than conventional adaptive Rake receiver in multipath channels.

Energy Aware Algorithm and Implementation of SDR Oriented HSDPA Chip Level Equalizer

The flexibility and programmability of SDR come at the expense of reduced efficiency and increased energy consumption. This is usually considered as the penalty of SDR. However, the flexibility and programmability have great potentials for improving the system-wide efficiency if they are properly exploited. In this paper, we present a HSDPA chip equalizer that is explicitly designed for SDR implementations. The first SDR-specific feature of our work is the multi-mode operation based on heterogeneous algorithms. The proposed equalizer combines an optimized LMS variant (with subspace-aware extension) and an optimized SRI-RLS algorithm based on QRD. Instead of always applying the powerful SRI-RLS algorithm, the equalizer switches to simple LMS-variant when possible. With negligible BER degradation, the multi-mode operation can reduce 60% of the cycle-count on TI TMS320C6713 for 3GPP case 4 with 16QAM modulation. The proposed equalizer framework also incorporates a generic, robust and efficient scheme for equalization-length adaptation. The length-adaptation scheme can make very fast run-time decision based on an efficient policy-template, which is optimized with large training set at design time. We test 14 representative channel profiles specified in ITU-R M.1225, 3GPP TR 25.943 and 3GPP TS 25.101. Comparing to worst-case based design the length-adaptation achieves more than 10× cycle-count reductions for ten of the cases.

Practical Chip-level Equalizers in HSDPA

High-speed downlink packet access (HSDPA) has been developed to upgrade the current WCDMA system in yerms of providing a higher data rate for mobile users. To ensure a downlink speed of up to 14Mbps, the HSDPA system has three main features: adaptive modulation and coding, a hybrid automatic repeat request, and fast scheduling. Because standard documents describe only the specifications of Node B, various kinds of HSDPA receivers cen be used with different architectures. An ordinary receiver generally has a rake architecture, though a rake receiver is not good at reducing multiple access interference (MAI). The performance of rake receiver is indispensably deteriorated when the number of mobile users in the system increases. Conversely, an equalizer can alleviate the MAI significantly at the expense of complexity and can therefore be an alternative solution for a rake receiver in a HSDPA system. In this paper, the performance of several equalizers of a HSDPA system is compared in terms of several implementation issues. The simulation results provide useful information about proper equalizers for different design purposes with respect to the performance and complexity trade-off.

Dual Antenna Receivers for High Data Rate Terminals

In this paper, dual antenna receiver architectures are studied including RAKE, chip-level linear equalizer, and their combination. The arithmetic complexity of single and dual antenna receiver methods is analyzed. Cost of such receivers when implemented with customized hardware or software on application-specific instruction set processors (ASIP) is estimated. The study shows that feasible dual antenna detection can be obtained with less than 70% additional costs. More flexible implementation supporting several standards can be obtained with software but it requires higher power consumption due to additional memory.

Performance of receive diversity and LMMSE chip equalization in WCDMA HSDPA network

More advanced receiver structures than the conventional single antenna Rake can be used to improve the signal-to-noise (SNR) ratios, which is especially beneficial in order to utilize the high bit rates provided by the HSDPA concept in Wideband Code Division Multiple Access (WCDMA) network. In WCDMA system, orthogonal Walsh---Hadamard sequences are used as channelization codes. In frequency-selective fading channels the orthogonality of channelization codes disappears and intra-cell multiple access interference (MAI) arises. In order to mitigate the effect of MAI, chip-level equalization has shown to be a simple and effective solution. The effectiveness of chip equalization, however, degrades at the cell borders where the inter-cell interference dominates rather than MAI. Dual antenna reception is a straight-forward solution to mitigate that performance drop. In this paper, we present an analysis of the expected gains of advanced receivers over conventional single antenna Rake receiver in realistic situations by using a dynamic WCDMA system-level tool. Considered advanced receivers include single and dual antenna Linear Minimum Mean Squared Error (LMMSE) chip-level equalizers and dual antenna Rake receiver. The network performance with advanced receivers is studied also from a more practical point of view by assuming that the penetration of advanced HSDPA terminal receivers is gradually increased in the network.

Towards multi-mode terminals

The increasing demand for wireless based services continues to grow with a multiplicity of standards developing. This is driving a need to develop integrated mobile terminals which have multi-mode capabilities, i.e., multiple communication systems which can coexist. The attention of this paper is focused on the coexistence of multiple communication systems via a simple hardware based structure with the algorithms and architectures developed within the framework of multi-mode terminals. The term multi-mode in this paper is limited to a set of standards and to a receiver that is expected to handle different systems with a low hardware complexity. Dedicated hardware is shared and reused by different systems. Existing specifications DAB, DVB-T, HIPERLAN-2 and UMTS are considered as examples in this paper, although the methodology could be applied to other systems. The systems considered can be classified into two categories: multi-carrier systems and single-carrier systems. This paper considers multi-mode terminals from both the algorithm and the architecture viewpoint, reducing receiver complexity by taking advantage of the commonalities among different specifications and receiver requirements. As an example, a joint channel estimation, chip-level frequency domain equalization and parallel interference cancellation structure for WCDMA is presented

Blind Chip-Level Equalizer for the Downlink of Cyclic-Prefix CDMA Systems

The authors present a chip-level blind frequency domain equalizer (FEQ) for the forward-link channel of a cyclic-prefix code division multiple access system. The FEQ coefficients are obtained without the need of training symbols or knowledge of channel state information. The coefficients are instead acquired by solving a constraint energy minimization problem involving the subspace spanned by the active and passive spreading codewords. They also prove that the random scrambling code sequences is required for the operation of the proposed equalization algorithm. Results from computer simulations are provided to verify the performance of the proposed FEQ

Blind Multiuser Detection for Long-Code CDMA Systems with Transmission-Induced Cyclostationarity

We consider blind channel identification and signal separation in long-code CDMA systems. First, by modeling the received signals as cyclostationary processes with modulation-induced cyclostationarity, long-code CDMA system is characterized using a time-invariant system model. Secondly, based on the time-invariant model, multistep linear prediction method is used to reduce the intersymbol interference introduced by multipath propagation, and channel estimation then follows by utilizing the nonconstant modulus precoding technique with or without the matrix-pencil approach. The channel estimation algorithm without the matrix-pencil approach relies on the Fourier transform, and requires additional constraint on the code sequences other than being nonconstant modulus. It is found that by introducing a random linear transform, the matrix-pencil approach can remove (with probability one) the extra constraint on the code sequences. Thirdly, after channel estimation, equalization is carried out using a cyclic Wiener filter. Finally, since chip-level equalization is performed, the proposed approach can readily be extended to multirate cases, either with multicode or variable spreading factor. Simulation results show that compared with the approach using the Fourier transform, the matrix-pencil-based approach can significantly improve the accuracy of channel estimation, therefore the overall system performance.

On the Equivalence of Linear MMSE Chip-Level Equalizer and Generalized RAKE

Several linear equalization schemes have been proposed for the downlink of direct-sequence code-division multiple-access systems. Previous numerical performance evaluation of such algorithms showed the equivalence of the linear minimum mean-square error chip-level equalizer and a slightly modified version of the generalized RAKE. In this letter, we establish this equivalence analytically.

MMSE equalization of downlink CDMA channel utilizing unused orthogonal spreading sequences

For the code division multiple access (CDMA) downlink channel, the chip-level equalization has been considered in this paper. There is no interference after despreading if all spreading codes are orthogonal, as in IS-95. However, it cannot be true for a frequency-selective fading channel. In this case, the chip-level equalization can be applied to restore the orthogonality. We investigate the chip-level equalization using finite impulse response (FIR) equalizers for the mobile station with multiple receive antennas. A blind approach and the minimum mean square error (MMSE) approach with code-multiplexed pilot are considered. A generalized MMSE equalization, which combines the MMSE and blind approaches together, is also investigated. It is shown that the generalized MMSE equalizer can effectively increase the number of samples to track the variation of channel and thereby performs better when the coherence time is small. In addition, we derive closed-form solutions of the blind, MMSE, and generalized MMSE equalizers for given channels.

Downlink Specific Linear Equalization for Frequency Selective CDMA Cellular Systems

We derive and compare several linear equalizers for the CDMA downlink under frequency selective multipath conditions: minimum mean-square error (MMSE), zero-forcing (ZF), and RAKE. MMSE and ZF equalizers are designed based on perfect knowledge of the channel. The downlink specific structure involves first inverting the multipath channel to restore the synchronous multi-user signal transmitted from the base-station at the chip-rate, and then correlating with the product of the desired user's channel code times the base-station specific scrambling code once per symbol to decode the symbols. ZF equalization restores orthogonality of the Walsh-Hadamard channel codes on the downlink but often suffers from noise gain because certain channel conditions (no common zeros) are not mets MMSE restores orthogonality only approximately but avoids excessive noise gain. We compare MMSE and ZF to the traditional matched filter (also known as the RAKE receiver). Our formulation generalizes for the multi-channel case as might be derived from multiple antennas and/or over-sampling with respect to the chip-rate. The optimal symbol-level MMSE equalizer is derived and slightly out-performs the chip-level but at greater computational cost. An MMSE soft hand-off receiver is derived and simulated. Average BER for a class of multi-path channels is presented under varying operating conditions of single-cell and edge-of-cell, coded and un-coded BPSK data symbols, and uncoded 16-QAM. These simulations indicate large performance gains compared to the RAKE receiver, especially when the cell is fully loaded with users. Bit error rate (BER) performance for the chip-level equalizers is well predicted by approximate SINR expressions and a Gaussian interference assumption.