Chip Communication Architectures Research Articles

Design of TTL Based Routing Algorithm on UTAR Network on Chip Communication Architecture

XY adaptive routing protocol is a routing protocol used on UTAR NoC communication architecture. This routing algorithm adapts shrotest-path first algorithm, which will forward will not be able to work optimally if the closest route no longer have enough bandwidth to continue the packet. Packet will be stored inside the router and forwarded to the nearest router when closest route has enough bandwidth. This paper suggest TTL based routing algorithm to resolve this issue. TTL based routing algorithm adapts XY adaptive routing protocol by adding several parameters on RTL UTAR NoC and additional bit in each packet sent by router. This additional bit and parameter will be used by TTL based algorithm as additional factors in choosing alternative routes inside the communication architecture. Use of TTL on TTL based routing different from use of TTL on communication network. Packets that carry TTL value that equal to Maximum TTL will be route using XY adaptive routing protocol. TTL based routing algorithm has shown better performance compared to XY adaptive routing on some of the experiment done using MSCL NoC Traffic Pattern Suite. This research also proves that TTL based routing algorithm cannot work optimally on small-scaled architecture.

FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC

Chip communication architectures become an important element that is critical to control when designing a complex MultiProcessor System-on-Chip (MPSoC). This led to the emergence of new interconnection architectures, like Network-on-Chip (NoC). NoCs have been proven to be a promising solution to the concerns of MPSoCs in terms of data parallelism. Field-Programmable Gate Arrays (FPGA) has some perceived challenges. Overcoming those challenges with the right prototyping solutions is easy and cost-effective leading to much faster time-to-market. In this paper, we present an FPGA based on rapid prototyping in hardware/software co-design and design evaluation of a mixed HW/SW MPSoC using a NoC. A case study of two-dimensional mesh NoC-based MPSoC architecture is presented with a validation environment. The synthesis and implementation results of the NoC-based MPSoC on a Virtex 5 ML 507 enable a reasonable frequency (151.5 MHz) and a resource usage rate equals to 58% (6,586 out of 11,200 slices used).

AN AREA AND POWER EFFICIENT ON CHIP COMMUNICATION ARCHITECTURES FOR IMAGE ENCRYPTION AND DECRYPTION

The design of new electronic systems is getting more complex as more functionality is integrated into these systems. To design complex system, a predictable design flow is needed. A soft processor based System-on-Chip (SoC) is often mentioned as the hardware platform to be used in modern electronics systems for fast prototyping on FPGA. In this paper, a novel area and power efficient on chip communication architectures has been proposed for image encryption and decryption using single soft processor(Micro Blaze). Proposed System On Chip explores On chip Communication architectures features to efficiently implement the application. The SoC offers scalability and guarantees on the timing behavior when communicating data between various processing and storage elements. Proposed SoC has been implemented on Spartan6 FPGA and evaluated at 83.33MHz. It has occupied only 19% of resources available on target FPGA , consumes very low power. The proposed on chip communication architectures compared with device utilization on FPGA and power consumed.

An optimised 3D topology for on-chip communications

Increasing system complexity, energy and device reliability, requirement of modular approach, structured layout, effective spatial reuse of resources, scalability and re-programmability have made network-on-chip (NoC) an obvious interconnection design alternative to the ubiquitous bus based on chip communication architecture in system-on-chip. Designing of a topology and its routing scheme plays a vital role in determining performance of any NoC architecture. In recent years, 3D stacked NoC architecture attracts added interest in NoC design as it offers improved performance and shorter global interconnect. In this paper, we have developed a partially, vertically interconnected 3D topology, namely 3D Recursive Network Topology (3D RNT) and prove that the topology has a Hamiltonian connectedness. We have developed deadlock-free routing algorithm for the 3D RNT topology. Also, we compare the performance of the 3D RNT with partially and fully connected 3D mesh topologies (3D PMT and 3D FMT) by conducting suitable experiments. The experiment results show that there is not much deviation in respect of the performance of the 3D RNT on comparing with 3D PMT and 3D FMT even though a number of vertical links are trimmed down to 75%, which is an encouraging outcome as far as design space is concerned.

DL(2m): A New Scalable Interconnection Network for System-on-Chip

With the feature size of semiconductor technology reducing and intellectual properties (IP) cores increasing, on chip communication architectures have a great influence on the performance and area of System-on-Chip(SoC) design. Network-on-Chip(NoC) has been proposed as a promising solution to complex SoC communication problems and has been widely accepted by academe and industry. Focusing on decreasing node degrees, reducing links and reusing router nodes, a regular NoC architecture, named Double-Loop(DL(2m)) interconnection network, is proposed. The topology of DL(2m) is simple, symmetric and scalable in architecture, and it is 3-regular plane graph with 4m nodes. The nodes of DL(2m) adopt Johnson coding scheme that can make the design of routing algorithms simple and efficient. The DL(2m) was compared with Ring and 2D Mesh by simulating and analysing, both under uniform load and under more realistic load assumptions in the several network size scenarios. The results show that the DL(2m) topology is a good trade-off between performance and cost, and it is a better NoC topology when there are not too many network nodes.

A Node Encoding of Torus Topology and Its Improved Routing Algorithm

With the feature size of semiconductor technology reducing and intellectual properties (IP) cores increasing, on chip communication architectures have a great influence on the performance and area of System-on-Chip (SoC) design. Network-on-Chip (NoC) has been proposed as a promising solution to complex SoC communication problems and has been widely accepted by academe and industry. This paper discusses how to choose suitable topology and node encoding scheme for NoC, and proposes a two-dimensional plane code based on Johnson Code by the combination of Torus topology with corresponding node encoding. The node encoding implies the relation among neighbouring nodes and the global information of routing. And it has good scalable characteristics. The two methods for code compressing are also presented to reduce the storage space of node address and increase the utilization rate of channel bandwidth. Utilizing the code, the improved X-Y routing is proposed, which is implemented with only three or six logic operations in middle nodes. The node structure is designed at the same time. The experimental results show combination of the proposed code with Torus topology can simplify the routing algorithm in the implementation of NoC, decrease silicon resource consumption and greatly improve communication performance.

A functional formalization of on chip communications

Abstract This paper presents a formal model and a systematic approach to the validation of communication architectures at a high level of abstraction. This model is described mathematically by a function, named GeNoC . The correctness of GeNoC is expressed as a theorem, which states that messages emitted on the architecture reach their expected destination without any modification of their content. The model identifies the key constituents common to all on chip communication architectures, and their essential properties from which the correctness theorem is deduced. Each constituent is represented by a function that has no explicit definition but is constrained to satisfy the essential properties. Thus, the validation of a particular architecture is reduced to the proof that its concrete definition satisfies the essential properties. In practice, the model has been defined in the logic of the ACL2 theorem proving system. We illustrate our approach on several architectures that constitute concrete instances of the generic GeNoC model. Some of these applications come from industrial designs, such as the AMBA AHB bus or the Octagon network from ST Microelectronics.