Checking Circuit Research Articles

Emulation of Optical Binary to Gray Code Converter and Even/Odd Parity Checker Circuit Using Electro-optic Effect-Based Directional Couplers

Emulation of Optical Binary to Gray Code Converter and Even/Odd Parity Checker Circuit Using Electro-optic Effect-Based Directional Couplers

Realization of 4-Bit Parity Checker Circuit Using XPM Technique-Based Phase-Shifted Fiber Bragg Grating Scheme

Realization of 4-Bit Parity Checker Circuit Using XPM Technique-Based Phase-Shifted Fiber Bragg Grating Scheme

Construction of logic circuit with modular molecular switching strategy based on DNA strand displacement

SummaryAt present, many DNA logic circuits have been successfully constructed. However, advanced complex DNA computing tasks with simple structure, fast response, and modularization still remain a huge challenge. In this paper, molecular switch circuits (MSCs) are constructed based on DNA strand displacement to improve above problems. At first, molecular switch is constructed, which is the basic element for building logic circuits. Next, the functions of AND, OR, Fan‐in, and Fan‐out are realized through switches cascading in series or parallel. Furthermore, switch canvas strategy is explored to obtain the shortest reaction path and highest output concentration for circuits. Finally, a novel strategy of integrating computing module using molecular switches is proposed. Here, we construct a half‐adder, half‐subtractor, and a 9‐bit parity checking circuits to verify its feasibility. Compared with the classical monorail and dual‐track logic circuits, the structure scale is reduced by more than two times, and the DNA strands are decreased by more than four times, which effectively reduces the circuit complexity and raises the reaction speed. The above results show that MSC strategy has a great potential to construct large‐scale DNA circuits and provides a development model for the scalability and modularity of biological computing.

Harnessing XPM effects in non-linear directional couplers for 4-bit gray code conversion and even parity verification

Abstract The all-optical switching phenomena in the non-linear directional coupler using cross-phase modulation (XPM) effect have been proposed. It is designed to generate an all-optical XOR functionality, considering the XOR logic gates as a basic module the design and analysis of an efficient all-optical 4-bit binary to gray code converter and 4-bit even parity checker circuit is proposed. The design methodology includes the switching of a weak continuous-wave (CW) signal, which is controlled by the combination of two controlled pump signals. In this paper, mathematical analysis of the coupled mode theory associated with optical directional couplers has been discussed. The switching characteristics of XPM effect based All-optical directional couplers have been examined for appropriate values of the controlled pump signals. Appropriate values of extinction ratio and corresponding controlled pump signal levels are investigated for an efficient generation of XOR logic gates. Further, the detailed analysis of layout generation and design aspects of All-optical 4-bit binary to gray code converter and 4-bit even parity checker circuits have been carried out. The proposed methodology is verified by the appropriate simulation results, which include the transmittivity, extinction ratio (Xratio) curve variation and dynamic time domain plot associated with proposed units.

QCA Based Design of Reversible Parity Generator and Parity Checker Circuits for Telecommunication

QCA Based Design of Reversible Parity Generator and Parity Checker Circuits for Telecommunication

Novel lockstep-based fault mitigation approach for SoCs with roll-back and roll-forward recovery

All-Programmable System-on-Chips (APSoCs) constitute a compelling option for employing applications in radiation environments thanks to their high-performance computing and power efficiency merits. Despite these advantages, APSoCs are sensitive to radiation like any other electronic device. Processors embedded in APSoCs, therefore, have to be adequately hardened against ionizing-radiation to make them a viable choice of design for harsh environments. This paper proposes a novel lockstep-based approach to harden the dual-core ARM Cortex-A9 processor in the Xilinx Zynq-7000 APSoC against radiation-induced soft errors by coupling it with a MicroBlaze TMR subsystem in the programmable logic (PL) layer of the Zynq. The proposed technique uses the concepts of checkpointing along with roll-back and roll-forward mechanisms at the software level, i.e. software redundancy, as well as processor replication and checker circuits at the hardware level (i.e. hardware redundancy). Results of fault injection experiments show that the proposed approach achieves high levels of protection against soft errors by mitigating around 98% of bit-flips injected into the register files of both ARM cores while keeping timing performance overhead as low as 25% if block and application sizes are adjusted appropriately. Furthermore, the incorporation of the roll-forward recovery operation in addition to the roll-back operation improves the Mean Workload between Failures (MWBF) of the system by up to ≈19% depending on the nature of the running application, since the application can proceed faster, in a scenario where a fault occurs, when treated with the roll-forward operation rather than roll-back operation. Thus, relatively more data can be processed before the next error occurs in the system.

On the self-testing (m,n)-code checker design

We propose an approach to a self-testing (m, n)-code checker design, based on subdividing the set of all code words into special subsets called segments. The checker circuit is constructed by using one- and two-output configurable logic blocks (CLB). Previously, in each output of a CLB, a function representing exactly one segment was implemented. In the proposed approach, at each CLBs output, it is possible to implement functions that represent several segments and to provide the self-testing property. It allows reducing the number of CLBs and simplifying the circuit of the checker.

Ultra high speed and novel design of power-aware CNFET based MCML 3-bit parity checker

MCML (MOS Current Mode Logic) based implementation producing fast response and compliment output at the same time gives an impetus to the researcher to replace Bulk CMOS. Moreover, tremendous challenges faced by bulk CMOS at channel lengths below 45 nm induces a need to strive for a technological replacement of silicon in years to come. This introduces a zest in designer's mind to look for competent and novel substances to overcome the shortcoming of existing silicon. The future technology should be capable to deliver fast response, low power operation, scalable to reduced dimensions, and strong towards process variations. Carbon nanotube based technology (CNFET) is one of the reliable and competent alternative because it has most of these desired features and similar operating principle as that of CMOS. And hence, this research article focuses on a relative evaluation of CMOS and CNFET version of 3 bit parity checker at 16-nm technology nodes. The CNFET based 3 bit parity checker is faster (9.75×), it offers improvement in power dissipation (11.93×), improvement in PDP (116.39×), improvement in EDP (1135.76×) compared to CMOS counterpart. Scaling down the device emerges with a challenge of variability, just as power, delay and area, variability also has an impact on performance of the circuit. Technology scaling has significant consequences such as wider variation. This research article also presents variability analysis, in terms of delay (tp) and power-delay product (PDP) for the proposed CNFET based MCML 3 bit Parity checker circuit. Extensive simulation using 16-nm technology node are carried out by loading two nominal copies of 'CNFET based MCML 3 bit Parity checker' (Circuit under Test) at either ends—input and output. This simulation framework supports the high level integration where stand alone operation has no application in the industry. The intent of this research is to investigate the circuit with minimal variability to propagation delay and PDP. The proposed ‘CNFET based MCML 3 bit parity checker’ exhibits improvement in delay (14.01×) and improvement in PDP (242.1×) variability as compared to CMOS counterpart. Thus, the CNFET based implementation emerges out as a robust circuit showing narrower spread in variability analysis against applied VDD.

Designing majority gate-based nanoscale two-dimensional two-dot one-electron parity generator and checker for nano-communication

At the present time, logic circuits design prototypes with quantum-dot cellular automata (QCA) have been comprehensively researched. The confines of orthodox CMOS technology induce to the breakthroughs of different technologies, one of which is QCA. Thoughtlessly, because of the deficiency of advance assembly support, QCA circuits frequently agonize from several sorts of manufacture shortcomings and variations and, hence, are error prone and defective. QCA technology is forming its aspect due to extreme effectiveness and rapidity with lesser area requirement. This study, a novel architecture of parity generator and checker, is proposed based on two-dot one-electron cells. Parity generator and checker assist in impeccable binary information communication from point to point. With the outlined parity generator and checker circuit, a nano-communication architecture is designed. The designed architecture is rationalized with a competently established standard mathematical operation based on Coulomb’s theory. All the outlined design contains a minimum number of cells, extent, and energy compared to existing four-dot two-electron QCA designs. The outlined designs comprehend minimum majority gate and latency. Besides, power depletion by the designs is measured and it is perceived that the total energy and power required to operate these designs are incredibly low.

Design of reversible parity generator and checker for the implementation of nano-communication systems in quantum-dot cellular automata

Complementary metal-oxide semiconductor (CMOS) technology may face so much problems in future due to the smaller size of transistors and increase in circuits’ volume and chips temperature. A new technology that can be a good alternative to CMOS circuits is quantum-dot cellular automata (QCA). These technologies have features such as a very low power consumption, high speed and small dimensions. In nano-communication system, error detection and correction in a receiver message are major factors. In addition, circuit reversibility in QCA helps designs a lot. In this research, generator and checker circuit of the reversible parity and eventually their nano-communication system are designed reversible using odd parity bit. The proposed circuits and the theoretical values are tested by QCADesigner 2.0.3 simulator to show the correct operation of the circuits. According to the simulation results, the proposed circuits compared with the previous structure improve delay by 90–75–35% in generator and checker structures of parity and their reversibility of nano-communication system, respectively. The proposed circuits are used in nano-transmitters and nano-receivers.

Ограничения на структуры компонентов полностью самопроверяемых схем встроенного контроля, синтезированных методом логического дополнения до равновесного кода «1 из 3»

Ограничения на структуры компонентов полностью самопроверяемых схем встроенного контроля, синтезированных методом логического дополнения до равновесного кода «1 из 3»

QCA Based Error Detection Circuit for Nano Communication Network

This paper outlines low power nano-scale circuit design for even parity generator, as well as, even parity checker circuit using quantum-dot cellular automata (QCA). The proposed even parity generator and even parity checker are achieved by using a new layout of XOR gate. This new XOR gate as a state-of-the-art is much denser and faster than the existing ones. The proposed parity generator has outshined the existing design by reducing the cell count as 10%, area as 5.66%, and latency by 12.5%. The proposed parity checker has also outshined the existing design with an improvement in cell count as 17.94% and in the area as 38.46% having a reduction in latency of 22.22%. The comparison proves that the circuits are denser and faster than the existing one. Nano communication architecture with the proposed circuits also demonstrates the efficiency of this design. Furthermore, the bit-error coverage by the proposed method is described. Besides, the defects in the circuits are explored to facilitate guide to proper implementation. The tests vectors are proposed to identify the defects in the designs and the defect coverage by those test vectors. The estimation of dissipated energy by the layouts establishes a very low energy dissipation nature of the designs. Different parameters like a logic gate, density, and latency are utilized to evaluate the proposed designs that confirm the faster processing speed at nano-scale.

Применение равновесного кода «1 из 5» для организации контроля комбинационных схем

Objective: To study specificities of “1-out of-5”equilibrium code application in the process of concurrent error detection of combinational logic circuits organization. Methods: Information and coding theories, as well as technical diagnostics of discrete systems were applied. Results: It was suggested to apply a “1-out of-5”equilibrium code in organizing of combinational circuits control by means of Boolean complement method, the tester of which has a simple structure and needs five testing patterns for its full check. The calculation method of Boolean complement functions was given; the former makes it possible to provide testability of a Boolean complement block and a tester within a checking circuit. The advantages of a “1-out of-5”equilibrium code application were presented, compared to the usage of other equilibrium codes with a shorter length of a code word for organization of combinational circuits’ check. Practical importance: The application of a “1-out of-5”equilibrium code for organization of combinational circuits’ check is promising for self-checking discrete automatic and calculating machines.

Towards designing efficient reversible binary code converters and a dual-rail checker for emerging nanocircuits

Reversible logic has attracted interest from many researchers in the area of quantum information science. Since there is no information loss in reversible logic, energy consumption is greatly reduced. However, realization of quantum equivalent circuits using cascading reversible gates is complex. Predominantly, this work targets implementation of quantum equivalent circuits using cascading reversible gates. In this work, novel code converters and a dual-rail checker with lower cost metrics such as gate count, garbage output, ancilla input, unit delay, logical calculation, and quantum cost are constructed. Several new reversible gates, namely BE (binary excess), BG-2 (binary Gray), GB-2 (Gray binary), and NG-R1 and NG-R2 (N $$=$$= new, R $$=$$= reversible), are designed and used to construct efficient code converter and dual-rail checker circuits. The main contribution of these novel circuits is the consideration of the gate-level schematics in the respective quantum equivalent circuit using our proposed algorithm. The performance results establish that the novel binary-coded decimal (BCD)-to-excess-3, binary-to-Gray, and dual-rail checker achieve improvement of 25 and 66.6 % in gate count and 44.4 % in quantum cost, respectively, compared with counterpart designs.

Modeling of all-optical even and odd parity generator circuits using metal-insulator-metal plasmonic waveguides

Plasmonic metal-insulator-metal (MIM) waveguides sustain excellent property of confining the surface plasmons up to a deep subwavelength scale. In this paper, linear and S-shaped MIM waveguides are cascaded together to design the model of Mach-Zehnder interferometer (MZI). Nonlinear material has been used for switching of light across its output ports. The structures of even and odd parity generators are projected by cascading the MZIs. Parity generator and checker circuit are used for error correction and detection in an optical communication system. Study and analysis of proposed designs are carried out by using the MATLAB simulation and finite-differencetime-domain (FDTD) method.

A parity checker circuit based on microelectromechanical resonator logic elements

Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro-resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.

Novel conservative reversible error control circuits based on molecular QCA

Quantum-dot cellular automata are a prominent part of the nanoscale regime. They use a quantum cellular based architecture which enables rapid information process with high device density. This paper targets the two kinds of novel error control circuits such as Hamming code, parity generator and checker. To design the HG-PP (HG = Hamming gate, PP = parity preserving), NG-PP (NG = new gate) are proposed for optimising the circuits. Based on the proposed gates and a few existing gates, the Hamming code and parity generator and checker circuits are constructed. The proposed gates have been framed and verified in QCA. The simulation outcomes signify that their framed circuits are faultless. In addition to verification, physical reversible is done. The reversible major metrics such as gate count, quantum cost, unit delay, and garbage outputs, uses best optimisation results compared to counterparts. They can be utilised as a low power error control circuit applied in future communication systems.

Reversible SSG Gate for Implementing Parity Checker Generator and Magnitude Comparator

The objective is to design a new reversible logic gate for implementing parity checker and generator logic circuit and a magnitude comparator logic circuit with minimum computational time. Power dissipation seems to be a major drawback in all conventional irreversible logic circuits. As a solution to this, circuits can be constructed using reversible logic gates. According to the principle of reversible logic a new 3X3 gate named as SSG gate has been proposed. SSG gate has the ability to realize the following logic functions like XOR, NOR, OR, NOT, XNOR, AND and COPY. The proposed work can be implemented on a floating point subtractor and multiplier design. The proposed SSG gate is used to test the functionality of a even parity checker and generator circuit and it is compared with the circuit realized using existing Feynman gate. The comparative result shows that SSG parity checker and generator consumes 0.67 seconds less time compared with the existing gate. The comparative result of the 2-bit magnitude comparator designed using proposed SSG gate and with the existing reversible gate1 and Gate2 shows that the computation time for SSG gate comparator is reduced by 0.33 seconds with the existing reversible gate1 and gate2.

Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication

Quantum-dot cellular automata (QCA) is an emerging area of research in reversible computing. It can be used to design nanoscale circuits. In nanocommunication, the detection and correction of errors in a received message is a major factor. Besides, device density and power dissipation are the key issues in the nanocommunication architecture. For the first time, QCA-based designs of the reversible low-power odd parity generator and odd parity checker using the Feynman gate have been achieved in this study. Using the proposed parity generator and parity checker circuit, a nanocommunication architecture is proposed. The detection of errors in the received message during transmission is also explored. The proposed QCA Feynman gate outshines the existing ones in terms of area, cell count, and delay. The quantum costs of the proposed conventional reversible circuits and their QCA layouts are calculated and compared, which establishes that the proposed QCA circuits have very low quantum cost compared to conventional designs. The energy dissipation by the layouts is estimated, which ensures the possibility of QCA nano-device serving as an alternative platform for the implementation of reversible circuits. The stability of the proposed circuits under thermal randomness is analyzed, showing the operational efficiency of the circuits. The simulation results of the proposed design are tested with theoretical values, showing the accuracy of the circuits. The proposed circuits can be used to design more complex low-power nanoscale lossless nanocommunication architecture such as nano-transmitters and nano-receivers.

Design of parity generator and checker circuit using electro-optic effect of Mach–Zehnder interferometers

Parity is an extra bit which is used to add in digital information to detect error at the receiver end. It can be even and odd parity. In case of even parity, the number of one's will be even included the parity and reverse in the case of odd parity. The circuit which is used to generate the parity at the transmitter side, called the parity generator and the circuit which is used to detect the parity at receiver side is called as parity checker. In this paper, an even and odd parity generator and checker circuits are designed using electro-optic effect inside lithium niobate based Mach–Zehnder Interferometers (MZIs). The MZIs structures collectively show powerful capability in switching an input optical signal to a desired output port from a collection of output ports. The paper constitutes a mathematical description of the proposed device and thereafter simulation using MATLAB. The study is verified using beam propagation method (BPM).