Check Node Processing Unit Research Articles

Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes

Non-binary low-density parity-check (NB-LDPC) codes outperform their binary counterparts in many cases. However, an NB-LDPC decoder usually requires excessive hardware resources and memory consumption. The trellis-based min-max decoding algorithm (TMMA), a well-known algorithm proposed in recent years, achieves good tradeoff between decoding performance and hardware complexity. Note that the check node processing unit (CNU) occupies the most hardware consumption. Based on the TMMA, many simplifications for the CNU have been developed with slight performance loss. The current TMMA with L truncations (L-TMMA) is promising for higher hardware efficiency than others. In this brief, based on the L-TMMA, we propose a new CNU design by incorporating algorithmic transformation and architectural optimization to further reduce the hardware complexity and thereby the critical path without any performance degradation. Synthesis results show that the proposed design achieves the lowest hardware consumption and the highest clock frequency with a small latency compared to the state-of-the-arts. Specifically, it saves more than 1/3 hardware resources compared with its original one.

A New PWL Approximation for the &quotSelf-Adjustable Offset Min-Sum&quot Decoding with a highly Reduced-Complexity

A new PieceWiseLinear (PWL) function is proposed for the decoding of the Low-Density-Parity-Check (LDPC) code with the Self Adjustable Offset Min-Sum (SAOMS) algorithm. Avoiding the use of the non-linear function f(x) = ln 1 + e j xj in the adjustable offset factor, this linear approximation greatly simplifies the hardware implementation with a little BER performance loss. The proposed solution is new, useful and is successfully tested on decoding regulars (504, 252) and (8000, 4000) LDPC codes. The corresponding Check Node Processing Unit (CNPU) have been designed, described and simulated using Very High Speed integrated circuits Hardware Description language(VHDL). The synthesis results were obtained using an Altera Quartus II software with cyclone II EP2CF896C6 as the target FPGA device. The designed CNPU is fully parallel and flexible to be used for different block length when a regulars (3, 6) LDPC codes are required.

A dual-rate LDPC decoder for china multimedia mobile broadcasting systems

This paper presents an efficient VLSI architecture and implementation for LDPC decoder used in China Multimedia Mobile Broadcasting (CMMB) systems. An area-efficient layered decoding architecture based on min-sum algorithm is incorporated in the design. A novel split-memory architecture is developed to efficiently handle the weight-2 submatrices that are rarely seen in conventional LDPC decoders. In addition, the check-node processing unit is highly optimized to minimize complexity and computing latency while facilitating a reconfigurable decoding core. The proposed design is implemented using 90 nm CMOS technology with the core area of approximately 4.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the standard supply voltage 1.0 V. The decoder can achieve the maximum throughput of 228 Mb/s for rate 1/2 and 342 Mb/s for rate 3/4 at 15 iterations of layered decoding. Therefore, it can be deployed on the CMMB mobile platform.

Configurable Multi-Rate Decoder Architecture for QC-LDPC Codes Based Broadband Broadcasting System

In this paper we present a Base-matrix based decoder architecture for multi-rate QC-LDPC codes proposed in broadband broadcasting system. We use the Modified Min-Sum Algorithm (MMSA) as the decoding algorithm in this architecture, which lowers the complexity of the LDPC decoder while keeping almost the same performance or even better. Based on this algorithm, we designed a novel check node processing unit to reduce the complexity of the decoder and facilitate the multiplex of the processing units. The decoder designed with hardware constraints is not only scalable in throughput, but also easily configurable to support different QC-LDPC codes flexible in code rate and code length.