Check Node Degree Research Articles

Optimised design and tree analysis of regularised variable‐node BATS codes

In this Letter, the authors investigate a modified encoding scheme of batched sparse (BATS) codes to improve the erasure floor performance. In the proposed regularised variable-node (RBATS) codes, variable-node degrees are regularised to maximise the minimum degree for transmission. The asymptotical decoding performance of RBATS codes is analysed by a tree-based analysis. Furthermore, they optimise check-node degree distribution of RBATS codes to decrease decoding overhead according to the decoding condition. It is demonstrated through simulation results that the optimised RBATS codes can not only lower the transmission overhead but also improve erasure floor performance compared with traditional BATS codes.

Adaptive Linear Programming Decoding of Nonbinary Linear Codes Over Prime Fields

In this work, we consider adaptive linear programming (ALP) decoding of linear codes over prime fields, i.e., the finite fields $\mathbb F_{p}$ of size $p$ where $p$ is a prime, when used over a $p$ -ary input memoryless channel. In particular, we provide a general construction of valid inequalities (using no auxiliary variables) for the codeword polytope (or the convex hull) of the so-called constant-weight embedding of a single parity-check (SPC) code over any prime field. The construction is based on sets of vectors, called building block classes , that are assembled to form the left-hand side of an inequality according to several rules. In the case of almost doubly-symmetric valid classes we prove that the resulting inequalities are all facet-defining , while we conjecture this to be true if and only if the class is valid and symmetric . Valid symmetric classes impose certain symmetry conditions on the elements of the vectors from the class, while valid doubly-symmetric classes impose further technical symmetry conditions. For $p=3$ , there is only a single valid symmetric class and we prove that the resulting inequalities together with the so-called simplex constraints give a complete and irredundant description of the codeword polytope of the embedded SPC code. For $p > 5$ , we show that there are additional facets beyond those from the proposed construction. As an example, for $p=7$ , we provide additional inequalities that all define facets of the embedded codeword polytope. The resulting overall set of linear (in)equalities is conjectured to be irredundant and complete. Such sets of linear (in)equalities have not appeared in the literature before, have a strong theoretical interest, and we use them to develop an efficient (relaxed) ALP decoder for general (non-SPC) linear codes over prime fields. The key ingredient is an efficient separation algorithm based on the principle of dynamic programming. Furthermore, we construct a decoder for linear codes over arbitrary fields $\mathbb F_{q}$ with $q =p^{m}$ and $m>1$ by a factor graph representation that reduces to several instances of the case $m=1$ , which results, in general, in a relaxation of the original decoding polytope. Finally, we present an efficient cut-generating algorithm to search for redundant parity-checks to further improve the performance towards maximum-likelihood decoding for short-to-medium block lengths. Numerical experiments confirm that our new decoder is very efficient compared to a static LP decoder for various field sizes, check-node degrees, and block lengths.

On the Design of Multi-Edge Type Low-Density Parity-Check Codes

Since multi-edge type low-density parity-check (MET-LDPC) codes were first proposed, the design of MET-LDPC codes has been extensively studied for various applications. However, the existing design rules assume that check node degrees are in the so-called concentrated form which enables one to conveniently find pairs of edge and node distributions satisfying the socket count equalities (SCEs). However, it in return makes the code design conducted in a limited search space, which may lead to a sub-optimal design. This paper proposes a novel design rule for MET-LDPC codes together with a scheme to efficiently sort out invalid distributions, i.e., ones not satisfying the SCEs, in the design process. The proposed design rule does not require check node degrees to be in the concentrated form and can find out optimized MET-LDPC codes without any restriction on the search space. Based on the proposed design rule, MET-LDPC codes are designed across a wide range of code rates on binary-erasure channel and binary-input additive-white Gaussian channel. The designed codes are compared with ones reported in the open literature, which confirms that MET-LDPC codes with the proposed design rule have better threshold performances regardless of channel and code rate even with sets of limited code parameters.

Design and analysis of LDPC codes for joint source‐channel decoding of two correlated sensors

This study is concerned with the design of ensembles of systematic low-density parity-check (LDPC) codes to increase the lifetime of wireless sensors by taking advantage of the inherent correlation between the transmitted data of the sensors. The authors consider two correlated sensors where the data is encoded independently at each sensor through a systematic LDPC encoder and sent over two independent channels. At the receiver, a joint source-channel decoder consisting of two component LDPC decoders is considered where the encoded bits at the output of each component decoder are used as the a priori information at the other decoder. The authors first perform asymptotic performance analysis using the concept of extrinsic information transfer (EXIT) charts. Then, the developed modified EXIT charts are used to design ensembles for different values of correlation. Our results show that as the average check node degree of the designed ensembles grow, the decoding thresholds corresponding to the designed ensembles approach the theoretical limit. Finite block-length performance evaluation indicates that for larger values of correlation, deploying the designed ensembles through the joint decoder can almost double the sensor's lifetime without increasing the complexity of the encoder.

LDPC Code Design for Distributed Storage: Balancing Repair Bandwidth, Reliability, and Storage Overhead

Distributed storage systems suffer from significant repair traffic generated due to the frequent storage node failures. This paper shows that properly designed low-density parity-check (LDPC) codes can substantially reduce the amount of required block downloads for repair thanks to the sparse nature of their factor graph representation. In particular, with a careful construction of the factor graph, both low repair-bandwidth and high reliability can be achieved for a given code rate. First, a formula for the average repair bandwidth of LDPC codes is developed. This formula is then used to establish that the minimum repair bandwidth can be achieved by forcing a regular check node degree in the factor graph. Moreover, it is shown that given a fixed code rate, the variable node degree should also be regular to yield minimum repair bandwidth, under some reasonable minimum variable node degree constraint. It is also shown that for a given repair-bandwidth requirement, LDPC codes can yield substantially higher reliability than the currently utilized Reed–Solomon codes. Our reliability analysis is based on a formulation of the general equation for the mean-time-to-data-loss (MTTDL) associated with LDPC codes. The formulation reveals that the stopping number is closely related to the MTTDL. It is further shown that LDPC codes can be designed such that a small loss of repair-bandwidth optimality may be traded for a large improvement in erasure-correction capability and thus the MTTDL.

Design of Rate-Compatible QC-IRA-d Codes Based on Gaussian Approximation Analysis and Graph Extension

In this paper, we propose a novel extending algorithm to design rate compatible (RC) QC-IRA-d codes through Tanner Graph extension. The structure of QC-IRA-d codes provides high efficiency and low complexity for graph extension. Thus, in the proposed method, there are three features: (1) close relation between the extended parts and original parity check matrix; (2) larger length of introduced cycles; (3) balanced check node degree. All of them guarantee good performance of the designed RC family codes. Simulation results show that the graph extension method outperforms existed algorithms from 0.05 to 0.47 dB for different rate codes.

Improved online fountain codes based on shaping for left degree distribution

In this paper, an improved encoding scheme for online fountain codes is proposed with the joint optimization of variable node degree and check node degree is proposed. The coding scheme can be divided into the build-up phase and the completion phase. In the build-up phase, left degree distribution is exploited to guarantee optimal performance phase by modifying the traditional coding scheme of choosing input symbols uniformly at random. A memory-based selecting of the source symbols is employed to decrease the number of connected components, which can thus produce the dimension increasement of the linear subspace of a decoding graph constructed in the build-up phase. The upper bound on coding overhead is also derived from the analysis of random graph theory. Compared with conventional online fountain codes, it can be seen from the simulation results that the proposed scheme can provide significant performance improvement with respect to both coding overhead and feedback cost. Moreover, the lower encoding/decoding complexities may make the proposed scheme more practical in energy-constrained applications such as distributed storage.

Variable LLR Scaling in Min-Sum Decoding for Irregular LDPC Codes

Min-sum decoding is a low-complexity alternative to the so-called belief propagation and consists in simplification of the nonlinear operation on the log likelihood ratios (LLRs) in the check nodes. The resulting suboptimality may be tempered via appropriate scaling of the LLRs, e.g., the fixed optimal scaling in the normalized min-sum algorithm, and variable scaling algorithms gradually appearing in the literature. However, up to now, none of the papers studied variable scaling both as per iteration and as per different check node degree, due to the prohibitive complexity of multioptimization over space of too many parameters. In this paper, we propose a generalized mutual information (GMI) of LLRs as the criterion to search for the scaling factors for different check node degrees in every iteration in a 1-D thus low-complexity manner. This approach is first analyzed via density evolution, and in addition can be extended to practical LLRs based formulas via Monte Carlo tools to cope with the mismatch issue. Bit error rate simulation results on two low-density parity-check codes show that our proposed GMI metrics have a noticeable gain over the variable scaling schemes that appeared in the literature.

Performance Analysis and Improvement of LT Codes over AWGN Channels

LT codes, the first universal erasure-correcting codes, have near-optimal performance over binary erasure channels for any erasure probability, but exhibit high bit error rate and error floor over the noisy channels. This paper investigated the performance of LT codes over the additive white Gaussian noise channels. We designed the systematic LT codes through reconstructing the bipartite graph and proposed a modification of the encoding scheme for the systematic LT codes to eliminate the cycles in generator matrix. With the proposed encoding scheme, the systematic LT codes are almost left-regular. Consequently, two types of the systematic LT codes, left-regular right-regular and left-regular right-irregular LT codes, were considered from the perspective of bit error rate. For the left-regular right-irregular LT code, we modified the degree distributions and proposed three kinds of check-node degree distributions. And then we analyzed the performance of the above-mentioned systematic LT codes with the proposed encoding scheme and different degree distributions. Simulations results show that the performance of the systematic LT codes with the proposed encoding scheme outperforms that of the conventional LT codes and the bit error rate of the systematic LT codes declines more than one order compared with that of the conventional LT codes. Finally, we proposed a class of the concatenated code, which serially concatenate the conventional LT codes with the systematic LT codes adopting the proposed encoding scheme. The performance of the proposed concatenated code was evaluated through simulations.

Gallager B LDPC Decoder with Transient and Permanent Errors

This paper studies the performance of a noisy Gallager B decoder for regular LDPC codes. We assume that the noisy decoder is subject to both transient processor errors and permanent memory errors. We permit different error rates at different functional components. In addition, for the sake of generality, we allow asymmetry in the permanent error rates of component outputs, and thus we model error propagation in the decoder via a suitable asymmetric channel. We then develop a density evolution-type analysis on this asymmetric channel. The recursive expression for the bit error probability is derived as a function of the code parameters (node degrees), codeword weight, transmission error rate, and the error rates of the permanent and the transient errors. Based on this analysis, we then derive the residual error of the Gallager B decoder for the regime where the transmission error rate and the processing error rates are small. In this regime, we further observe that the residual error rate can be well approximated by a suitable combination of the transient error rate and the permanent error rate at variable nodes, provided that the check node degree is large enough. Based on this insight, we then propose and analyze a scheme for detecting permanent errors and correcting detected residual errors. The scheme exploits the parity check equations of the code and reuses the existing hardware to locate permanent errors in memory blocks. Performance analysis and simulation results show that, with high probability, the detection scheme discovers correct locations of permanent memory errors, while, with low probability, it mislabels the functional memory as being defective. The proposed error detection-and-correction scheme can be implemented in-circuit and is useful in combating failures arising from aging.

Estimating Channel Parameters from the Syndrome of a Linear Code

In this letter, we analyse the properties of a maximum likelihood channel estimator based on the syndrome of a linear code. For the two examples of a binary symmetric channel and a binary input additive white Gaussian noise channel, we derive expressions for the bias and the mean squared error and compare them to the Cram\'er-Rao bound. The analytical expressions show the relationship between the estimator properties and the parameters of the linear code, i.e., the number of check nodes and the check node degree.

Large Scale LP Decoding with Low Complexity

Linear program (LP) decoding has become increasingly popular for error-correcting codes due to its simplicity and promising performance. Low-complexity and efficient iterative algorithms for LP decoding are of great importance for practical applications. In this paper we focus on solving the binary LP decoding problem by using the alternating direction method of multipliers (ADMM). Our main contribution is that we propose a linear-complexity algorithm for the projection onto a parity polytope (having a computational complexity of small O(d), where small d is the check-node degree), as compared to recent work , which has a computational complexity of small O(d log d). In particular, we show that the projection onto the parity polytope can be transformed to a projection onto a simplex.

EXIT-Chart-Based LDPC Code Design for 2D ISI Channels

In this paper, optimization of low-density parity-check (LDPC) codes to approach the symmetric information rate (SIR) of two-dimensional (2-D) intersymbol interference (ISI) channels is proposed for high-density magnetic recording, such as bit-patterned magnetic recording (BPMR) and 2-D magnetic recording (TDMR). The code design makes use of the modified Extrinsic Information Transfer (EXIT) chart, where the optimal variable node degree is searched by selecting the best check node degree to fit the check node decoder (CND) EXIT curve to the EXIT curve of the variable node decoder (VND) curve combined with 2-D detector. Simulation results show that LDPC codes with code length 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> bits optimized for a 2-D ISI channel corresponding to 4 Tb/in <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> recording density can achieve bit error rate 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> at signal-to-noise ratio 0.33 dB away from the SIR. To our knowledge, this is the first capacity-approaching LDPC code successfully optimized for a 2-D ISI channel.

A Physical-Layer Rateless Code for Wireless Channels

In this paper, we propose a physical-layer rateless code for wireless channels. A novel rateless encoding scheme is developed to overcome the high error floor problem caused by the low-density generator matrix (LDGM)-like encoding scheme in conventional rateless codes. This is achieved by providing each symbol with approximately equal protection in the encoding process. An extrinsic information transfer (EXIT) chart based optimization approach is proposed to obtain a robust check node degree distribution, which can achieve near-capacity performances for a wide range of signal to noise ratios (SNR). Simulation results show that, under the same channel conditions and transmission overheads, the bit-error-rate (BER) performance of the proposed scheme considerably outperforms the existing rateless codes in additive white Gaussian noise (AWGN) channels, particularly at low BER regions.

Low-Complexity LP Decoding of Nonbinary Linear Codes

Linear Programming (LP) decoding of Low-Density Parity-Check (LDPC) codes has attracted much attention in the research community in the past few years. LP decoding has been derived for binary and nonbinary linear codes. However, the most important problem with LP decoding for both binary and nonbinary linear codes is that the complexity of standard LP solvers such as the simplex algorithm remains prohibitively large for codes of moderate to large block length. To address this problem, two low-complexity LP (LCLP) decoding algorithms for binary linear codes have been proposed by Vontobel and Koetter, henceforth called the basic LCLP decoding algorithm and the subgradient LCLP decoding algorithm. In this paper, we generalize these LCLP decoding algorithms to nonbinary linear codes. The computational complexity per iteration of the proposed nonbinary LCLP decoding algorithms scales linearly with the block length of the code. A modified BCJR algorithm for efficient check-node calculations in the nonbinary basic LCLP decoding algorithm is also proposed, which has complexity linear in the check node degree. Several simulation results are presented for nonbinary LDPC codes defined over Z_4, GF(4), and GF(8) using quaternary phase-shift keying and 8-phase-shift keying, respectively, over the AWGN channel. It is shown that for some group-structured LDPC codes, the error-correcting performance of the nonbinary LCLP decoding algorithms is similar to or better than that of the min-sum decoding algorithm.

Distributed Joint Source-Channel Coding for Correlated Sources Using Non-systematic Repeat-Accumulate Based Codes

In this paper, we propose a technique for coding the data from multiple correlated binary sources, with the aim of providing an alternative solution to the correlated source compression problem. Using non-systematic repeat-accumulate based codes, it is possible to achieve compression which is close to the Slepian---Wolf bound without relying on massive puncturing. With the technique proposed in this paper, instead of puncturing, compression is achieved by increasing check node degrees. Hence, the code rate can be more flexibly adjusted with the proposed technique in comparison with the puncturing-based schemes. Furthermore, the technique is applied to distributed joint source-channel coding (DJSCC). It is shown that in many cases tested, the proposed scheme can achieve mutual information very close to one with the lower signal-to-noise power ratio than turbo and low density generator matrix based DJSCC in additive white Gaussian noise channel. The convergence property of the system is also evaluated via the extrinsic information transfer analysis.

Quasi-Cyclic LDPC Codes: Influence of Proto- and Tanner-Graph Structure on Minimum Hamming Distance Upper Bounds

Quasi-cyclic (QC) low-density parity-check (LDPC) codes are an important instance of proto-graph-based LDPC codes. In this paper we present upper bounds on the minimum Hamming distance of QC LDPC codes and study how these upper bounds depend on graph structure parameters (like variable degrees, check node degrees, girth) of the Tanner graph and of the underlying proto-graph. Moreover, for several classes of proto-graphs we present explicit QC LDPC code constructions that achieve (or come close to) the respective minimum Hamming distance upper bounds. Because of the tight algebraic connection between QC codes and convolutional codes, we can state similar results for the free Hamming distance of convolutional codes. In fact, some QC code statements are established by first proving the corresponding convolutional code statements and then using a result by Tanner that says that the minimum Hamming distance of a QC code is upper bounded by the free Hamming distance of the convolutional code that is obtained by "unwrapping" the QC code.

Improved Construction of Irregular Progressive Edge-Growth Tanner Graphs

The progressive edge-growth algorithm is a well-known procedure to construct regular and irregular low-density parity-check codes. In this paper, we propose a modification of the original algorithm that improves the performance of these codes in the waterfall region when constructing codes complying with both, check and symbol node degree distributions. The proposed algorithm is thus interesting if a family of irregular codes with a complex check node degree distribution is used.

A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes

For an efficient multimode low-density parity-check (LDPC) decoder, most hardware resources, such as permutators, should be shared among different modes. Although an LDPC code constructed based on a Reed-Solomon (RS) code with two information symbols is not quasi-cyclic, in this paper, we reveal that the structural properties inherent in its parity-check matrix can be adopted in the design of configurable permutators. A partially parallel architecture combined with the proposed permutators is used to mitigate the increase in implementation complexity for the multimode function. The high check-node degree of a high-rate RS-LDPC code leads to challenges in the efficient implementation of a high-throughput decoder. To overcome this difficulty, the variable nodes have been partitioned into several groups, and each group is processed sequentially in order to shorten the critical-path delay and hence increase the maximum operating frequency. In addition, shuffled message-passing decoding is adopted, since fewer iterations can be used to achieve the desired bit-error-rate performance. In order to demonstrate the usefulness of the proposed flexible-permutator-based architecture, one single-mode rate-0.84 decoder and two multimode decoders whose code rates range between 0.79 and 0.93 have been implemented. These decoders can achieve multigigabit-per-second throughput. Using the proposed architecture to support lower rate RS-LDPC codes, e.g., rate-0.568 code, is also investigated.

A Generic Scalable Architecture for Min-Sum/Offset-Min-Sum Unit for Irregular/Regular LDPC Decoder

The most common algorithm used in iterative decoding of low-density parity check (LDPC) codes is based on a generic class of the sum-product algorithm, which has a nonlinear dependence on the log(tanh()) function. The implementation based on fixed precision has substantial loss of accuracy and is computationally expensive with full precision. A suboptimal version of belief propagation called the offset-min-sum algorithm is generally used in hardware implementation. This paper proposes a generic scalable architecture for minimum search during check-node operation in the offset-min-sum algorithm applicable to regular as well as irregular LDPC codes with check node of any degree d. For an LDPC code with maximum check node degree d, the proposed architecture consists of 2(d-2) 2 × 1 multiplexers and 3(d-2) two-input compare-and-select units (CSUs). This has latency of [2⌈log2(d)⌉-2]tdc when ⌈log2(d)⌉-log2(d) <; log2(4/3) else [2⌈log2(d)⌉-3]tdc, with tdc representing the delay of a two-input CSU. The proposed architecture has been implemented for d = 20 using a TSMC 0.18-μm CMOS process.