Regulated Charge Pump Research Articles

A Temperature Compensated Voltage Controlled Relaxation Oscillator for Frequency Modulated DC-DC Charge Pump Regulation

Relaxation oscillators with wide dynamic range are required for low power frequency modulated switch mode DCDC regulator designs. In this brief, a temperature compensation technique with variable threshold control for Voltage Controlled Relaxation Oscillator (VCRO) is presented. The voltage to current conversion circuit reduces the drift in the frequency gain across temperature by introducing a PMOS-NMOS current gain compensation scheme. The current gain circuit also allows absolute control on the minimum value of control voltage after which VCRO starts doing voltage to frequency conversion. This restricts the amplifier to go out of saturation which is inherently generating the control voltage for VCRO. Measurement results show that across temperature range of -40 oC to 150 oC, the oscillator achieves a temperature stability of 187 ppm/oC at 18MHz and 171 ppm/oC at 92.5MHz respectively. Implemented in 90nm process node, it occupies 57μm×32μm area while dissipating 2.61 nW/KHz from a 1.5V supply.

High-Performance Charge Pump Regulator with Integrated CMOS Voltage Sensing Control Circuit

This paper introduces a design for a charge pump DC-DC boost regulator with an integrated low-voltage control circuit. With a charge pump and feedback circuits implemented in 0.35 µm CMOS technology, the proposed DC-DC boost regulator offers an efficient device solution for low-power applications. The proposed design employs an error amplifier, oscillator, and comparator in the control circuit which is designed with a supply voltage of 1.8–3.5 V and 2 MHz frequency. Stability is obtained via a pole-zero compensation in the feedback circuit. The charge pump regulator with four pump stages and the whole regulator circuit are analyzed using the Cadence simulation tool. Measurements of the fabricated 0.35 µm CMOS regulator show that the transient time of the error amplifier is controlled within 1.0 µsec and the output voltage is accurately controlled from 7.8 V to 9.4 V with 27–38 mV ripple and 4.5 mA maximum current.

A Low-Ripple Charge Pump With Novel Compensator for Transient-Response Improvement in CMOS Image Sensors

This brief presents a low-ripple, fully-integrated, linear-regulated charge pump with transient-response improvement for CMOS image sensors. A compensator is proposed to accelerate the recovery of the output when an undershoot occurs. The regulated charge pump is designed with 0.11 μm 1-poly 4-metal CMOS process and occupies an area of 0.073 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . According to the post-layout simulation, the worst steady-state ripple is 0.95 mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> and the recovery time (99.9%) of the regulated output is 155 ns when the undershoot is 114 mV. The application of the compensator leads to a 78% decrease on the recovery time. When achieving similar recovery time, the area cost of the proposed topology is reduced by 49% compared to the traditional method of increasing filter capacitance. The total power dissipation of the charge pump is 1.476 mW, and the compensator only consumes 28 μW.

A Regulated Charge Pump with Extremely Low Output Ripple

In this paper, we present a regulated charge pump with extremely low output ripple (&lt;1 mV) that can be used for accurate programming of nonvolatile memory. We present a technique to include a low-drop-out regulator inside the charge-pump regulation loop to reduce the ripple. This charge pump was fabricated in a 0.35 μ m standard CMOS process. The die area of this charge pump is 0.163 mm 2 . While operating from a 2.5 V supply, this charge pump generates regulated voltages up to 10 V.

Development of a charge pump for sensor biasing in a Serial Powering scheme for the ATLAS pixel detector upgrade

CMOS monolithic pixel detector technology is one of the options considered for the outer layer of an upgraded ATLAS pixel detector in 2026. In this upgrade pixel detector modules will be powered in series by a constant current source to reduce power losses and material budget. On-chip shunt regulators generate the local 1.8 V supply voltage from the input current to provide power to the integrated circuits. The sensor bias for monolithic sensors is often limited and not sufficiently large to allow a common bias for all sensors in the serial powering chain. In this paper, we give an introduction to the serial powering strategy for CMOS detectors with emphasis on the design and simulation results of a regulated charge pump circuit for sensor biasing. Two prototypes operating with a pumping frequency of 640 MHz, one with 6-stages and one with 19-stages, were designed and fabricated in a modified TowerJazz 0.18 μm CMOS imaging technology to provide negative bias down to − 6 V and − 20 V, respectively. Simulation results demonstrate good performance of the charge pump circuit which could be used to bias the CMOS sensor.

A Power Efficient Regulated Charge Pump Based on Charge Sharing for Contactless Devices: An Alternative to Four-Phase Charge Pumps

In this paper, a regulated charge sharing based charge pump with boosted transfer clocks able to operate without overlapped phases for low supply voltage is presented. The overlapping period required for the threshold voltage cancellation is removed when applying the charge sharing concept to a conventional four-phase charge pump. In order to overcome this issue, transfer clocks with higher amplitude than power supply are used to control the gate of charge transfer transistors. The charge sharing based charge pump with boosted transfer clocks and the conventional four-phase charge pump are both fabricated using a 55 nm UMC High Voltage CMOS technology. Experimental measurement results reveal that the power efficiency of the charge sharing charge pump with boosted transfer clocks can be 20% higher than a traditional four-phase charge pump for an output programming current of 20 mu A. Thus, charge sharing based charge pumps are suited for low power contactless devices using an embedded NOR Flash memory for storage and code execution.

A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- μm 1.8-V/3.3-V Low-Voltage CMOS Process

A new digitally dynamic power supply technique for 16-channel 12-V-tolerant stimulator is proposed and realized in a 0.18-μm 1.8-V/3.3-V CMOS process. The proposed stimulator uses four stacked transistors as the pull-down switch and pull-up switch to withstand 4 times the nominal supply voltage (4 × V DD). With the dc input voltage of 3.3 V, the regulated three-stage charge pump, which is capable of providing 11.3-V voltage at 3-mA loading current, achieves dc conversion efficiency of up to 69% with 400-pF integrated capacitance. Power consumption is reduced by implementing the regulated charge pump to provide a dynamic dc output voltage with a 0.5-V step. The proposed digitally dynamic power supply technique, which is implemented by using a p-type metal oxide semiconductor (PMOS) inverter with pull-down current source and digital controller, greatly improves the power efficiency of a system. The silicon area of the stimulator is approximately 3.5 mm2 for a 16-channel implementation. The functionalities of the proposed stimulator have been successfully verified through animal test.

Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process

A regulated cross-couple charge pump with new charging current smoothing technique is proposed and verified in a 0.18- $\mu \text {m}~1.8$ -V/3.3-V CMOS process. The transient behaviors of 3-stage cross-couple charge pump and the expressions for the charging current are described in detail. The experiment results show that the charging current ripples are reduced by a factor of three through using the proposed new clocking scheme. The voltage ripples in the power supply line, which is connected with the charge pump input, are also smoothed greatly as the filter circuit does. The proposed scheme is used to decrease the smoothing capacitance in the power line of charge pump for reducing the size of implantable devices in biomedical application. In addition, the power efficiency is improved. The proposed cross-couple charge pump can provide 10.5-V output voltage with 3.5-mA output current, and the power efficiency of the charge pump can be up to 69%.

A Regulated Charge Pump for Tunneling Floating-Gate Transistors

Flash memory is an important component in many embedded system-on-a-chip applications, which drives the need to generate high write/erase voltages in generic CMOS processes. In this paper, we present a regulated, high-voltage charge pump for erasing Flash memory and floating-gate transistors. This 0.069-mm2 charge pump was fabricated in a 0.35 $\mu \text {m}$ standard CMOS process. While operating from a 2.5 V supply, the charge pump generates regulated voltages up to 16 V with a PSRR of 52 dB and an output impedance of 6.8 $\text{k}\Omega $ . To reduce power consumption for use in battery-powered applications, this charge pump uses a variable-frequency regulation technique and a new circuit for minimizing short-circuit current in the clock-generation circuitry; the resulting charge pump is able to erase the charge on floating-gate transistors using only $1.45 \mu J$ .

Стенд для исследования характеристик микросхем источников вторичного электропитания с накачкой заряда

An automated test bench for the study of the characteristics of various kinds of chips of mobile sources of regulated charge pump secondary power supply receiving energy from batteries was created. Having a modular structure, the test bench includes, in addition to the test charge pump module, power supply, control, load, display modules, and a USB module for connection with a computer. The test bench enables carrying out research of various types of chips by changing only one small measuring board. The control module is based on PIC18F2550 microcontroller. The automated measuring system consists of a multimeter and oscilloscope. The investigated characteristics are output voltage as a function of load current, output voltage as a function of supply voltage, the forms of the output voltage ripple, the response of chips to a stepped load transition. One of the major goals of the research is to study algorithms of the charge pump circuits. A program for controlling the test bench by creating a virtual front panel was developed. Together with a virtual panel of the oscilloscope and available multimeter software this allows controlling the equipment operating parameters and making measurements remotely over the Internet. Using the created test bench new experimental data on all of the above characteristics for MAX1759 chip were obtained, and an algorithm of this chip in the buck mode operation was studied for the first time.

A low jitter supply regulated charge pump PLL with self-calibration**Project supported by the National Key Basic Research and Development Program of China (No. 2015CB352100).

This paper describes a ring oscillator based low jitter charge pump PLL with supply regulation and digital calibration. In order to combat power supply noise, a low drop output voltage regulator is implemented. The VCO gain is tunable by using the 4 bit control self-calibration technique. So that the optimal VCO gain is automatically selected and the process/temperature variation is compensated. Fabricated in the 0.13 μm CMOS process, the PLL achieves a frequency range of 100–400 MHz and occupies a 190 × 200 μm2 area. The measured RMS jitter is 5.36 ps at a 400 MHz operating frequency.

High-Performance Regulated Charge Pump with an Extended Range of Load Current

High-Performance Regulated Charge Pump with an Extended Range of Load Current

Integrated high voltage boost converter with LC filter and charge pump

Purpose – The paper aims to design of dual-mode boost converter with integrated low-voltage control circuit is introduced in this paper. The paper aims to discuss these issues. Design/methodology/approach – The converter is operated either with LC filter or with charge pump circuit by the switch control. The control stage with error amplifier, comparator, and oscillator is designed with the supply voltage of 3.3 V and the operating frequency of 5.5 MHz. The compensator circuit exploits a pole compensation for a stable operation. Findings – The simulation test in 0.35 μm CMOS process shows that the charge pump regulator and DC-DC boost converter are accurately controlled with the variation of number of stages and duty ratio. The output-voltage is obtained to be 6-15 V within the ripple ratio of 5 percent. Maximum power consumption is about 0.65 W. Originality/value – This dual-mode is useful in the converter with a wide load-current variation. The advantage of the dual-mode converter is that it can be used in either high or low load current with a simple switch control. Furthermore, in charge pump regulator, there is no degradation of output voltage because of the feedback control circuit.

Dual Negative Regulated Charge Pump

Dual Negative Regulated Charge Pump

A Regulated Charge Pump With a Low-Power Integrated Optimum Power Point Tracking Algorithm for Indoor Solar Energy Harvesting

This brief presents a regulated charge pump (CP) with an integrated optimum power point tracking (OPPT) algorithm designed for indoor solar energy harvesting. The proposed OPPT circuit does not require a current sensor that consumes power proportionally to the load. The solar cell voltage is regulated at the optimum power point; the CP output is regulated according to the target voltage. The controller of the OPPT circuit and CP dissipates only 450 nW; thus, the proposed technique is appropriate for indoor solar energy harvesting applications under dim lighting conditions.

A gain-optimising regulated charge pump

A high-efficiency charge-pump regulator formed by the proposed reconfigurable charge pump is presented in this article. The voltage gain of the reconfigurable charge pump can be adaptively adjusted based on the input voltage and the regulated output voltage. Enhancement of power efficiency is therefore achieved by reducing the conduction loss of the cascaded linear regulator due to the optimised gain of the reconfigurable charge pump. The proposed charge-pump regulator was implemented in commercial complementary metal-oxide semiconductor (CMOS) 0.35 μm technology. The active chip area is 0.46 mm2. The input range is from 1.5 to 3.3 V. The experimental results show that the proposed charge-pump regulator improves the power efficiency by as much as 40% when regulated at 1.2 V.

A low noise regulated charge pump circuit

In this work, a low noise regulated charge pump circuit is presented. The proposed charge pump uses a digital frequency shaped clock scheme to spread tonal energy of the oscillator to overall frequency ranges, and reduces the output noise of the charge pump, and improves the power efficiency. To achieve constant output voltage during an over loading condition, the proposed charge pump utilizes feedback. The proposed charge pump generates 4.1V ∼ 4.4V output voltage and provides 30mA current driving capability with 30mV ripple at 2.5V ∼ 3.5V supply line. At 800MHz ∼ 2.2GHz ranges, the output noise power of the proposed charge pump is at least 11.4dBm less than that of a charge pump with normal clock.

A dual-phase charge pump circuit with compact size

In this paper, a regulated dual-phase charge pump with compact size is presented. By means of a nano-ampere switched-capacitor voltage reference (SCVR) circuit, the dual-phase charge pump regulator can reduce the quiescent current and the output ripple. Besides, a new power stage is proposed to define the stability of the overall system. Owing to the design of buffer stage, the charge pump regulator can extend bandwidth and increase phase margin. Thus, the transient response and driving capability can be improved. Beside, the proposed automatic body switching circuit can efficiently drive the bulk of the power p-type MOSFETs to avoid leakage and potential latch-up. This chip was fabricated by TSMC 0.35 μm, 3.3 V/5 V 2P4 M CMOS technology. The input voltage range varies from 2.9 to 4.9 V for the lithium battery and the output voltage is regulated at 5 V. Experimental results demonstrate the charge pump can provide 50 mA maximum load current without any oscillation problems.

Low-Ripple and Dual-Phase Charge Pump Circuit Regulated by Switched-Capacitor-Based Bandgap Reference

This paper proposes a low-ripple and dual-phase charge pump circuit regulated by switched-capacitor-based bandgap reference. Due to design of a buffer stage, a system can have better bandwidth and phase margin, and thus, the transient response and driving capability can be improved. Besides, the dual-phase control can reduce the output voltage ripple by means of only one closed-loop regulation in order to improve the power conversion efficiency. Besides, the proposed automatic body switching (ABS) circuit can efficiently drive the bulk of the power p-type MOSFETs to avoid leakage and potential latch-up. Usually, the regulated charge pump circuit needs a bandgap reference circuit to provide a temperature-independent reference voltage. The switched-capacitor-based bandgap reference circuit is utilized to regulate the output voltage. This chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 mum 3.3 V/5 V 2P4M CMOS technology. The input voltage range varies from 2.9 to 5.5 V, and the output voltage is regulated at 5 V. Experimental results demonstrate that the charge pump can provide 48 mA maximum load current without any oscillation problems.

Ripple reduction on skipping-based regulated two-phase voltage doubler charge pump

An on-chip ripple reduction system for a regulated two-phase voltage doubler charge pump circuit is presented. Simulated results show that ripple reduction ratios up to 53% can be achieved when the designed ripple reduction solution is applied over a 5 V regulated charge pump with flying and load capacitors Cf =CL=1 µF, switching frequency fs=100 kHz, and load RL=10 kΩ.