Charge Balance Control Research Articles

A dual-mode digital controller with a high accuracy load current estimator and Gaussian adaptive duty cycle switching for fast transient recovery in DC-DC buck converters

To improve the dynamic performance, this paper proposes a dual-mode digital controller with a high accuracy load current estimator and Gaussian adaptive duty cycle switching for DC-DC buck converters with an auxiliary power stage. The proposed digital controller has two operating modes: steady state and transient. In steady-state mode, a conventional PID control module is used to regulate the main power stage and the output voltage. In transient mode, a charge balance control module is responsible for controlling the auxiliary power stage to improve the dynamic performance. A long short-term memory (LSTM)-based load current estimator is proposed to obtain high accuracy load current. It employs a multiple-to-one structure and estimates the load current based on time series data (a sequence of data points indexed in time order). A Gaussian adaptive duty cycle switching is proposed to suppress the output voltage chattering when transitioning between the auxiliary and the main power stages. Simulation and experimental results demonstrate that the proposed controller has a superior dynamic performance when compared to controllers using linear-based load current estimator and direct duty cycle switching. The overshoot/undershoot and settling time can be reduced by over 50 % for a 1.9 A load transient in a 5 to 1.8 V buck converter operating switching at 2 MHz..

State of Charge Balancing Control for Multiple Output Dynamically Adjustable Capacity System

<div>A multiple output dynamically adjustable capacity system (MODACS) is developed to provide multiple voltage output levels while supporting varying power loads by switching multiple battery strings between serial and parallel connections. Each module of the system can service either a low voltage bus by placing its strings in parallel or a high voltage bus with its strings in series. Since MODACS contains several such modules, it can produce multiple voltages simultaneously. By switching which strings and modules service the different output rails and by varying the connection strategy over time, the system can balance the states of charge (SOC) of the strings and modules. A model predictive control (MPC) algorithm is formulated to accomplish this balancing. MODACS operates in various power modes, each of which imposes unique constraints on switching between configurations. Those constraints are mathematically formalized so that MPC can be applied to minimize predicted SOC differences over a finite time horizon. In this article, several variations that vary in how freely strings can connect and disconnect from the bus bars are presented. Methods allowing more flexibility in configuration changes can balance SOCs more quickly but take more computation to resolve. In contrast, simpler schemes reduce computation and simplify implementation, but take longer to balance the SOCs. Simulation results illustrate the expected behavior.</div>

Reliability evaluation of a novel fault tolerant multilevel inverter with reduced components

Safety–critical applications rely heavily on multilevel inverters. This article introduces a fault tolerant (FT) multilevel inverter sustaining an uninterrupted operation with an open switch fault occurred in a single and multiple power switches. Power semiconductor devices used in dc-ac converters increased in numbers to obtain high-quality voltage waveform which makes them vulnerable to failure. As a result, reliability is one of the biggest challenges in the utilization of multilevel inverters (MLIs) in many industrial applications. At the same time, reduced component multilevel inverters can achieve the highest resolution in output voltage waveform by compromising significant features (such as fault tolerance ability, charge balance control, etc.) but it is required to be preserved. For effective fault tolerant operation of MLIs, redundant switching states have given the highest priority in terms of switch level failures. A study is being undertaken to develop a novel fault-tolerant MLI, in the event of an open circuit fault on single and multiple switches. Therefore, the proposed FT-MLI structure can fulfill the operational requirement for a time being and claimed to be reduced components. A valid fault tolerant switching technique along with appropriate fault clearance is employed to obtain the desirable output voltage waveforms. In order to determine the feasibility of FT-MLI, performance evaluations are carried out based on results obtained under normal and abnormal operating conditions through the use of a laboratory prototype.

Drive Control Strategy for Plug-in Hybrid Electric Vehicle System Based on Modular Multilevel Converter

A power conversion system for plug-in hybrid electric vehicles (PHEV) based on “back-to-back” modular multilevel converter(BMMC) is proposed to solve the problem that the traditional MMC-EV can only work with one motor. The power flow of BMMC system with two motors is complex and no one has ever studied it. The state of charge (SOC) balance control strategy of the integrated power converter is studied in various driving modes by this paper. Based on the bridge arm current control, this strategy combines the vector control of permanent magnet synchronous motor(PMSM) with the hierarchical SOC equalization control, realizes the high performance drive control of PHEV system, and high-efficiency power transfer and management among motor, generator and battery, and avoids the battery and energy loss caused by the redundant charge and discharge process. At the same time, it is convenient to switch freely between different driving modes. The correctness and feasibility of this control strategy are verified through RT-LAB real-time simulation.

Charge Balance Control for DC/DC Converter Systems: From Single-Input Systems to Multiple-Input Systems

DC–DC converters with high dynamic performance are attracting more and more attentions in industry and academia. The charge balance control (CBC) method enables the single-input dc–dc (SIDD) converter system to achieve optimal dynamic performance. In this article, the CBC method for the multiport converter is proposed, and the analogy and the innovative transplantation approach of the CBC from single-input systems to multi-input systems are developed. First, general steps and unified equations of the CBC for SIDD converter are summarized. Second, through analogy analysis, the CBC method is transplanted to a full-bridge three-port converter (FB-TPC) system to improve the dynamic performance under load step change. Third, through innovative transplantation, a CBC strategy based on magnetizing current three-stage regulation is proposed, achieving optimal dynamic performance for the FB-TPC system under power distribution step change. Experimental results on an FB-TPC verify the feasibility and effectiveness of the CBC methods for multiport converter and the transplantation method.

Auto‐tuning charge balance control for improving transient response on buck converter

SummaryLoad transient and dynamic voltage scaling (DVS) are commonly seen in the operation of the system processor. These two functions usually encounter large output voltage transient, which is hard to be quickly settled. Charge balance control is one of the prior choices that enables the converter to operate at its optimal charge/discharge slew rate so as to achieve fast transient response. The effectiveness of the optimal performance generally requires precise knowledge of the circuit parameters for charge balance computation. However, parameter drifting due to the manufacturing process may affect the performance, which is hard to implement a power integrated circuit (IC) for wide range applications. Different from the original approaches, this paper proposes an auto‐tuning charge balance control (AT‐CBC) to optimize load transient response and DVS of the buck converter. The auto‐tuning mechanism can save the preknowledge of the output filter and avoid complex calculation in digital control. The function of AT‐CBC is validated by a field‐programmable gate array (FPGA) controlled buck converter. Experimental result shows that the output voltage can be settled within 3 μs for the 750‐mA load step transient. For the 0.3‐V DVS transient, the output voltage can be settled within 4 μs.

One Million Cycle Durability Test of Electrochromic Devices Using Charge Balance Control

We fabricated 10 mm × 10 mm WO3 electrochromic devices (ECDs) using a nanoparticle deposition system (NPDS), which is a coating method that uses kinetic spray. NPDS has the advantage of mass production due to its relatively low pressure and low temperature working conditions but can result in porous surfaces, which has a negative effect on device durability. We developed an optical transmittance measurement and voltage control system that allows dynamic control. Transmittance was measured by Optical Power Meter, 2936-R Newport, while voltage was dynamically applied by NI9477, National Instrument. Current was measured by high resolution current, National Instrument. This system enables ECDs to be feedback controlled depending on the measured electronic properties. We then characterized the WO3 ECDs, focusing on the relationship between transmittance and current under well-known static operating conditions. Finally, we proposed a new algorithm to extend durability performance by adopting charge balance control and conducted an accelerated life test over 1,000,000 cycles. According to our results, the optical performance was maintained until the test ended, and there was a 45.4% difference in the maximum and minimum transmittance of the sample after the accelerated life test. Therefore, the charge balance control enhanced the lifetime of the ECDs by avoiding negative charge accumulation, verifying that the durability of ECDs could be enhanced by adopting dynamic control.

Linearized Discrete Charge Balance Control with Simplified Algorithm for DCM Buck Converter

In this paper, a linearized discrete charge balance (LDCB) control strategy is proposed for buck converter operating in discontinuous conduction mode (DCM). For DC-DC power converters, discrete charge balance (DCB) control is an attractive approach to improve the output voltage transient response. However, as a non-linear control strategy, the algorithm is complex, which is difficult for implementation. To reduce the complexity, this paper proposes the LDCB control strategy that is derived through linearizing conventional DCB controller. By deriving the differential functions of the DCB control algorithm, the small signal relationship between the input and output of DCB controller is explored. Furthermore, based on the relationship, the LDCB controller is formed through three parallel feed loops to the duty ratio. As a linear control approach, the achieved LDCB controller is greatly simplified for implementation. This not only saves the hardware cost, but also reduces the calculation lag, which provides potential to improve the switching frequency. Besides, since the LDCB controller shares the same small signal model as that of DCB controller, it achieves similar control loop bandwidth and transient performance. Effectiveness of the proposed LDCB control is verified by zero/pole plots, transient analyses and experimental results.

Boosting Efficiency in Polycrystalline Metal Halide Perovskite Light-Emitting Diodes

Metal halide perovskites (MHPs) have outstanding photophysical properties and are therefore being evaluated as next-generation light emitters. Within just a few years, the efficiencies of polycrystalline perovskite light-emitting diodes (PeLEDs) have been drastically improved and are catching up with those of conventional organic LEDs. The electroluminescence efficiency of polycrystalline PeLEDs has been limited by shortcomings such as limited outcoupling efficiency, charge imbalance in MHP emitting layers, difficulty controlling surface morphology, small exciton binding energy at room temperature, and nonradiative recombination at defect sites. In this Perspective, we focus on promising strategies such as optical engineering, charge balance control, morphological and nanograin engineering, and chemical modification to overcome these shortcomings and suggest future directions for research to further improve the efficiencies of polycrystalline PeLEDs.

A low-cost and flexible architecture of digitally controlled DC-DC converter to improve dynamic performance

One type of DC-DC converters is dual transistor forward converter. In this article, a low-cost architecture of a digital controller for dual transistor forward converter is presented. This architecture is designed by using the finite set model predictive control technique. Based on this approach, a low-cost fixed-point arithmetic architecture with minimum functional units is presented to find the optimum switching time at each sampling point. Charge balance control method is utilized to improve the dynamic performance of the transient response. The proposed architecture is implemented and realized by using a field-programmable gate array (FPGA) platform to evaluate the precision of the fixed-point calculation. Several cases for different loading conditions for different word lengths are practically investigated and the proposed digital controller shows a minimum voltage overshoot--undershoot and short settling time under load-changing situations. Compared with other controllers, the presented work provides a better dynamic performance and lower implementation cost.

New Cascaded Multilevel Inverter by Using Capacitor Based Basic Units with the Capability of Charge Balance Control Method

In this paper, two new cascaded multilevel inverters based on new capacitor basic unit are proposed. In the proposed topologies, the same numbers of dc voltage source and capacitor are used that lead to decrease the number of required insulated dc voltage sources. In order to generate all positive and negative voltage levels (even and odd) at the output three different algorithms to determine the magnitude of voltage sources are proposed. Minimum number of used power electronic devices and lower amount of blocked voltage that is made by power switches are two main advantages of the proposed topologies. These features lead to decrease the installation space and total cost of the inverter. These are obtained by comparing the proposed topologies with several capacitor based cascaded multilevel inverters. In addition, in order to balance the used capacitors’ voltage, a new charge balance control method is proposed. Finally, the correct performance of the proposed cascaded inverter is reconfirmed through experimental and simulation results on a five-level proposed inverter in EMTDC/PSCAD software program.

Multiagent-Based Distributed State of Charge Balancing Control for Distributed Energy Storage Units in AC Microgrids

In this paper, a multiagent-based distributed control algorithm has been proposed to achieve state of charge (SoC) balance of distributed energy storage (DES) units in an ac microgrid. The proposal uses frequency scheduling instead of adaptive droop gain to regulate the active power. Each DES unit is taken as an agent and it schedules its own frequency reference given of the real power droop controller according to the SoC values of all other DES units. Further, to obtain the average SoC value of DES, the dynamic average consensus algorithm is utilized by each agent. A generalized small-signal model of the proposed frequency scheduling for the proposed frequency scheduling is developed in order to verify the stability of the control system and to guide control parameters design. The convergence characteristics for the dynamic consensus adopted in the multiagent system are also analyzed to choose the proper control parameter. Experimental results verified the effectiveness, the robustness against communication topology changes, and capability of “plug & play” for the proposed multiagent system through different case studies.

Control of Active Power Exchange With Auxiliary Power Loop in a Single-Phase Cascaded Multilevel Converter-Based Energy Storage System

Cascaded multilevel converter (CMC)-based energy storage system, which consists of cascaded H-bridge converters and energy storage components, is a promising option to compensate fluctuating electric power of renewable energy. This paper proposes a novel single-phase CMC-based battery storage system, which includes an LC branch. The cascaded converter cells and the LC branch form an auxiliary power loop, which could realize active power exchange between different cells with the proposed dual-frequency phase-shifted carrier pulse width modulation (DF-PSC PWM). The principle and effectiveness of DF-PSC PWM and the power transfer mechanism are analyzed. Meanwhile, the design of the tuned filter, output filter, and the state of charge balancing control system is introduced. The operation principle of the power exchange in the proposed energy storage system has been successfully verified by simulation and experimental results.

A New Cascaded Multi-level Inverter Topology with Reduced Number of Components and Charge Balance Control Methods Capabilities

In this article, a new basic unit for cascaded multi-level inverter is proposed. This inverter is able to increase the number of output voltage levels and reduces the number of power electronic devices. To generate all voltage levels at the output, five different algorithms to determine the magnitude of DC voltage sources are suggested. This inverter is compared with conventional cascaded multi-level inverters. The comparisons show that the proposed topology needs fewer DC voltage sources and power switches, less variety of the magnitude of DC voltage sources, and smaller amounts of blocked voltage by switches. As a result, the installation space and total cost of the inverter decrease. As it is impossible to use charge balance control methods for the asymmetric cascaded multi-level inverters, the developed topology based on the proposed cascaded inverter–the sub-symmetric topology with the usability of charge balance control methods–is proposed. A new algorithm is proposed to determine the magnitude of DC voltage sources. In addition, full-wave and half-wave charge balance control methods are applied in the proposed developed topology. The accurate performance of the proposed topology by applying charge balance control methods is verified through the simulation and experimental results of an 81-level sub-symmetric inverter.

Charge Balancing Control for an Asymmetric Multilevel Inverter with Multiple Paired-H-Bridges

Cascaded H-Bridge (CHB) multilevel inverter (MLI) is among the most preferred topology in solar PV systems. While traditional asymmetric CHB MLI is easy to achieve higher number of output voltage levels compared to traditional symmetric CHB MLI, charge balancing between the voltage sources remains a challenge for asymmetric CHB MLI. This drawback results in unsteady DC voltage levels due to unbalanced power drawn from each voltage sources. Besides that, in battery powered applications, unbalanced power drawn results in unequal discharged in the batteries. In this paper, an asymmetric CHB MLI topology is proposed which is easier to modularize as for symmetric CHB MLI while maintaining the ease in charge balancing control. The performance of this proposed asymmetric CHB MLI with charge balance control has been evaluated using PSIM software.

Three-Phase Asymmetric Multilevel Inverter Topologies with Better Charge Balancing

Cascaded H-bridge multilevel inverter is among the most preferred topology in solar systems. While traditional asymmetric cascaded H-bridge multilevel inverter is easy to achieve higher number of output voltage levels compared to traditional symmetric cascaded H-bridge multilevel inverter, charge balancing between the voltage sources remains a challenge for asymmetric cascaded H-bridge multilevel inverter. This drawback results in unsteady DC voltage levels due to unbalanced power drawn from each voltage sources. Besides that, in battery powered applications, unbalanced power drawn results in unequal discharged in the batteries. In this paper, two three-phase asymmetric cascaded H-bridge multilevel inverter topologies are proposed which offer easier in terms of modularity while maintaining the ease in charge balancing control. The performance of these two proposed topologies with charge balance control has been evaluated using PSIM software.

Asymmetric Cascaded DC Sources Multilevel Inverter with Less Active Switches and Simpler Control Strategy

Cascaded H-Bridge (CHB) multilevel inverter (MLI) is among the most preferred topology in solar PV systems. While traditional asymmetric CHB MLI is easy to achieve higher number of output voltage levels compared to traditional symmetric CHB MLI, charge balancing between the voltage sources remains a challenge for asymmetric CHB MLI. This drawback results in unsteady DC voltage levels due to unbalanced power drawn from each voltage sources. Besides that, in battery powered applications, unbalanced power drawn results in unequal discharged among the batteries. In this paper, an asymmetric half H-bridge (HHB) MLI topology is presented which is easy to modularize as for symmetric CHB MLI while maintaining the ease in charge balancing control. The performance of this proposed asymmetric HHB MLI with charge balance control has been evaluated using PSIM software.

Design of Integrated Bipolar Symmetric Output DC–DC Power Converter for Digital Pulse Generators in Ultrasound Medical Imaging Systems

This paper presents a bipolar symmetric output switching dc–dc converter for digital pulse generators in ultrasound medical imaging systems. The proposed power stage architecture can generate symmetric bipolar supply voltages, while operating in a time-interleaving manner. Meanwhile, in order to power unipolar pulse generators with the same peak-to-peak pulse amplitude, the power stage can also be reconfigured to deliver a 2× unipolar output voltage. The power converter employs an adaptive <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\Delta}I$</tex></formula> charge balance control scheme to ensure that the outputs are symmetrically balanced and well regulated. At the circuit level, to utilize a single feedback controller for both power stage topologies, the assignment of a suitable chip ground is discussed. A prototype is fabricated using a 0.25-μm CMOS process and occupies a chip area of 6 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{2}$</tex></formula> . For an input supply voltage of 1.5 V, the dc–dc converter can regulate the bipolar outputs at a nominal voltage level of ±2.5 V and at 5 V for the unipolar output configuration and a maximum load current of 45 mA for both. The bipolar output power converter achieves a maximum efficiency of 83.4% at a load power of 187.5 mW, with the voltage balance error maintained within ± 2% over the entire load range.

A New Digital Control Algorithm for Dual-Transistor Forward Converter

In this paper, a new digital control algorithm is presented to improve the dynamic performance of the dual-transistor forward converter (DTFC) during a transient event. The algorithm uses a linear control scheme under the stable-state condition and the charge balance control scheme under the transient condition. Based on the principle of capacitor charge balance, the proposed algorithm predicts the switch over time to achieve optimal transient response for a DTFC, thus the minimal voltage derivation and recovery time are achieved when the load current has a step change. Compared with a conventional voltage mode controller, the proposed algorithm provides a much better dynamic performance. Furthermore, simulation and experiment results demonstrate the effectiveness of the algorithm.

Cascaded cross‐switched multilevel inverter in symmetric and asymmetric conditions

This study proposes and analyses a new cascaded multilevel inverter in both symmetric and asymmetric conditions. Firstly, the topology is presented in general form and then it is optimised. For any given number of voltage levels, the proposed topology reduces the number of switches. In the symmetric condition, the proposed topology offers capability of charge balance control method while reducing the number of switches. Also, unlike the other reduced switch topologies, the proposed topology does not increase the total standing voltage of the switches in comparison with the conventional cascaded H-bridge (CHB) multilevel inverter. In the asymmetric condition, the proposed topology has highest output voltage resolution while keeping the total standing voltage equal to the CHB topology. In other words, in both symmetric and asymmetric conditions the number of switches in the proposed topology is lower than that of the CHB topology. However, both the proposed topology and also the CHB topology have the same total standing voltage on the switches. Other asymmetric topologies use higher number of switches and have higher total standing voltage in comparison with the proposed asymmetric topology. A modified phase-shifted-pulse width modulation is also presented for the proposed symmetric topology. The proposed topology is verified with simulation and experimental results.