Characteristics Of Polycrystalline Silicon Thin-film Transistors Research Articles

Study on Characteristics of Poly-Si TFTs With 3-D Finlike Channels Fabricated by Nanoimprint Technology

This study addresses the characteristics of polycrystalline-silicon thin-film transistors (poly-Si TFTs) with 3-D finlike channels fabricated using ultraviolet nanoimprint lithography. The poly-Si 3-D finlike channels with a line width/space ratio of about $\sim$ 1 : 1 were fabricated and studied by scanning electron microscope and transmission electron microscopy. The poly-Si TFTs with 3-D finlike channels, fabricated using the nanoimprint technique, have superior performances in comparison to that with the single channel. Besides, the characteristics of poly-Si TFTs, such as the transfer characteristics, output drain current, transconductance, on/off current ratio, subthreshold swing, and field-effective mobility, with respect to the width/space/height of 3-D finlike structures were also investigated. The proposed approach can be utilized to fabricated high-performance poly-Si TFTs or high-sensitivity biosensors at low cost.

Drain current model for thin-film transistors with interface trap states

A surface-potential-based drain current model for thin-film transistors (TFTs) is presented. In this model, the influence of traps located at the gate-oxide/silicon interface is accounted for to reproduce the gradual increase in the subthreshold current. The model uses a single equation that includes both drift and diffusion current components to describe the drain current in all operation regions. Calculations using the model produce results that are in good agreement with the measured current-voltage characteristics of polycrystalline silicon TFTs with large grains.

Improvement of Memory State Misidentification Caused by Trap-Assisted GIDL Current in a SONOS-TFT Memory Device

This letter studies the nonvolatile memory characteristics of polycrystalline-silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon (SONOS) structure. As the device was programmed, significant trap-assisted gate-induced drain leakage current was observed due to the extra programmed electrons trapped in the nitride layer which lies above the gate-to-drain overlap region. In order to suppress the leakage current and thereby avoid signal misidentification, we utilized band-to-band hot hole injection into the nitride layer. Because the injected hot holes can remain in the nitride layer after repeated Fowler-Nordheim erase and program operations, this method can exhibit good sustainability in such a SONOS-TFT memory device.

Turn-on characteristics of polycrystalline silicon TFT's-impact of hydrogenation and channel length

Experimental measurements and two-dimensional (2-D) numerical simulation have been used to investigate the impart of the polycrystalline silicon (poly-Si) density of states (DOS) and channel dimensions on the transient response of poly-Si thin-film transistors (TFTs). TFTs exposed to different hydrogenation times were used to investigate the effect of the poly-Si DOS. The experimental results show that TFT turn-on time increases with increasing channel length and decreases with increasing hydrogenation time. For the first time, transient simulations were carried out using best fit poly-Si DOS distributions which were extracted numerically from DC transfer characteristics. The resulting simulations show excellent agreement with the experimental data. Degradation in the transient characteristic is thereby correlated with an increase In the poly-Si DOS.

On the characteristics of polycrystalline-silicon thin-film transistors; two-dimensional numerical analysis

A two-dimensional non-planar device simulator for poly-Si TFT is developed, in which the influences of trapped charges and carrier scattering within the grain boundary are incorporated into Poisson's equation and drift-diffusion current formulations, respectively. With this simulator, the I-V characteristics of poly-Si TFT devices can be characterized. Thin-film transistors on polycrystalline silicon were fabricated for testing. Excellent agreement between the simulated results and the experimental data has been obtained. Some TFT characteristics, such as the ‘pseudo-subthreshold’ region, the activation energy and the barrier height are investigated and elucidated by our simulator. Finally, making use of this simulator, we have investigated the effects of poly-Si film and gate oxide thickness on the TFT I-V characteristics; the simulated results predict that scaling down the oxide thickness will drastically improve the driving capability by reducing the grain potential barrier.

Effect of GE incorporation on the performance of P-channel polycrystalline Si 1−xGe x thin-film transistors : H. C. Lin, H. Y. Lin and C. Y. Chang. Solid-State Electronics, 39 (5), 645 (1996)

We present a new analytical model for the current-voltage characteristics of polycrystalline-silicon thin-film transistors (poly-Si TFTs). We use an “effective medium” approach which treats a polycrystaline film with grain boundaries as a uniform effective medium with an effective mobility and density of states in the energy gap. The current-voltage characteristics and their derivatives with respect to terminal voltages are continuous for both the below and above threshold regimes. A new interpretation of the saturation voltage allows us to accurately describe the finite output conductance in saturation, and we also realistically describe the “kink” effect. Our model has only five parameters which are easily extractable from experimental data: ideality factor (η), low-field mobility (μ0), threshold voltage (VT), output conductance parameter (Γ), and kink parameter (V0). We calculate the current-voltage characteristics of n-and p-channel poly-Si TFTs with 5, 6, 10, 15, and 30 μm gate lengths and 50 μm gate width and obtain a good agreement between calculation and experiment. Our analytical model is suitable for automatic parameter extraction and has been used for computer aided design.

On the pseudo-subthreshold characteristics of polycrystalline-silicon thin-film transistors with large grain size

A two-dimensional nonplanar device simulator for polycrystalline-silicon thin-film transistors (poly-Si TFTs) was developed, in which the influence of trapped charges and carrier scattering within the grain boundary region are incorporated into Poisson's equations and drift-diffusion current formulations, respectively. With this simulator, the I-V characteristics of poly-Si TFT devices can be characterized. TFTs in polycrystalline silicon were fabricated to test the simulator. Special attention was paid to the conduction mechanism in poly-Si TFTs with large grain size. A concept called the pseudo-subthreshold region is presented to explain the observed behavior. The key factors affecting the pseudosubthreshold slope were investigated and elucidated using the simulator.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New analytical polycrystalline-silicon thin-film transistor model for computer aided design and parameter extraction

We present a new analytical model for the current-voltage characteristics of polycrystalline-silicon thin-film transistors (poly-Si TFTs). We use an “effective medium” approach which treats a polycrystaline film with grain boundaries as a uniform effective medium with an effective mobility and density of states in the energy gap. The current-voltage characteristics and their derivatives with respect to terminal voltages are continuous for both the below and above threshold regimes. A new interpretation of the saturation voltage allows us to accurately describe the finite output conductance in saturation, and we also realistically describe the “kink” effect. Our model has only five parameters which are easily extractable from experimental data: ideality factor (η), low-field mobility (μ 0), threshold voltage ( V T ), output conductance parameter (Γ), and kink parameter ( V 0). We calculate the current-voltage characteristics of n-and p-channel poly-Si TFTs with 5, 6, 10, 15, and 30 μm gate lengths and 50 μm gate width and obtain a good agreement between calculation and experiment. Our analytical model is suitable for automatic parameter extraction and has been used for computer aided design.