Characteristics Of poly-Si TFTs Research Articles

Characterization of (100)-Dominantly Oriented Poly-Si Thin Film Transistors Using Multi-Line Beam Continuous-Wave Laser Lateral Crystallization

(100)-dominantly oriented poly-Si film was realized by using multi-line beam (MLB) continuous-wave laser lateral crystallization (CLC) with overlapping. Si grains were developed along laser scanning direction with an average grain size of approximately 20 μm x 2 μm. The fabricated TFTs have high field effect mobility up to 1010 cm2/Vs. In this work, the device characteristics of the fabricated TFTs are investigated. Fabrication process of the poly-Si TFTs are as follows: A buffer SiO2 layer of 1 μm thickness was deposited on a quartz substrate by Plasma-Enhanced Chemical Vapor Deposition (PECVD). Sequentially, an amorphous Si (a-Si) film of 150 nm thickness and a cap SiO2 of 100 nm thickness were deposited by PECVD. The films were dehydrogenated by furnace annealing at 490 oC in N2 ambient for an hour before crystallization with MLB-CLC (wavelength: 532 nm, laser power: 6 W). The laser beams scanned the sample at a speed of 0.8 cm/s with an overlapping ratio of 83%. After the cap SiO2 layer was etched by buffered hydrofluoric acid (BHF) solution, the poly-Si active layer was patterned using lithography and dry etching (Cl2: 20 sccm, HBr: 20 sccm). Gate oxide SiO2 of 42 nm thickness was deposited by Electron cyclotron Resonance (ECR) Plasma Chemical Vapor Deposition (SiH4: 0.6 sccm, O2: 10 sccm, Ar: 40 sccm) and Mo gate electrode of 300 nm thickness was deposited by sputtering. Patterning gate electrodes was carried out by lithography and wet etching (H3PO4:HNO3:CH3COOH:H2O = 400:25:50:25), followed by self-aligned source and drain formation by As ion implantation (ion dose: 2 x 1015 cm-2, accelerating voltage: 66 kV) using the Mo gate as mask. Activation annealing treatment was performed at 550 oC in N2 ambient for 30 minutes. Before SiO2 insulator film of 600 nm was deposited by Atmospheric Pressure Chemical Vapor Deposition (APCVD), sacrificial SiO2 in source and drain region was etched by BHF. Contact hole was formed by lithography and BHF wet etching. Mo metal pad of 700 nm thickness was deposited by sputtering and patterned by lithography and wet etching. Finally, the sample was annealed at 400 oC in H2 ambient for 30 minutes. The highest temperature of the fabrication processes was 550 oC. The devices were designed with the width and length of channel of W = 10 µm and L = 10 µm, respectively. Figure 1 shows microphotograph of poly Si film and schematic of TFT designed mask. This result reveals that poly-Si film was periodic in 200 µm and the channels were fabricated parallel with scanning direction in 10 groups at different positions. In particular, TFTs of group 1 were fabricated along heavy-void regions and distance of two consecutive groups was 20 µm in perpendicular direction of laser scan. Figure 2 shows an EBSD mapping of the laser-crystallized poly-Si films. It was found that (100) Si crystal grains with an average size of 20 µm x 2 µm were formed. In this figure, crystal orientation of the poly-Si film was different from the middle to the side of the measured region. As result, characteristics of TFTs was relatively different in each group. Table I indicates average mobility, maximum mobility, and variation of TFTs in 10 groups. TFTs with ultrahigh electron field effect mobility (µFE ) of over 1000 cm2/Vs in a linear region was realized. A high average electron field effect mobility of 636 cm2/Vs and its low variation of 25% were achieved in group 7 in which (100) Si crystal grains were dominant. Figure 3 shows IDS-VGS characteristics of poly Si TFTs in group 7. A high off-leakage current and its high variation of 10-10 – 10-6 were observed owing to trap states in both the grain boundaries and crystal grains. Table I.Average mobility of TFTs and their variation in each group Group Average mobility (cm2/Vs) Maximum mobility (cm2/Vs) Standard deviation (cm2/Vs) 1 2 3 4 5 6 7 8 9 10 270 490 453 476 510 590 636 600 632 618 512 1010 780 717 697 873 971 940 973 808 114 264 131 148 79 167 159 194 183 118 Figure 1

Study on Characteristics of Poly-Si TFTs With 3-D Finlike Channels Fabricated by Nanoimprint Technology

This study addresses the characteristics of polycrystalline-silicon thin-film transistors (poly-Si TFTs) with 3-D finlike channels fabricated using ultraviolet nanoimprint lithography. The poly-Si 3-D finlike channels with a line width/space ratio of about $\sim$ 1 : 1 were fabricated and studied by scanning electron microscope and transmission electron microscopy. The poly-Si TFTs with 3-D finlike channels, fabricated using the nanoimprint technique, have superior performances in comparison to that with the single channel. Besides, the characteristics of poly-Si TFTs, such as the transfer characteristics, output drain current, transconductance, on/off current ratio, subthreshold swing, and field-effective mobility, with respect to the width/space/height of 3-D finlike structures were also investigated. The proposed approach can be utilized to fabricated high-performance poly-Si TFTs or high-sensitivity biosensors at low cost.

A numerical analysis of the electrical characteristics of small-grains poly-Si TFTs

Voltage characteristics of polysilicon thin films transistors (Poly-Si TFTs) are related to basic material and device parameters. Understanding and modeling the electrical behavior of poly-Si TFT require knowledge of equivalent properties of polysilicon which are strongly affected by defects present in this material. A numerical analysis, which studies the electrical characteristics of small-grains poly-Si TFTs, has been investigated. The density of states (DOS) in the band gap is modeled by assuming an exponential distribution of deep and tail states. The proposed model evaluates the influence of both deep and tail states on the electrical conduction process and the dominant contribution of tail states on the threshold voltage values while the deep states in the middle of polysilicon gap controls the lower threshold regime. The surface potential and ON/OFF current ratio are also calculated. The comparison of the generated current-voltage characteristics obtained from numerical simulation TCAD-ATLAS with those reported in the literature show a good agreement.

Metal induced crystallized poly-Si Thin Films and Thin Film Transistors

Metal induced crystallization of a-Si was implemented by using nickel salt solution, nickel silicon oxide mixture, and a nano-layer of SiO2 mask. By using salt solution to form nickel media, the crystallization of a-Si started from many isolated sites and proceeded along radial directions at the isotropical crystallization rate under the optimized soaking conditions. By using nickel silicon oxide mixture, the crystallization of a-Si behaved an effect of self-controlled release of nickel, the poly-Si had low nickel residua under the induce holes and at the domain boundaries. By using a nano-layer of SiO2 mask to pre-define nucleation lines, the poly-Si composing of continuous zonal domain in exactly same width was obtained, the crystallization of a-Si started from some isolated sites inside the inducing windows, then proceeded along radial/lateral direction outside the windows. The characteristics of poly-Si TFTs made with these three different schemes were analyzed.

Low frequency noise modeling of polycrystalline silicon thin-film transistors

A modified and improved low frequency model for polycrystalline silicon thin-film transistors (poly-Si TFTs) is developed in this paper. For small grain size poly-Si TFTs, based on carrier number fluctuations, an improvement of the standard low frequency noise model has been investigated to explain the noise characteristics of poly-Si TFTs. An exponential energy distribution for interface density of states is employed to model the interface trap capacitance. For large grain size devices, mobility fluctuations related to fluctuations of the grain boundary charges is used to describe the excess subthreshold noise. The anomalous noise increase behavior of poly-Si TFTs when operated in the kink regime is also studied and modeled. The proposed model and the experimental data agree well over a wide range of operation regimes.

High-Performance Poly-Silicon TFTs Using a High-$k$ $\hbox{PrTiO}_{3}$ Gate Dielectric

In this letter, a polycrystalline-silicon thin-film transistor (poly-Si TFT) with a high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> PrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric is proposed for the first time. Compared to TFTs with a Pr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric, the electrical characteristics of poly-Si TFTs with a PrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric can be significantly improved, such as lower threshold voltage, smaller subthreshold swing, higher <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> current ratio, and larger field-effect mobility, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density and low grain-boundary trap state. All of these results suggest that the poly-Si TFT with a high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> PrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric is a good candidate for high-speed and low-power display driving circuit applications in flat-panel displays.

Reduction of photoleakage current in polycrystalline silicon thin-film transistor using NH3 plasma treatment on buffer layer

The technology of polycrystalline silicon thin-film transistors (poly-Si TFTs) with low photoleakage current is developed in this work. The electrical characteristics of poly-Si TFTs under illumination were significantly improved employing the NH3 plasma treatment on the buffer layer, with no need for complicate device structure and additional masks. The trap states that originated from the plasma bombardment on the interface between the poly-Si layer and buffer oxide can effectively recombine the light-induced electron-hole pairs. The fewer residual electron-hole pairs lead to the lower photoleakage current and improved subthreshold swing, as well as maintaining good electrical characteristics in the dark sate.

High-Performance Poly-Si TFTs With $\hbox{Pr}_{2} \hbox{O}_{3}$ Gate Dielectric

In this letter, a polycrystalline silicon thin-film transistor (poly-Si TFT) with high-quality praseodymium oxide (Pr2O3) gate dielectric is proposed. Compared to TFTs with tetraethoxysilane gate dielectric, the electrical characteristics of poly-Si TFTs with Pr2O3 gate dielectric can be significantly improved, such as lower threshold voltage, lower subthreshold swing, triple ON/OFF current ratio, and a field-effect mobility that is about twice higher, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density by using a high-kappa gate dielectric. Therefore, the poly-Si TFT with Pr2O3 high-kappa gate dielectric is a promising candidate for high-speed and low-power display driving circuit applications in flat-panel displays.

Improved Electrical Characteristics of MILC Poly-Si TFTs Using Fluorine Ion Implanation

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Electrical Enhancement of Solid Phase Crystallized Poly-Si Thin-Film Transistors with Fluorine Ion Implantation

Solid phase recrystallized polycrystalline silicon thin-film transistors (SPC poly-Si TFTs) with fluorine ion implantation were investigated in this study. Electrical characteristics and reliability of the proposed poly-Si TFTs were improved effectively, especially for field effect mobility and off current. The fluorine-ion-implanted poly-Si TFT can suppress the hot carrier multiplication near the drain side, leading to superior endurance to electrical stress compared with conventional poly-Si TFTs. It was found that fluorine ions will pile up at the poly-Si interface during thermal annealing, without the initial deposition of pad oxide. The proposed technology is manageable and compatible with conventional poly-Si TFT fabrication. As the ion dosages increase more than , however, the electrical characteristics of poly-Si TFTs were degraded due to the increase of trap state density caused by the fluorine segregation in the poly-Si film.

Characterization of polycrystalline silicon thin films fabricated by rapid joule heating method

Polycrystalline thin film transistors (poly-Si TFTs) were fabricated using the 5-μs-rapid joule heating method. The optimum condition of 0.77 J/cm2 for crystallization was determined through analysis of transfer characteristics of poly-Si TFTs. The density of the tail-type defect states decreased from 1.4×1012 to 9.5×1011 cm-2 and the carrier mobility increased from 300 cm2/Vs to 760 cm2/Vs as the joule heating energy density increased from 0.68 to 0.77 J/cm2. The threshold voltage of the drain current ranged between 0.9 and 1.15 V.

27.2: Poly‐Si Thin‐Film Transistors Using Polysilazane‐Based Spin‐On Glass for All Dielectric Layers

AbstractPolycrystalline silicon thin‐film transistors (poly‐Si TFTs) with all layers of dielectric made from polysilazane‐based spin‐on glass (PS‐SOG) have been developed for the first time. The maximum annealing temperature of the PS‐SOG was at 400 °C. The electrical characteristics of poly‐Si TFTs with PS‐SOG as a gate dielectric are stable and the gate leakage current is sufficiently low. PS‐SOG is expected to realize CVD‐free deposition of dielectric layers and remarkable cost reduction of poly‐Si TFTs.

Improving reliability of poly-Si TFTs with channel layer and gate oxide passivated by NH 3/N 2O plasma

The polycrystalline silicon thin film and gate oxide of poly-Si TFTs were treated by NH 3/N 2O plasma or their combination to improve the reliability of TFTs. The poly-Si TFTs with and without NH 3/N 2O plasma treatment were characterized by measuring the transfer curves of poly-Si TFTs. The results showed that the characteristics of poly-Si TFTs treated with NH 3/N 2O plasma were greatly improved at hot-carrier stress and thermal accelerated tests. The reason is that nitrogen atoms terminate the dangling bonds and improve the characteristics of poly-Si TFTs.

Electrical characteristics of MILC poly-Si TFTs with long Ni-offset structure

We have observed that B/sub 2/H/sub 6/-doped amorphous silicon (a-Si) showed a faster growth rate of metal-induced lateral crystallization (MILC) than that of undoped a-Si. From the analysis of the microstructure, it was thought that boron atoms could help modify the growth behavior from that of a branched crystal network to unidirectional crystal growth with few branches and that growth rate could to be enhanced. By using this good crystalline structure at the boundary region between the source/drain and channel, we have successfully fabricated p-type poly-Si thin-film transistors with good electrical properties with a MILC process.

Metal-induced lateral crystallization of a-Si thin films by Ni-Co alloys and the electrical properties of poly-Si TFTs

We have introduced a new process in metal-induced lateral crystallization (MILC). By adding Co to the Ni-MILC process, the electrical characteristics of MILC poly-Si TFTs were considerably improved. In particular, a considerable decrease of TFT leakage current were achieved in both n-type and p-type devices.

P‐71: OLED Pixel Design Employing a Novel Current Scaling Scheme

AbstractA new active matrix organic light emitting diode (AMOLED) pixel design is proposed by employing a novel current scaling scheme and verified by SPICE simulation. The new pixel design scales down the data current more effectively to guarantee less charging time, compared with conventional current mirror structure, as well as compensates the variation of the electrical characteristics of poly‐Si TFTs, such as threshold voltage and mobility.

46.4: Oblique Incidence Excimer Laser Annealed (OI‐ELA) Poly‐Si TFTs for Eliminating Residual Source/Drain Junction Defects

AbstractWe report residual ion implantation damage at source/drain junctions of self‐aligned, excimer‐laser‐annealed poly‐Si TFTs. The laser irradiation intensity decreased remarkably at the junction due to diffraction of laser beam at gate electrode edge. We eliminated the junction defects by oblique‐incidence excimer laser annealing and improved the characteristics of poly‐Si TFTs.

Analysis of Narrow Width Effects in Polycrystalline Silicon Thin Film Transistors

In this study, narrow width effects of polycrystalline silicon thin film transistors (poly-Si TFTs) are investigated. With reducing channel width, TFT characteristics such as mobility, threshold voltage, and subthreshold swing are found to improve dramatically. To gain insight on the origin of the narrow width effects, a physically-based model is proposed to simulate the output characteristics of poly-Si TFTs. Excellent fitting with the experimental data is observed over a wide range of drain bias, gate bias, and channel width. Our model shows that both the deep state density and tail state density are reduced with reducing channel width, thus accounting for the improved TFT characteristics. In addition, subthreshold swings of poly-Si TFTs with various channel widths and lengths are compared. It is found that the subthreshold swings of poly-Si TFTs with the same channel area are identical, indicating that the grain-boundary trap density is reduced due to the reduction of channel area.

Development of a new design simulator for poly‐Si TFTs to optimize the lightly doped drain structure

Abstract—A new design simulator to simulate the characteristics of poly‐Si TFTs taking into account its physical structure was developed. By using the simulator, we can optimize the length and the sheet resistance of the LDD region in order to obtain sufficient ON currents and to suppress OFF currents under both dark and illuminated conditions.

Polycrystalline Silicon Thin Film Transistors Fabricated by Employing Selective Self Ion-Implantation and Excimer Laser Annealing

Polycrystalline silicon thin film transistors (poly-Si TFT’s) fabricated by excimer laser annealing (ELA) are promising devices for active-matrix liquid-crystal display (AMLCD) due to their high field-effect mobilities and low thermal budgets [1,2]. It is well known that the electrical characteristics of poly-Si TFTs depend on the grain size and the defect density of the poly-Si film. In the fabrication of low temperature poly-Si TFT’s, excimer laser annealing is considered as most a promising tool for preparing poly-Si films with low defect densities. However, grain size is very sensitive to the laser energy density, and nucleation takes place randomly [3,4]. Selective self ion-implantation (Si+) has also been reported as a tool for artificial nucleation prior to thermal annealing. If high-energy ion-implantation is employed, high-density defects and high-density nucleation can be provided artificially in amorphous silicon films [5]. In this paper, we propose a novel method to prepare good quality poly-Si films by employing selective self ionimplantation and ELA. We fabricated poly-Si TFT’s by employing the proposed method and confirmed the improved electrical characteristics of poly-Si films in both the onand the off-state through measurements of the TFT characteristics.