Characteristics Of Field Programmable Gate Array Research Articles

RingNet: A Memory-Oriented Network-On-Chip Designed for FPGA

In this paper, we identify the general requirements for network-on-chips (NoCs) and the general characteristics of field-programmable gate arrays (FPGAs) from leading producers. Based on the analysis provided, an FPGA-oriented NoC called RingNet is proposed. As a distinctive feature, RingNet uses communication through a centrally placed memory that aims at preventing network congestions and limiting the network buffer requirements. Optimal utilization of FPGA resources is one of the goals of RingNet development. Especially buffers are implemented in distributed RAM available in FPGAs, and the virtual cut-through is used as an efficient switching technique for FPGA. Simulations prove guaranteed throughput, predictable latency, and fair network access provided by RingNet. Synthesis results for sample FPGAs from Xilinx, Intel, and Lattice prove the universality of RingNet. The provided analysis of NoC implementations leads to the conclusion that RingNet needs fewer resources and supports higher clock frequencies than the widely used AXI4 architecture.

Real-Time Underwater Image Recognition with FPGA Embedded System for Convolutional Neural Network.

The underwater environment is still unknown for humans, so the high definition camera is an important tool for data acquisition at short distances underwater. Due to insufficient power, the image data collected by underwater submersible devices cannot be analyzed in real time. Based on the characteristics of Field-Programmable Gate Array (FPGA), low power consumption, strong computing capability, and high flexibility, we design an embedded FPGA image recognition system on Convolutional Neural Network (CNN). By using two technologies of FPGA, parallelism and pipeline, the parallelization of multi-depth convolution operations is realized. In the experimental phase, we collect and segment the images from underwater video recorded by the submersible. Next, we join the tags with the images to build the training set. The test results show that the proposed FPGA system achieves the same accuracy as the workstation, and we get a frame rate at 25 FPS with the resolution of 1920 × 1080. This meets our needs for underwater identification tasks.

Hardware Software Co-Design for JPEG Encoder Test Bench

This paper presents a hardware/software (HW/SW) co-design approach using System On a Programmable Chip (SOPC) technique to achieve Joint Photographic Experts Group (JPEG) algorithm. It firstly introduces JPEG image compression technology and the system architecture. Then the hardware/software design process of JPEG encoder test bench is introduced. It focuses on using the characteristics of Field-Programmable Gate Array (FPGA) structure to achieve JPEG algorithm including the improved Discrete Cosine Transform (DCT), and Nios II embedded processor of customizable characteristics, translating image acquisition, JPEG image compression and Thin Film Transistor Liquid Crystal Display (TFT-LCD) controller into user-defined modules according to Altera Avalon bus requirements with the SOPC Builder, where the user-defined module can be added to the system under the control of soft-core Nios II Embedded. Finally, the whole system is verified on a single FPGA chip. The experimental results shows the advantages of JPEG algorithm as a FPGA hardware module includes low power consumption, high image quality, low production costs and stable performance. There’s a very great practical significance to reduce costs and improve image processing speed.

Fingerprinting techniques for field-programmable gate array intellectual property protection

As current computer-aided design (CAD) tool and very large scale integration technology capabilities create a new market of reusable digital designs, the economic viability of this new core-based design paradigm is pending on the development of techniques for intellectual property protection. This work presents the first technique that leverages the unique characteristics of field-programmable gate arrays (FPGAs) to protect commercial investment in intellectual property through fingerprinting. A hidden encrypted mark is embedded into the physical layout of a digital circuit when it is placed and routed onto the FPGA. This mark uniquely identifies both the circuit origin and original circuit recipient, yet is difficult to detect and/or remove, even via recipient collusion. While this approach imposes additional constraints on the backend CAD tools for circuit place and route, experiments indicate that the performance and area impacts are minimal.