Channel Hot Carrier Reliability Research Articles

Impact of ALD TiN Capping Layer on Interface Trap and Channel Hot Carrier Reliability of HKMG nMOSFETs

In this letter, the effect of TiN capping layer on interface quality and the channel hot carrier (CHC) reliability of high-k/metal-gate (HKMG) nMOSFET was investigated. Experiments show that the fresh interface trap density was reduced from ${1.83}\times {10}^{{11}}$ to ${7.75}\times {10}^{{10}}$ cm−2 for 1.4 and 2.4 nm ALD TiN capping layers, respectively, while the CHC time-to-failure was worsened by 13%. Combining the chemical analysis by secondary ion mass spectroscopy and the characterization of active energy for trap generation, it is found that the extraordinary chlorine introduced by a ALD TiN capping layer deposition could be responsible for the improved fresh interfacial trap but degraded CHC reliability in HKMG nMOSFETs. The mechanism can be explained by the lower binding energy of Si–Cl than Si–H, which results in more interface passivation but easier to be broken by electrical stress. This finding can provide the guide for the optimization of HKMG process.

Impact of the Substrate Orientation on CHC Reliability in n-FinFETs—Separation of the Various Contributions

In this paper, we perform a comparative analysis of the degradation induced by a channel hot carrier (CHC) in bulk n-FinFETs with rotated (100) and nonrotated (110) sidewall surfaces. CHC degradation includes several components, and separating each contribution is necessary for identifying different mechanisms in devices with different surface orientations. First, the permanent and recoverable components are separated based on the recovery phenomenon after the CHC stress, ascribed to the electron detrapping from the oxide bulk defects. Then, the contribution of generated interface states to the permanent component is quantified by charge pumping measurements. The nonrotated bulk FinFETs showed higher threshold voltage degradation at the maximum bulk current stress condition due to the higher interface precursor defect density compared with the rotated devices. On the other hand, the rotated bulk FinFETs showed higher threshold voltage degradation at the stress condition of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> due to higher bulk defect trapping, ascribed to the lower physical oxide thickness.

Improvement of hot carrier reliability with deuterium anneals for manufacturing multilevel metal/dielectric MOS systems

This paper discusses new experimental findings critical for process integration of deuterium post-metal anneals to improve channel hot carrier reliability in manufacturing multilevel metal CMOS integrated circuits. Detailed account of the deuterium process optimization experiments varying temperature, time, and ambient is given. Specifically, the first demonstration of the large hydrogen/deuterium isotope effect for multilevel metal/dielectric MOS systems is reported. Previous accounts of the isotope effect had been limited to CMOS structures with one-level of dielectric/metal and to about a 10 fold improvement in reliability. Deuterium, instead of hydrogen is introduced via an optimized post-metal anneal process to achieve a 50-100 fold improvement in transistor channel hot carrier lifetime. The benefits of the deuterium anneal are still observed even if the post-metal anneal is followed by the final SiN cap wafer passivation process. It is concluded that the deuterium post-metal anneal process is suitable for manufacturing high performance CMOS products and fully compatible with traditional integrated circuit processes.

Channel hot-carrier stressing of reoxidized nitrided oxide p-MOSFETs

Channel hot carrier reliability of reoxidized nitrided oxide (RNO) and conventional oxide p-MOSFETs was studied. RNO p-MOSFET degradation is shown to be due to electron trapping, as in oxide devices. Since nitridation introduces electron traps, device lifetimes determined by static stress were found to be lower by 2-3 orders of magnitude in the RNO than in the oxide p-MOSFETs. However, circuit life is determined by the shortest-lived device type. For conventional oxide, circuit lifetime is determined by n-MOSFET lifetime. The authors demonstrate that both RNO n- and p-channel lifetimes are many orders of magnitude longer than oxide n-channel lifetimes; therefore, for submicrometer CMOS, use of RNO is predicted to increase circuit lifetime significantly. X-ray irradiations were found to degrade oxide p-channel hot carrier reliability far more strongly than RNO reliability. >

Effect of synchrotron X-ray radiation on the channel hot-carrier reliability of reoxidized nitrided silicon dioxide

Channel hot-carrier-induced degradation was studied in reoxidized nitrided oxide n-channel MOSFETs which were exposed to 1-2-keV X-rays from a synchrotron source. It is found that transconductance degradation under high gate bias stress (Vg=1.3 V/sub d/) is enhanced by the X-ray exposure to a lesser degree in reoxidized nitrided oxide (RNO) devices than in conventional oxide devices. This indicates that radiation generates fewer electron traps in RNO than in a conventional oxide. >