Reset Words Research Articles

Experimental research based on robot-assisted surgery: Lower limb fracture reduction surgery planning navigation system.

Lower extremity fracture reduction surgery is a key step in the treatment of lower extremity fractures. How to ensure high precision of fracture reduction while reducing secondary trauma during reduction is a difficult problem in current surgery. First, segmentation and three-dimensional reconstruction are performed based on fracture computed tomography images. A cross-sectional point cloud extraction algorithm based on the normal filtering of the long axis of the bone is designed to obtain the cross-sectional point clouds of the distal bone and the proximal bone, and the optimal reset target pose of the broken bone is obtained by using the iterative closest point algorithm. Then, the optimal reset sequence of reset parameters was determined, combined with the broken bone collision detection algorithm, a surgical planning algorithm for lower limb fracture reset was proposed, which can effectively reduce the reset force while ensuring the accuracy of the reset process without collision. The average error of the reduction of the model bone was within 1.0 mm. The reduction operation using the planning and navigation system of lower extremity fracture reduction surgery can effectively reduce the reduction force. At the same time, it can better ensure the smooth change of the reduction force. Planning and navigation system of lower extremity fracture reduction surgery is feasible and effective.

ПОРІГ ЗВОРОТНОСТІ ДЛЯ МОНОЇДІВ ПЕРЕТВОРЕНЬ

Motivated by the Cerny conjecture for automata, we introduce the concept of monoidal automata, which allows us the formulation of the Сerny conjecture for monoids. We obtain upper bounds on the reset threshold of monoids with certain properties. In particular, we obtain a quadratic upper bound if the transformation monoid contains a primitive group of permutations and a singular of maximal rank with only one point of contraction. Keywords: Cerny conjecture, finite automaton, finite monoid, transformation monoid.

High-Precision and Resilient-to-Interference Ultrawideband Two-Way-Ranging Based on Clock-Less Active Reflector in 65-nm CMOS

An impulse-radio ultrawideband (IR-UWB) two-way ranging (TWR) system for indoor and harsh environments is described. In the proposed system, a synchronization (sync) word with a specific sequence of UWB impulses and with a particular pulse-position modulation (PPM) is transmitted from the anchor and then detected by the tag using a continuous-time sync detection mechanism. Then, the tag instantaneously reflects a similar sync-word back to the anchor. Finally, the anchor detects the sync-word using the same continuous-time sync detection mechanism as the tag. The time of flight (ToF) between the transmitted sync and the received sync on the anchor is then calculated to measure the distance between the transmitter and the receiver. Unlike common TWR systems, here in the tag, a clock-less active reflector is used, which reduces sync detection and reply time and, hence, increases the ranging accuracy due to the mitigation of clock drift. To reduce narrowband interference (NBI) and multiuser interference (MUI), the sync-word uses a combination of ON–OFF keying (OOK) and PPM. The proposed sync-word detector continuously verifies the presence of UWB impulses having the correct time intervals. As a proof of concept, a 4-bit sync-word is utilized although the technique can be directly expanded to longer sync-words. The proposed system is fabricated using a 65-nm CMOS integrated circuit technology. Experimental results show the accuracy and resilience-to-interference (NBI and MUI) of the proposed TWR. The technique shows a 1.2-cm standard deviation for the accuracy of a single-measurement TWR in a semiclosed metal box using omnidirectional antennas.

Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture

The In-Memory Computing (IMC) architecture based on Conventional 6T, 8T, and 10T SRAM suffers from compute disturbance, compute-failure, and half-select issues, which affect the reliability of In-Memory Boolean Computation (IMBC) operations. To overcome these problems, local bit-line Shared pass-gate Dual-Port 8T (SDP8T) SRAM-based IMC architecture is proposed to perform energy-efficient IMBC operations. The local bit-line shared pass-gate structure addresses the half select issues with a small area overhead and achieves higher array efficiency by incorporating the bit-interleave architecture. The virtual-VSS write-assist is used in SDP8T SRAM to improve the write-margin yield (μ−3σ) by 48.99%, and multi-VTH technique improves Decoupled Read-Margin (DRM) yield by 5.26% when compared to DP8T SRAM. The Dynamical Reset Word Line (DRWL) scheme is proposed to resolve the sneak current problem and make the proposed IMC architecture more resilient to compute disturbance at non-read decouple paths during IMBC operations. Further, the Reference-based Reconfigurable Sense Amplifier (RRCSA) scheme is proposed to achieve reliable (compute-failure free) sensing for IMBC on four operands simultaneously in a single cycle, normal read, and Binary Content Addressable Memory (BCAM) operations. The 4 Kb SRAM array is implemented in 65-nm CMOS technology to analyze the SDP8T-IMC architecture. The operating frequency of 1190 MHz and average-energy consumption of 18.56 fJ/bit are achieved during IMBC operation at 1V. For BCAM operations, it achieves 0.60 fJ/search/bit energy consumption in the worst case (i.e., all data mismatch) at 1V. Cumulatively, the proposed SDP8T-IMC architecture has the highest figure of merits than the recently reported IMC architecture.

Deep reinforcement learning optimal control strategy for temperature setpoint real-time reset in multi-zone building HVAC system

Determining a proper trade-off between energy consumption and indoor thermal comfort is important for HVAC system control. Deep Q-learning (DQN) based multi-objective optimal control strategy is designed for temperature setpoint real-time reset to balance the energy consumption and indoor air temperature. In addition, this study develops an EnergyPlus-Python co-simulation testbed to evaluate DQN control strategy in a simulation environment. A case study experiment is conducted to evaluate the performance of DQN control strategy for real-time reset of supply air temperature and chilled supply water temperature setpoint in a multi-zone building VAV system. The developed EnergyPlus-Python co-simulation testbed is used to train and test the DQN control strategy for performance analysis. The applied DQN strategy leans to update control actions (i.e. temperature setpoint) through interaction with the simulation environment. Simulation results show that the DQN control strategy is effective in finding a proper trade-off between the energy consumption of HVAC system and indoor air temperature. Meanwhile, the DQN control strategy can find a proper temperature setpoint reset sequence in smaller training episodes, and the control actions can be stable after ten DQN training episodes. This study provides a preliminary direction of deep reinforcement learning control strategy for temperature setpoint real-time reset in multi-zone building HVAC systems.

Modulation Method for High-Capacity Fibre Channel Switch and High-Speed Pulse Network Data

Fibre channel (FC) switches are widely used in storage area networks and avionics systems. In this work, the FC protocol, the switching structure and the scheduling algorithm of the FC switch are deeply studied, and a 48-port FC switch is completed on a single-chip field-programmable gate array (FPGA). In addition, an improved scheduling algorithm for Inter-System Link Protocol (iSLP) is proposed for the input and scheduling of optical fiber pulse network data. On this basis, the overall architecture of the FC switch is proposed, the x690tffg1158 FPGA chip is selected, and the FC port control module is designed, which is composed of the receiving controller, the interface state machine, the sending controller, and the flow control. The routing table lookup module of FC switch is designed, the unicast routing table format and multicast routing table format are proposed, and the corresponding unicast and multicast routing table lookup table module architectures are designed. Aiming at the characteristics of high reliability and low distortion in the transmission of high-speed pulse network signals by FC switches, the modulation and demodulation of Bias-T (BIAS-T) are redesigned. The experiment is implemented using Verilog hardware description language (HDL), and Modelsim 10.5 software is adopted to simulate each module of the switch. The switch adopts an 8×N switching structure, which can accurately perform word synchronization. After the link is initialized, the transceivers can send and receive data frames normally. The redesigned BIAS-T is applied to solve the instability of the end of the analog modulation method, and then realize the low distortion and data integrity of the high-speed pulse signal of the FC switch.

Deep Learning Aided Blind Synchronization Word Estimation

In this paper, we address a blind frame synchronization problem where the receiver acts as an eavesdropper in the wiretap channel. A challenging condition is considered, where the receiver has completely no prior information except that an unknown synchronization word (SW) is repeated in a nonperiodic fashion. Although an autocorrelation method was proposed for the fixed frame length scenario, the scheme is not applicable to the variable-length scenario. To solve the problem, we propose a deep learning-aided blind SW estimation method where recurrent neural networks (RNNs) are used as a symbol predictor that predicts a symbol from an observation of preceding symbols. The prediction confidence of the RNN-based predictor is used for the localization of the SW symbols in the received signal. Two RNNs fed with the received signal forward and backward are used for accurate SW localization. It has been verified by simulation that the proposed schemes estimate the SW well when the amount of the received signal is sufficiently large. It is straightforward to get synchronization to the received signal with the correctly estimated SW.

A joint design method of frame synchronization code and LDPC code

Frame synchronization word (FSW) is an important basis in signal synchronization detection. In our work, the joint design of frame synchronization words and error correcting code are proposed which through regularly distributing the frame synchronization words among the information bits to improve the decoding performance of the LDPC. Frame synchronization word should be added to the information sequence corresponding to the position with the check matrix larger column weight which can guarantee that more Frame synchronization words are received by the check node in the decoding iteration. The frame synchronization word is known to the receiver which play an important role in decoding iteration. The results of simulation show that the algorithm makes an obvious improvement in decoding performance when the signal-noise ratio (SNR) is lower than 1 dB.

A Novel Data-Aided Frame Synchronization Method Based on Hough Transform for Optical Communications

In optical communication systems, frame synchronization is essential for subsequent operations, such as error correction and payload extraction. Various methods, so far, have been proposed in the published literature, but the performance is unsatisfactory under high bit error rate (BER) conditions. We present, in this work, a novel data-aided frame synchronization technique for optical packet transmission systems, in which the transmitter sends a sequence of packets with a specific synchronization word periodically inserted, and the receiver blindly recognizes the synchronization word to attain frame synchronization. The proposed algorithm detects the synchronization word based on Hough transform (HT), a classic method for line detection in digital image processing. The core principle of the algorithm is to exploit the periodicity of the frame synchronization word, which appears as black-and-white spaced stripes on a binary image when the frames are all aligned. Simulations are conducted over a 56Gbps optical QPSK transmission system, and the results show that our algorithm is still effective in attaining frame synchronization at a BER of 0.3. A comparison is also made between our algorithm and existed autocorrelation (AC)-based algorithm. The results demonstrate that our algorithm has a better error resilience performance. When the BER is higher than 0.03, our algorithm outperforms an AC-based algorithm significantly.

Algorithmic cooling based on cross-relaxation and decoherence-free subspace

Heat-bath algorithmic cooling (HBAC) has been proven to be a powerful and effective method for obtaining high polarization of the target system. Its cooling upper bound has been recently found using a specific algorithm, the partner pairing algorithm (PPA-HBAC). It has been shown that by including cross-relaxation, it is possible to surpass the cooling bounds. Herein, by combining cross-relaxation and decoherence-free subspace, we present a two-qubit reset sequence and then generate a new algorithmic cooling (AC) technique using irreversible polarization compression to further surpass the bound. The proposed two-qubit reset sequence can prepare one of the two qubits to four times the polarization of a single-qubit reset operation in PPA-HBAC for low polarization. When the qubit number is large, the cooling limit of the proposed AC is approximately five times as high as the PPA-HBAC. The results reveal that cross-relaxation and decoherence-free subspace are promising resources to create new AC for higher polarization.

Analysis of Blind Frame Recognition and Synchronization Based on Sync Word Periodicity

Blind recognition of communication parameters has been studied for various applications including cognitive radios, non-cooperative communications, electronic warfare, etc. In this article, the identification of frame information, such as frame length and synchronization word (SW), and frame synchronization, is addressed over the wiretap channel, where no prior information of the frame structure is available, but only the existence of a repeated SW is known. Modifying the previous study, we propose two blind frame recognition and synchronization algorithms based on the correlation between two distinct windows of the received signal as well as the mean of periodic samples. The algorithms run in two steps. A multiple of frame length is estimated via the correlation and then other frame parameters are acquired using the mean of periodic samples with the estimate. Asymptotic analysis of the first algorithm shows that the error probability of estimation vanishes as the received data increases both in noiseless and noisy transmissions. The second algorithm improves the performance in the limited received data scenario. Simulation results as well as complexity analysis of the proposed algorithm are also shown.

Parallel brute-force algorithm for deriving reset sequences from deterministic incomplete finite automata

A reset sequence (RS) for a deterministic finite automaton $\mathscr{A}$ is an input sequence that brings $\mathscr{A}$ to a particular state regardless of the initial state of $\mathscr{A}$. Incomplete finite automata (FA) are strong in modeling reactive systems, but despite their importance, there are no works published for deriving RSs from FA. This paper proposes a massively parallel algorithm to derive short RSs from FA. Experimental results reveal that the proposed parallel algorithm can construct RSs from FA with 16,000,000 states. When multiple GPUs are added to the system the approach can handle larger FA.

Reset Complexity of Ideal Languages Over a Binary Alphabet

We prove PSPACE-completeness of checking whether a given ideal language serves as the language of reset words for some automaton with at most four states over a binary alphabet. We compare the reset complexity and the state complexity for languages related to slowly synchronizing automata.

Trade-Off Between Frame Synchronization and Channel Decoding for Short Packets

We consider the transmission of successive packets where each packet consists of a frame synchronization word (SW), followed by coded symbols. For short packets, the header cost is no longer negligible and the SW design requires careful optimization. In particular, a trade-off arises depending on the way the total transmit power is split among the SW and the codeword. Assuming optimal finite-length codes, we develop tight approximations on the probability of false synchronization for several synchronization metrics and use them to characterize this trade-off. Simulation results and comparisons with 5G Polar codes show the relevance of the proposed optimization for short-packet communication system design.

Synchronization challenges in deep space communications

Deep space missions keep pushing for new frontiers affecting a wide spectrum of disciplines. To support the scientific achievements expected from new missions, communication technology is being pushed towards its limits [1]. A need to increase communication links data rate as well as to lower the operative signal-to-noise ratio (SNR) are identified. The adoption of advanced coding schemes such as turbo codes and low-density parity-check (LDPC) codes (e.g., Consultative Committee for Space Data Systems (CC-SDS) standards) allows receivers to operate at lower SNRs. However, in order to exploit the full potential of the coding gain, the receiver must be able to acquire and track a signal with a SNR much lower than expected in nominal conditions of state-of-the-art systems. The target operating point is given by the candidate LDPC codes [2], where the codeword error rate is set to WER ≤ 10−5, achieved at the bit energy to noise density ratio E b /N 0 ≥ 5.2 dB, ≥ 3.6 dB for LDPC(128,64) and LDPC(256,128), respectively. In [3] the first receiver bottleneck related with frame synchronization, a functionality required previous to channel decoding, was identified. Even though frame synchronization enhancements were proposed beyond standard correlation techniques [3], [4], [1], it was recommended to increase the synchronization word length in order to achieve the target performance. The recommendation was recently adopted by the CCSDS. In this work, the focus lies on the receiver synchronization stages (i.e., acquisition and tracking). Not only from a research standpoint, but also for the design of next generation Telemetry Tracking & Command (TT&C) transponders, it is of capital importance to understand the performance limitations of state-of-the-art deep space communications architectures, clearly identifying possible bottlenecks and the synchronization stages (i.e., acquisition and tracking) to be improved. Digital carrier and timing synchronization have been an active research field for the past three decades in applications such as satellite-based positioning or terrestrial wireless communications systems. In those scenarios, the limitations of standard delay, frequency, and phase-locked loop (delay-locked loop, frequency-locked loop (FLL), and phase-locked loop (PLL), respectively) architectures have been clearly overcome by Kalman filter (KF) based solutions [5], which provide an inherent adaptive bandwidth, robustness, flexibility, and an optimal design methodology. Despite the advances in the field, synchronization architectures for deep space communications links, implemented in current TT&C transponders, still rely on well-known conventional architectures, which may be insufficient if limits are pushed to extremely low SNR or harsh propagation conditions. With the advent of powerful software defined radio receivers and new system design rules, it is now possible to adopt new robust architectures that may enable going beyond the performance and reliability provided by legacy solutions.

A bound for the length of the shortest reset words for semisimple synchronizing automata via the packing number

We show that if a semisimple synchronizing automaton with $n$ states has a minimal reachable non-unary subset of cardinality $r\ge 2$, then there is a reset word of length at most $(n-1)D(2,r,n)$, where $D(2,r,n)$ is the $2$-packing number for families of $r$-subsets of $[1,n]$.

Pulsed Reset Protocol for Fixed-Frequency Superconducting Qubits

The unconditional and fast reset of fixed-frequency superconducting qubits is crucial for the operation of near-term quantum computers at elevated trigger rates. Many reset schemes are either conditional (depend on the qubit's state) or require flux tunability. This study presents an all-microwave pulsed reset sequence that uses the readout resonator to unconditionally empty a fixed-frequency transmon qubit, and that also reduces the qubit thermal population. This method could be used to increase the repetition rate of a superconducting quantum computer running, for example, variational eigensolvers requiring many measurements.

Strongly connected synchronizing automata and the language of minimal reset words

We approach the problem of finding strongly connected synchronizing automata with a given ideal I that serves as the set of reset words, by studying the set of minimal words M of the ideal I (no proper factor is a reset word). We first show the existence of an infinite strongly connected synchronizing automaton A having I as the set of reset words and such that every other strongly connected synchronizing automaton having I as the set of reset words is an homomorphic image of A. Finally, we show that for any non-unary regular ideal I there is a strongly connected synchronizing automaton having I as the set of reset words with at most (kmk)2kmkn states, where k is the dimension of the alphabet, m is twice the length of a shortest word in I, and n is the number of states of the smallest automaton recognizing M. This synchronizing automaton is computable and we exhibit an algorithm to compute it in time O((k2mk)2kmkn).

Between primitive and 2-transitive: Synchronization and its friends

An automaton (consisting of a finite set of states with given transitions) is said to be synchronizing if there is a word in the transitions which sends all states of the automaton to a single state. Research on this topic has been driven by the Černý conjecture , one of the oldest and most famous problems in automata theory, according to which a synchronizing n -state automaton has a reset word of length at most (n-1)^2 .The transitions of an automaton generate a transformation monoid on the set of states, and so an automaton can be regarded as a transformation monoid with a prescribed set of generators. In this setting, an automaton is synchronizing if the transitions generate a constant map. A permutation group G on a set \Omega is said to synchronize a map f if the monoid \langle G,f\rangle generated by G and f is synchronizing in the above sense; we say G is synchronizing if it synchronizes every non-permutation. The classes of synchronizing groups and friends form an hierarchy of natural and elegant classes of groups lying strictly between the classes of primitive and 2-homogeneous groups. These classes have been floating around for some years and it is now time to provide a unified reference on them. The study of all these classes has been prompted by the Černý conjecture, but it is of independent interest since it involves a rich mix of group theory, combinatorics, graph endomorphisms, semigroup theory, finite geometry, and representation theory, and has interesting computational aspects as well. So as to make the paper self-contained, we have provided background material on these topics. Our purpose here is to present recent work on synchronizing groups and related topics. In addition to the results that show the connections between the various areas of mathematics mentioned above, we include a new result on the Černý conjecture (a strengthening of a theorem of Rystsov), some challenges to finite geometers (which classical polar spaces can be partitioned into ovoids?), some thoughts about infinite analogues, and a long list of open problems to stimulate further work.

Subset Synchronization and Careful Synchronization of Binary Finite Automata

We present a strongly exponential lower bound that applies both to the subset synchronization threshold for binary deterministic automata and to the careful synchronization threshold for binary partial automata. In the later form, the result finishes the research initiated by Martyugin (2013). Moreover, we show that both the thresholds remain strongly exponential even if restricted to strongly connected binary automata. In addition, we apply our methods to computational complexity. Existence of a subset reset word is known to be PSPACE-complete; we show that this holds even under the restriction to strongly connected binary automata. The results apply also to the corresponding thresholds in two more general settings: D1- and D3-directable nondeterministic automata and composition sequences over finite domains.