Centric Designs Research Articles

Guest Editorial: IEEE Transactions on Emerging Topics in Computing Thematic Section on Memory- Centric Designs: Processing-in-Memory, In-Memory Computing, and Near-Memory Computing for Real-World Applications

The von Neumann architecture has been the status quo since the dawn of modern computing. Computers built on the von Neumann architecture are composed of an intelligent master processor (e.g., CPU) and dumb memory/storage devices incapable of computation (e.g., memory and disk). However, the skyrocketing data volume in modern computing is calling such status quo into question. The excessive amounts of data movement between processor and memory/storage in more and more real-world applications (e.g., machine learning and AI applications) have made the processor-centric design a severe power and performance bottleneck. The diminishing Moore's Law also raises the need for a memory-centric design, which is rising on top of the recent material advancement and manufacturing innovation to open a paradigm shift. By doing computation right inside or near the memory, the memory-centric design promises massive throughput and energy savings.

Use of 3D printing for home applications: A new generation concept

This paper presents the use of 3D printing for fabrication of household things and their repair purpose. 3D printing facility provide an opportunity to fabricate customized products as per the requirement of user. 3D printing technology can also be used for repairing of household things, such as Knife, mixer grinder jars, water purifier parts, sanitary products, uniform decorative etc. This study suggest that one can use desktop 3D printing facility at his/her home to full fill his/her passion and hobby to have customized products for his house such as Name plates, Key rings, Gift items, Soap case, earrings, pens, etc. Case studies to prove viability of 3D printing in this purpose has also been presented in this paper. Various customised user centric designs have been printed.

Analysis of Low Power Consumption Techniques on FPGA for Wireless Devices

In present scenario, the portable wireless devices like mobile phones are used by almost every human being for communication purpose. Mobile devices are equipped with a processing element that is responsible for performing all the controlling and computational tasks. Most of the computational tasks inside the processing element are performed by ALU circuit. ALU is considered as the computational engine and responsible for high power consumption. Previously, microprocessors and microcontrollers were the choice of designers but nowadays the horizon has been shifted to FPGAs and SOCs as a processing element in mobile devices. Obviously, FPGAs have numerous advantages over processors and the growing need of applications compels the designers to use FPGAs for fast processing. Although FPGAs fulfils the requirement of designers but they suffer from the disadvantage of high power consumption due to their complex circuitry. The demand of high performance and low power devices creates a bottleneck in front of designers specifically for battery operated portable wireless devices. So, this paper presents some power minimization techniques that can be applied on communication centric designs targeted to FPGAs. There are different techniques given in the literature but most of them are applied at device level only. This paper gives an insight to minimize the power at architectural level of design hierarchy using XPower Analyzer as a CAD tool. The proposed techniques are applied on arithmetic and logical unit circuit for analysis purpose, as ALU is the heart of processing elements used in portable wireless devices. The circuit has been verified and realized on XILINX ISE directed to Spartan 3E XC3S250E FPGA. The analysis illustrates significant improvement in the power consumption.

Special Issue on Human Centric, Universal and Interactive Design for Robotics and Mechatronics

According to the aged society in Japan, the expectation is high for the development of the human support robot or devices in daily life and in medical treatment and welfare. The human centered design and the universal design are very important concept for creating the useful human support devices. Human centric and universal designs are the designs of products and environments to be usable by all people, to the greatest extent possible, without the need for adaptation or specialized design. This special issue provides current researches and developments of human centric, universal and interactive design for robotics and mechatronics. Also, this special issue covers a broad range of research topics, such as human centric design, universal and interactive design, human machine interaction, transport system, housing environment system, rehabilitation devices, multi modal interface, evaluation of the usability, sensor/actuator technologies for assistive system, robotics and mechatronics to support elderly persons. We thank the authors for their fine contributions and the reviewers for their generous time and effort. In closing, we thank the Editorial Board of the Journal of Robotics and Mechatronics for helping make this issue possible.

GemDroid

As the demand for feature-rich mobile systems such as smartphones and tablets has outpaced other computing systems and is expected to continue at a faster rate, it is projected that SoCs with tens of cores and hundreds of IPs (or accelerator) will be designed to provide unprecedented level of features and functionality in future. Design of such mobile systems with required QoS and power budgets along with other design constraints will be a daunting task for computer architects since any ad hoc, piece-meal solution is unlikely to result in an optimal design. This requires early exploration of the complete design space to understand the system-level design trade-offs. To the best of our knowledge, there is no such publicly available tool to conduct a holistic evaluation of mobile platforms consisting of cores, IPs and system software. This paper presents GemDroid, a comprehensive simulation infrastructure to address these concerns. GemDroid has been designed by integrating the Android open-source emulator for facilitating execution of mobile applications, the GEM5 core simulator for analyzing the CPU and memory centric designs, and models for several IPs to collectively study their impact on system-level performance and power. Analyzing a spectrum of applications with GemDroid, we observed that the memory subsystem is a vital cog in the mobile platform because, it needs to handle both core and IP traffic, which have very different characteristics. Consequently, we present a heterogeneous memory controller (HMC) design, where we divide the memory physically into two address regions, where the first region with one memory controller (MC) handles core-specific application data and the second region with another MC handles all IP related data. The proposed modifications to the memory controller design results in an average 25% reduction in execution time for CPU bound applications, up to 11% reduction in frame drops, and on average 17% reduction in CPU busy time for on-screen (IP bound) applications.

Rapid design space exploration using legacy design data and technology scaling trend

Rapid and effective design space exploration at all stages of a design process enables faster design convergence and shorter time-to-market. This is particularly important during the early stage of a design where design decisions can have a significant impact on design convergence. This paper describes a methodology for design space exploration using design target prediction models. These models are driven by legacy design data, technology scaling trends and, an in situ model-fitting process. Experiments on ISCAS benchmark circuits validate the feasibility of the proposed approach and yielded power centric designs that improved power by 7–32% for a corresponding 0–9% performance impact; or performance centric designs with improved performance of 10.31–17% for a corresponding 2–3.85% power penalty. Evolutionary algorithm based Pareto analysis on an industrial 65 nm design uncovered design tradeoffs which are not obvious to designers and optimize both power and performance. The high performance design option of the industrial design improved the straight-ported design's performance by 29% with a 2.5% power penalty, whereas the low power design option reduced the straight-ported design's power consumption by 40% for a 9% performance penalty.