Cellular Neural Network Processor Research Articles

A universal concept based on cellular neural networks for ultrafast and flexible solving of differential equations.

This paper develops and validates a comprehensive and universally applicable computational concept for solving nonlinear differential equations (NDEs) through a neurocomputing concept based on cellular neural networks (CNNs). High-precision, stability, convergence, and lowest-possible memory requirements are ensured by the CNN processor architecture. A significant challenge solved in this paper is that all these cited computing features are ensured in all system-states (regular or chaotic ones) and in all bifurcation conditions that may be experienced by NDEs.One particular quintessence of this paper is to develop and demonstrate a solver concept that shows and ensures that CNN processors (realized either in hardware or in software) are universal solvers of NDE models. The solving logic or algorithm of given NDEs (possible examples are: Duffing, Mathieu, Van der Pol, Jerk, Chua, Rössler, Lorenz, Burgers, and the transport equations) through a CNN processor system is provided by a set of templates that are computed by our comprehensive templates calculation technique that we call nonlinear adaptive optimization. This paper is therefore a significant contribution and represents a cutting-edge real-time computational engineering approach, especially while considering the various scientific and engineering applications of this ultrafast, energy-and-memory-efficient, and high-precise NDE solver concept. For illustration purposes, three NDE models are demonstratively solved, and related CNN templates are derived and used: the periodically excited Duffing equation, the Mathieu equation, and the transport equation.

A Novel General and Robust Method Based on NAOP for Solving Nonlinear Ordinary Differential Equations and Partial Differential Equations by Cellular Neural Networks

This paper develops and validates through a series of presentable examples, a comprehensive high-precision, and ultrafast computing concept for solving nonlinear ordinary differential equations (ODEs) and partial differential equations (PDEs) with cellular neural networks (CNN). The core of this concept is a straightforward scheme that we call "nonlinear adaptive optimization (NAOP),” which is used for a precise template calculation for solving nonlinear ODEs and PDEs through CNN processors. One of the key contributions of this work is to demonstrate the possibility of transforming different types of nonlinearities displayed by various classical and well-known nonlinear equations (e.g., van der Pol-, Rayleigh-, Duffing-, Rössler-, Lorenz-, and Jerk-equations, just to name a few) unto first-order CNN elementary cells, and thereby enabling the easy derivation of corresponding CNN templates. Furthermore, in the case of PDE solving, the same concept also allows a mapping unto first-order CNN cells while considering one or even more nonlinear terms of the Taylor's series expansion generally used in the transformation of a PDE in a set of coupled nonlinear ODEs. Therefore, the concept of this paper does significantly contribute to the consolidation of CNN as a universal and ultrafast solver of nonlinear ODEs and/or PDEs. This clearly enables a CNN-based, real-time, ultraprecise, and low-cost computational engineering. As proof of concept, two examples of well-known ODEs are considered namely a second-order linear ODE and a second order nonlinear ODE of the van der Pol type. For each of these ODEs, the corresponding precise CNN templates are derived and are used to deduce the expected solutions. An implementation of the concept developed is possible even on embedded digital platforms (e.g., field programmable gate array (FPGA), digital signal processor (DSP), graphics processing unit (GPU), etc.). This opens a broad range of applications. Ongoing works (as outlook) are using NAOP for deriving precise templates for a selected set of practically interesting ODEs and PDEs equation models such as Lorenz-, Rössler-, Navier Stokes-, Schrödinger-, Maxwell-, etc.

Image processing applications via time-multiplexing cellular neural network simulator with numerical integration algorithms

A novel approach to simulate cellular neural networks (CNN) is presented in this paper. The approach, time-multiplexing simulation, is prompted by the need to simulate hardware models and test hardware implementations of CNN. For practical applications, due to hardware limitations, it is impossible to have a one-to-one mapping between the CNN hardware processors and all the pixels of the image. This simulator provides a solution by processing the input image block by block, with the number of pixels in a block being the same as the number of CNN processors in the hardware. The algorithm for implementing this simulator is presented along with popular numerical integration algorithms. Some simulation results and comparisons are also presented.

VLSI efficient discrete-time cellular neural network processor

Typical VLSI implementations of discrete-time cellular neural networks (DTCNN) incorporate costly hardware to implement the basic DTCNN cell, resulting in a small grid size that needs to be cascaded with many other chips for processing images of any practical size. In the paper, a low-cost DTCNN cell that can be incorporated into a single chip in large numbers has been proposed. Memory bandwidth considerations show that 256 DTCNN cells can be incorporated into a single chip DTCNN processor to compute a 256 /spl times/ 256 image at 30 frames per second. Techniques based on rectangular-shaped cell grids for use with video memory have been proposed to satisfy the memory bandwidth requirements. The architecture of the proposed DTCNN processor is also capable of supporting the flexible grouping of basic cells. In addition, the processor, which is capable of supporting the flexible grouping of cells, can be cascaded in a highly scalable manner to facilitate the processing of larger images at high speed.

A Programmable Imager for Very High Speed Cellular Signal Processing

In this paper a programmable imager with averaging will be described which is intended for averaging of different groups or sets of pixels formed by n × n kernels, n × m kernels or independent pixels of the array. This imager is a 64 × 64 array which uses passive pixels that can be randomly accessed. The read-outstage includes a sole charge amplifier with programmable gain, a sample-and-hold structure and an analog buffer. This read-out structure is different from other existing imagers with variable resolution since it uses a sole charge amplifier, whereas the normal structure is an operational amplifier per column plus a global operational amplifier. This structure will be described in detail indicating the advantages and disadvantages with respect to other imagers with averaging capabilities. This programmable resolution architecture can be more appropriate, and eventually, more efficient, when implementing very high speed Cellular Neural Network (CNN) processors in a CNN chipset—a mixed-signal hardware platform for CNN-based image processing. A significant processing time reduction can be obtained when decreasing the image resolution, and therefore the amount of information to be transferred to the CNN processor. This programmable resolution can also be used for fast image recognition and ulterior windowing at full resolution in a reduced area of the image, permitting a more accurate processing of the region of interest. In addition, full resolution images can still be obtained, as in commercial imagers which are usually included in CNN chipsets.

Architecture and Design of 1-D Enhanced Cellular NeuralNetwork Processors for Signal Detection

One-dimensional cellular array processor architecture and design for neural-based partial response (PR) signal detection are presented. Analog parallel computing approaches have many attractive advantages in achieving low power, low cost, and faster processing speed by its uniquely coupled parallel and distributed processing nature. In this paper, we describe the maximum likelihood sequence estimation (MLSE) algorithm for PR signals, the enhanced Cellular Neural Network (CNN) processor array architecture to realize the detection algorithm, and system performance evaluation. Analytical models and simulations on a design example of the detector have been employed to demonstrate the advantages of this scalable VLSI architecture. A processing rate of 265 Mbps was achieved for a prototype detector on a silicon area of 5.14 mm by 5.81 mm is a 1.2 µm CMOS technology. The processing rate can be beyond 1Gbps if it is implemented in the same amount of silicon area by using 0.5 µm CMOS technology. Such promising results clearly demonstrate the ability to meet the needs in future high speed data communication by VLSI realization of maximum likelihood sequence detectors based on the enhanced cellular neural network paradigm.