Gate Cell Research Articles

Low-Dimensional Polyoxometalate Molecules/Tantalum Oxide Hybrids for Non-Volatile Capacitive Memories.

Transition-metal-oxide hybrids composed of high surface-to-volume ratio Ta2O5 matrices and a molecular analogue of transition metal oxides, tungsten polyoxometalates ([PW12O40](3-)), are introduced herein as a charge storage medium in molecular nonvolatile capacitive memory cells. The polyoxometalate molecules are electrostatically self-assembled on a low-dimensional Ta2O5 matrix, functionalized with an aminosilane molecule with primary amines as the anchoring moiety. The charge trapping sites are located onto the metal framework of the electron-accepting molecular entities as well as on the molecule/oxide interfaces which can immobilize negatively charged mobile oxygen vacancies. The memory characteristics of this novel nanocomposite were tested using no blocking oxide for extraction of structure-specific characteristics. The film was formed on top of the 3.1 nm-thick SiO2/n-Si(001) substrates and has been found to serve as both SiO2/Si interface states' reducer (i.e., quality enhancer) and electron storage medium. The device with the polyoxometalates sandwiched between two Ta2O5 films results in enhanced internal scattering of carriers. Thanks to this, it exhibits a significantly larger memory window than the one containing the plain hybrid and comparable retention time, resulting in a memory window of 4.0 V for the write state and a retention time around 10(4) s without blocking medium. Differential distance of molecular trapping centers from the cell's gate and electronic coupling to the space charge region of the underlying Si substrate were identified as critical parameters for enhanced electron trapping for the first time in such devices. Implementing a numerical electrostatic model incorporating structural and electronic characteristics of the molecular nodes derived from scanning probe and spectroscopic characterization, we are able to interpret the hybrid's electrical response and gain some insight into the electrostatics of the trapping medium.

An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling

This letter introduces an analytical model to represent line-edge roughness (LER) effects on both off-state leakage and drive current for sub-100-nm devices. The model partitions a given device into small unit cells along its width, each unit cell assumes a constant gate length (i.e., cell's width is small compared to LER spatial frequency). An analytical model is used to represent saturated threshold voltage dependency on the unit cell's gate length. Using this technique, an efficient and accurate model for LER effects (through V/sub ts/ variations) on off-state leakage and drive current is proposed and experimentally validated using 193 and 248 nm lithography for devices with 80-nm nominal gate lengths. Assuming that the deviation from the ideal 0-LER case remains constant from generation to generation, the model predicts that 3 nm or less LER is required for 50-60-nm state-of-the-art devices in the 0.1-μm technology node. Based on data presented, we suggest that the LER requirement for this technology node is attainable with an alternated phase-shift type of patterning process.