Cell Area Overhead Research Articles

JCI-CAC: An Efficient Crosstalk Avoidance Code Considering Joint Capacitive and Inductive Effects

Capacitive coupling and inductive coupling are the two main factors in the occurrence of crosstalk fault in the communication bus. Among the various methods for reducing crosstalk fault, Crosstalk Avoidance Codes (CAC) codes are effective. However, with technology scaling, CACs are not able to prevent inductive effects. The proposed CACs methods are mainly based on capacitive coupling and do not consider inductive effects. To overcome this issue, a coding method is presented to avoid crosstalk fault called Joint Capacitive and Inductive CAC (JCI-CAC). The JCI-CAC coding reduces crosstalk faults by removing patterns of inductive coupling as ’11111’ and ’00000’ and capacitive coupling as ’10101’ and ’01010’. The JCI-CAC offers a new method to generate a new numerical system for data encoding that has a low computational overhead so that it can be used for any desired width of the communication bus. The simulation results of the proposed JCI-CAC mechanism are investigated in different criteria of delay, power consumption and area overhead. The simulation results provide less power consumption in JCI-CAC than other recent approaches. There have also been improvements in overhead area and critical paths in JCI-CAC coding. The main novelty of this paper is to provide a new numerical system and a new coding algorithm with minimum cell area overhead and power consumption, considering inductance coupling in addition to capacitive coupling. Based on simulation results, power consumption of JCI-CAC in the 8-bit and 16-bit bus is reduced by up to 20% compared to SOTA and FPF (PS-Fibo, S2AP, Improved Fibo-CAC, Fibo-CAC) codings. Also, cell area overhead in JCI-CAC compared to SOTA coding in an 8-bit bus is reduced by 4.8%.

Magnetic Nonvolatile SRAM Based on Voltage-Gated Spin-Orbit-Torque Magnetic Tunnel Junctions

This article proposes two different magnetic nonvolatile-static random access memory (MNV-SRAM) cell circuits for low-power, high-speed, and high-reliable backup operation with a compact cell area. They employ perpendicular magnetic tunnel junctions (p-MTJs) as nonvolatile backup storage elements and explore the spin-orbit torque (SOT) with the assistance of the voltage-controlled magnetic anisotropy effect (VCMA), referred to voltage-gated SOT (VGSOT), to perform the backup operation. By using an antiferromagnetic (AFM) layer that provides both an exchange bias and the SOT, no external magnetic field is required, making it suitable for practical applications. In addition, owing to the aid of the VCMA effect, the critical SOT write current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SOT</sub> ) for 1-ns backup operation can be reduced significantly, thus resulting in high speed, low power consumption, and high reliability. Moreover, such resulted I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SOT</sub> allows to be driven by the cross-coupled inverters in the SRAM cell, instead of a dedicated write driver, thereby leading to low cell area overhead. By using a commercial CMOS 40-nm design kit and a physics-based VGSOT-MTJ model, we have demonstrated their functionalities and evaluated their performance. Compared with previous SOT-based MNV-SRAM cell circuits, the proposed MNV-SRAM cell circuits can achieve lower backup energy dissipation, smaller backup delay, lower backup error rate and less cell area overhead without the assistance of the external magnetic field.

A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology

A new asymmetric 6T-SRAM cell design is presented for low-voltage low-power operation under process variations. The write margin of the proposed cell is improved by the use of a new write-assist technique. Simulation results in 65nm technology show that the proposed cell achieves the same RSNM as the asymmetric 5T-SRAM cell and 77% higher RSNM than the standard 6T-SRAM cell while it is able to perform write operation without any write assist at VDD=1V. Monte Carlo simulations for an 8Kb SRAM (256×32) array indicate that the scalability of operating supply voltage of the proposed cell can be improved by 10% and 21% compared to asymmetric 5T- and standard 6T-SRAM cells; 21% and 53% lower leakage power consumption, respectively. The proposed 6T-SRAM cell design achieves 9% and 19% lower cell area overhead compared with asymmetric 5T- and standard 6T-SRAM cells, respectively. Considering the area overhead for the write assist, replica column and the replica column driver of 2.6%, the overall area reduction in die area is 6.3% and 16.3% as compared with array designs with asymmetric 5T- and standard 6T-SRAM cells.

Selective State Retention Power Gating Based on Gate-Level Analysis

This work presents a novel approach based on gate-level analysis for implementing Selective State Retention Power Gating (SSRPG). A selective SRPG approach mitigates the area and power overhead of the conventional SRPG technique. However, only very few papers suggesting a selective SPRG approach were published. The proposed SSRPG technique employs a formal analysis and, therefore, does not require exhaustive simulations. To implement the new approach, an automatic algorithm, which is performed on a gate-level netlist, has been developed. This algorithm enables the extraction of a subset of flip-flops that is sufficient for a proper state retention power gating. Unique selective SRPG criteria have been defined to support the proposed algorithm. These criteria are used to reduce the total amount of the required retention cells. To the best of our knowledge, this is the first robust SSRPG approach using gate-level analysis for selecting a reduced sub set of FFs that require retention. The proposed approach has been applied to a practical design with about 3300 FFs. The experimental results show 78% reduction of the retention SPRG cell area overhead, compared to the common SRPG approach.

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

We propose shift-trim double-patterning lithography (ST-DPL), a cost-effective double-patterning technique for achieving pitch relaxation with a single photomask. The mask is re-used for the second exposure by applying a translational mask-shift. An additional non-critical trim exposure is applied to remove extra printed features. ST-DPL can be used to pattern critical layers and is very suitable for regular and gridded layouts, where redesign effort and area overhead are minimal. In this paper, the viability of ST-DPL is demonstrated through a design implementation at the poly and contacts layers in bidirectional layouts. Standard-cell layouts are constructed so as to avoid layout decomposition conflicts, which are found to be the limiting factor for the pitch relaxation that can be achieved with double patterning (ST-DPL as well as standard DPL). 2× pitch relaxation being associated with a considerable area overhead, 1.8 × pitch relaxation is achieved in our implementation while ensuring no layout decomposition conflicts and a small area overhead. Specifically, in comparison to layouts assumed to be feasible with a hypothetical single-patterning process, we observe virtually no area overhead when ST-DPL is applied to the poly layer (<; 0.3% cell-area overhead) and no more than 4.7% cell-area overhead when ST-DPL is applied at both the poly and contacts layers. The proposed method has many benefits over standard pitch-split double patterning: 1) cuts mask-cost to nearly half; 2) reduces overlay errors between the two patterns; 3) alleviates the bimodal line-width distribution problem in double patterning; and 4) slightly enhances the throughput of critical-layer scanners.

NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors

This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatile SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A V/sub dd//2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies.

A compact on-chip ECC for low cost flash memories

A compact on-chip error correcting circuit (ECC) for low cost flash memories has been developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC. The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND flash memory. The cumulative sector error rate has been improved from 10/sup -4/ to 10/sup -10/. By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated. As a result, the area for the circuit has been drastically reduced by a factor of 25. The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead. The power increase has been suppressed to less than 1 mA.