Cascode Technique Research Articles

A Capacitive-Feedback Amplifier with 0.1% THD and 1.18 μVrms Noise for ECG Recording

This paper presents an amplifier with low noise, high gain, low power consumption, and high linearity for electrocardiogram (ECG) recording. The core of this design is a chopper-stabilized capacitive-feedback operational transconductance amplifier (OTA). The proposed OTA has a two-stage structure, with the first stage using a combination of current reuse and cascode techniques to obtain a large gain at low power and the second stage operating in Class A state for better linearity. The amplifier additionally uses a DC servo loop (DSL) to improve the rejection of DC offsets. The amplifier is implemented in a standard 0.13 μm CMOS process, consuming 1.647 μA current from the supply voltage of 1.5 V and occupying an area of 0.97 mm2. The amplifier has a 0.5 Hz to 6.1 kHz bandwidth and 59.7 dB gain while having no less than a 65 dB common-mode rejection ratio (CMRR). The amplifier’s total harmonic distortion (THD) is less than 0.1% at 800 mVpp output. The amplifier can provide a noise level of 1.18 μVrms in the 0.5 Hz to 500 Hz bandwidth that the ECG signal is interested in and has 3.38 μVrms input-referred noise (IRN) over the entire bandwidth, so its noise efficiency factor (NEF) is 2.13.

Design of very low-voltages and high-performance CMOS gate-driven operational amplifier

This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 at 1MHz, the positive slew rate is 11.37 , the negative slew rate is 11.39 , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits.

A tunable low noise high PSRR high accuracy bandgap reference using stacked-long cascode technique in 14 ​nm FinFET process

A tunable CMOS bandgap reference circuit is presented. To improve the match performance of the current mirror, the proposed bandgap is realized with stacked-long Cascode technique. A detailed analysis of various error sources is provided and the techniques to reduce them are discussed. The bandgap reference with an accuracy of ±1.2% from −40 ​°C to 125 ​°C draws 57μA from a 1.8 ​V supply, and occupied 0.0036 ​mm2 in a 14 ​nm FinFET Process. The output noise is 0.76μV (rms) and the PSRR is −115dB@DC.

A 3.1–10.6 GHz UWB LNA Based on Self Cascode Technique for Improved Bandwidth and High Gain

In this work, we present a self cascode based ultra-wide band (UWB) low noise amplifier (LNA) with improved bandwidth and gain for 3.1–10.6 GHz wireless applications. The self cascode (SC) or split-length compensation technique is employed to improve the bandwidth and gain of the proposed LNA. The improvement in the bandwidth of SC based structure is around 1.22 GHz as compared to simple one. The significant enhancement in the characteristics of the introduced circuit is found without extra passive components. The SC based CS–CG structure in the proposed LNA uses the same DC current for operating first stage transistors. In the designed UWB LNA, a common source (CS) stage is used in the second stage to enhance the overall gain in the high frequency regime. With a standard 90 nm CMOS technology, the presented UWB LNA results in a gain $$\hbox {S}_{21}$$ of $$20.10 \pm 1.65\,\hbox {dB}$$ across the 3.1–10.6 GHz frequency range, and dissipating 11.52 mW power from a 1 V supply voltage. However, input reflection, $$\hbox {S}_{11}$$ , lies below $$-\,10$$ dB from 4.9–9.1 GHz frequency. Moreover, the output reflection ( $$\hbox {S}_{22}$$ ) and reverse isolation ( $$\hbox {S}_{12}$$ ), is below $$-\,10$$ and $$-\,48$$ dB, respectively for the ultra-wide band region. Apart from this, the minimum noise figure ( $$\hbox {NF}_{min}$$ ) value of the proposed UWB LNA exists in the range of 2.1–3 dB for 3.1–10.6 GHz frequency range with a a small variation of $$\pm \,0.45\,\hbox {dB}$$ in its $$\hbox {NF}_{min}$$ characteristics. Linearity of the designed LNA is analysed in terms of third order input intercept point (IIP3) whose value is $$-\,4.22$$ dBm, when a two tone signal is applied at 6 GHz with a spacing of 10 MHz. The other important benefits of the proposed circuit are its group-delay variation and gain variation of $$\pm \,115\,\hbox {ps}$$ and $$\pm \,1.65\,\hbox {dB}$$ , respectively.

Transformer Less High Voltage Gain Step-Up DC-DC Converter Using Cascode Technique

The objective of this work is to achieve high step-up voltage gain with appropriate duty ratio with the application of cascode technique on buck boost converters for electric energy conversion system. As the available electrical AC voltage cannot be directly fed to electronic power devices, these devices and load require DC Power conversion from AC voltage sources. Conventional boost converters are unable to provide high voltage gains due to the effect of power switches, the impact of the parasitic resistive components and the reverse-recovery problem of the diodes. In this paper high voltage gain step-up (HVGSU) DC-DC converter is proposed, which consists of two integrated buck-boost converters with a single switch. High voltage gain can be achieved using cascode technique without any extreme duty ratio, here the duty ratio of the switch is controlled using PWM technique. The simulation and hardware of the proposed converter is discussed in detail.

Ultralow-quiescent-current and wide-load-range low-dropout linear regulator with self-biasing technique for micropower battery management

In this paper, we present a 151 nA quiescent and 6.8 mA maximum-output-current low-dropout (LDO) linear regulator for micropower battery management. The LDO regulator employs self-biasing and multiple-stacked cascode techniques to achieve efficient, accurate, and high-voltage-input-tolerant operation. Measurement results demonstrated that the proposed LDO regulator operates with an ultralow quiescent current of 151 nA. The maximum output currents with a 4.16 V output were 1.0 and 6.8 mA when the input voltages were 4.25 and 5.0 V, respectively.

A COMPARATIVE STUDY OF DIFFERENT TYPES OF MIXER TOPOLOGIES

In this paper, a comparative study of different types of mixer topologies is presented. Gilbert cell is widely used as core of the mixer because it provides high conversion gain, good port-to-port isolation and low even-order distortion. It is found that the linearity of mixer is very good for Multi-Tanh technique by incorporating multiple differential trans-conductance stage but it reaches to very low conversion gain whereas, use of current bleeding technique increase linearity and conversion gain of the mixer by adding current source to increase the bias current at the expense of power consumption. A very low value of noise figure can be achieved with the switched biasing technique by replacing current source with parallel connected nMOS transistors but due to use of the transistor in place of tail current source, linearity is degraded and more power is consumed. Folded Cascode Technique is used to reduce DC supply voltage by folding the LO switching stage with pMOS transistors in switching stage but it degrades the noise figure. Bulk-driven technique can be employed to lower down the power consumption by providing the switching action via the gate of LO (RF) and amplification by the bulk of LO (RF) transistors, however it reduces the linearity. High linearity is obtained by using CCPD (Cross coupled post distortion) technique by cancelling of third order derivatives but it decreases the conversion gain and consume more power due to increase in the number of auxiliary transistors. MGTR enables to achieve high linearity by incorporating auxiliary transistor but it decreases the overall conversion gain and increases noise figure of the mixer. So it is observed that there is a trade-off among the performance metrics, i.e., conversion gain, noise figure linearity, and power consumption of the mixer.

Indirect frequency compensation technique using flipped voltage follower cell

ABSTRACTIn this paper, a useful frequency compensation technique for a three-stage fully differential amplifier with a recycling folded cascode (RFC) input stage structure is presented. The proposed compensation technique is based on using flipped voltage follower (FVF) cell in the RFC structure. This approach merges improved cascode and indirect compensation techniques that the output node of the FVF cell is used for the second one. The proposed circuit yields a higher gain bandwidth (GBW) than the other indirect compensation techniques at the cost of a more complex design procedure. This idea is simulated using 0.18 µm CMOS technology. Simulation results show a 125 dB DC gain, a 41 V/µs slew rate, a 44 MHz GBW, and a phase margin of 76°. The amplifier consumes 695 µW while driving a 30-pF load.

A High Performance Bulk Driven Quasi Floating Gate MOSEFT Based Current Mirror

A high performance low voltage bulk driven quasi floating gate MOS based current mirror has been proposed. The combination of bulk driven and quasi FGMOS decreases the input impedance upto 120Ω which is four times smaller than current mirror based on only bulk driven technique. The bandwidth has also been improved upto 173MHz which is three folds of bandwidth of conventional bulk driven current mirror. Very high output impedance upto 1GΩ is achieved using self cascode technique in output section depending the value of factor m. Small signal analysis of proposed circuit verifies the simulated results. The circuit is simulated using 0.18μm CMOS technology with supply voltage of ±0.3V. The proposed current mirror is highly suitable for low voltage applications.

A 5 V-to-3.3 V CMOS Linear Regulator with Three-Output Temperature-Independent Reference Voltages

This paper presents a 5 V-to-3.3 V linear regulator circuit, which uses 3.3 V CMOS transistors to replace the 5 V CMOS transistors. Thus, the complexity of the manufacturing semiconductor process can be improved. The proposed linear regulator is implemented by cascode architecture, which requires three different reference voltages as the bias voltages of its circuit. Thus, the three-output temperature-independent reference voltage circuit is proposed, which provides three accurate reference voltages simultaneously. The three-output temperature-independent reference voltages also can be used in other circuits of the chip. By using the proposed temperature-independent reference voltages, the proposed linear regulator can provide an accurate output voltage, and it is suitable for low cost, small size, and highly integrated system-on-chip (SoC) applications. Moreover, the proposed linear regulator uses the cascode technique, which improves both the gain performance and the isolation performance. Therefore, the proposed linear regulator has a good performance in reference voltage to output voltage isolation. The voltage variation of the linear regulator is less than 2.153% in the temperature range of −40°C–120°C, and the power supply rejection ratio (PSRR) is less than −42.8 dB at 60 Hz. The regulator can support 0~200 mA output current. The core area is less than 0.16 mm2.

Improved designs for current feedback op-amps

The performance of the current feedback op-amps (CFOAs) is very much determined by the input stage of CFOAs, including common-mode rejection ratio (CMRR). Two new CFOAs topologies are presented in this article: one topology uses a cascoding technique, and the second one uses a bootstrapping technique, both of which provide a much better CMRR and lower DC offset voltage than the conventional CFOAs. Moreover, the new CFOAs design exhibits an extended high frequency bandwidth, with a gain accuracy improvement. Applications requiring constant bandwidth with variable (closed loop) gain will benefit from the proposed topologies.

4 × 25 Gb/s 2.6 mW/Gb/s parallel optical receiver analog front‐end for 100 Gb/s Ethernet

ABSTRACTA design of 4 × 25 Gb/s parallel optical receiver analog front‐end, including transimpedance amplifier (TIA) and limiting amplifier (LA), is presented in this article. It features a pseudodifferential TIA structure to cancel common mode noise and stabilize circuit. The TIA and LA use regulated cascode technique and four stages interleaving active feedback structure to acquire 23.2 GHz bandwidth and 74.3 dBΩ transimpedance gain. The parallel TIA and LA chip occupies 525 × 1835 μm2 area. It consumes 76 mW per channel and the power consumption per bit is only 2.6 mW/Gb/s. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:974–978, 2015

Analog Implementation of Wavelet Transform in Switched-Current Circuits with High Approximation Precision and Minimum Circuit Coefficients

This paper presents a novel procedure for analog implementation of wavelet transform in switched-current (SI) circuits. An improved hybrid PSO---SQP optimization is employed to precisely approximate the impulse response of a filter to the wavelet base function in time domain. The SI first- and second-order section circuits with minimum coefficients are designed based on infinite-impulse-response digital filter technology. Cascode techniques are occupied to reduce the effects of parasitic elements. Based on these SI first- and second-order section circuits, a parallel wavelet circuit structure is presented to synthesize the approximated wavelet base function. By adjusting the switch clock frequency, the wavelets at different scales can be realized. The Gaussian wavelet is selected as an example to illustrate the design procedure. Simulation results demonstrate the feasibility of the proposed procedure for analog wavelet transform in SI circuits.

Design of InP DHBT power amplifiers at millimeter-wave frequencies using interstage matched cascode technique

In this paper, the design of InP DHBT based millimeter-wave(mm-wave) power amplifiers(PAs) using an interstage matched cascode technique is presented. The output power of a traditional cascode is limited by the early saturation of the common-base(CB) device. The interstage matched cascode can be employed to improve the power handling ability through optimizing the input impedance of the CB device. The minimized power mismatch between the CB and the common-emitter(CE) devices results in an improved saturated output power. To demonstrate the technique for power amplifier designs at mm-wave frequencies, a single-branch cascode based PA using single-finger devices and a two-way combined based PA using three-finger devices are fabricated. The single-branch design shows a measured power gain of 9.2dB and a saturated output power of 12.3dBm at 67.2GHz and the two-way combined design shows a power gain of 9.5dB with a saturated output power of 18.6dBm at 72.6GHz.

0.013 mm2 and Low‐power 10 Gb/s Transimpedance Amplifier for Short‐reach Optical Interconnects

ABSTRACTA transimpedance amplifier (TIA) has been designed and implemented for short‐reach optical interconnect applications. The TIA, which is based on the regulated cascode technique, is implemented with a bandwidth enhancement technique, where capacitive degeneration and resistive feedback has been exploited in a 0.13 μm CMOS technology, while maintaining a small chip area and low power consumption. The TIA showed a measured transimpedance gain of 51dBΩ and works up to 10 Gb/s in the presence of 0.3 pF input photodiode capacitance. It occupies an active area of 0.013 mm2 with a power dissipation of 4.3 mW. The proposed TIA achieved high gain‐bandwidth product per DC power (GBP/DC) figure of merit of 589 GHzΩ/mW with an input referred noise of 20 pA/√Hz. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2484–2487, 2013

An improved 860–960 MHz fully integrated CMOS power amplifier designation for UHF RFID transmitter

An improved design of 860–960MHz fully integrated CMOS power amplifier (PA) for UHF RFID transmitter is presented in this paper. It utilizes three stage differential structure, including common-source structure applying RC feedback circuit to improve linearity, cascade structure adopting self-biased cascode technique and self-forward-body-bias (SFBB) technique to overcome shortcomings of low breakdown voltage and to reduce supply voltage respectively in order to obtain high output power, high efficiency and low supply voltage. By integrating these techniques organically, simulation results demonstrate that the circuit provides 21dBm output power and 35% power-added efficiency (PAE) with 3V supply. A comparison with other PAs operating in similar frequencies shows the proposed LNA has advantages of higher output power, higher PAE, higher linearity and lower supply voltage.

High speed low power FEE for silicon detectors in nuclear physics applications

A high speed, low power and programmable readout front-end system is presented for silicon detectors to be used in nuclear physics applications. The architecture consists of a folded cascode charge sensitive amplifier, a pole-zero cancellation circuit to eliminate undershoots and a shaper circuit with Gm-C topology. All building blocks include a regulated cascode technique based gain enhancement. Experimental results show that the whole front-end system can be programmed for peaking times of 100ns, 200ns and 400ns maintaining the amplitude of the output voltage. Programmability is achieved by switching different resistors for all poles and zeros. The system has been designed in a 130nm CMOS technology and powered from a 1.2V supply. The output pulse has peak amplitude of 200mV for an input energy of 5MeV from the detector. A power consumption low noise tradeoff will be considered.

Self Cascode: A Promising Low Voltage Analog Design Technique

Two current mirror (CM) structures incorporating the self cascode (SC) technique for low voltage (LV) analog and mixed mode circuits are proposed. One CM is implemented by 4 MOSFETs, has output resistance of 0.3 M? and bandwidth of 1.2 GHz, while the other requires 8 MOSFETs, has output resistance of 15 M? and bandwidth of 1.1 GHz. Both can operate at ± 0.5 V. P-Spice simulations confirm the high performance of these CMs in comparison with the conventional and regulated structures.A small part of this paper is similar to the one that appeared in WASET-Vienna, Aug 13-15, 2008, Conference Proceedings

A 52-GHz 8.5-dB Traveling-Wave Amplifier in 0.13-$\mu$m Standard CMOS Process

The design of a traveling-wave amplifier (TWA) in 0.13-mum standard CMOS technology is presented. It is designed to maximize the gain-bandwidth product (GBP). An asymmetric cascode, coplanar waveguide (CPW), and loss compensation technique enables maximization of the TWA GBP. Design and modeling of 90-Omega CPW used to synthesize inductors of the TWA lines is presented. Simulations with a design kit and developed models for CPW show a 52-GHz bandwidth with a maximum power gain of 8.5 dB at 10 GHz for a 135-mW power consumption. Measurements up to 40 GHz confirm these results.

Switched-Current Sinusoidal Oscillators—Single Phase and Multiphase

Circuit designs of sinusoidal switched-current oscillators (SIOs) both single phase and multiphase are presented. First, a novel SIO is proposed. This SIO features simpler configuration and hence fewer transistors and connections, and faster building up of stable oscillation amplitude than those proposed in earlier works. Then, new design schemes of multiple-phase sinusoidal SIOs are introduced. Both even and odd phase SIOs can be implemented using the schemes described. Finally, cascode techniques, S^{2}I memory cell, dummy switches and balanced structure are applied to our SIOs to get high precision SIOs. The circuit operations of all SIO proposed have been validated by transistor level SPICE simulations.