Carry-lookahead Adder Circuit Research Articles

A new nano-design of 16-bit carry look-ahead adder based on quantum technology

There is a requirement and a desire to develop reliable and energy-efficient circuit designs that adapt to the expanding field of low-power circuit engineering in the VLSI domain based on nanotechnology. The quantum-dot cellular automata (QCA) technology possesses the potential to supplant the conventional, complementary metal-oxide-semiconductor (CMOS) technology in low-power nano-scale applications due to its diminutive cell dimensions, dependable circuitry architecture, and robust structural integrity. On the other hand, the carry look-ahead adder (CLA) is one of the vital circuits in digital processing utilized in diverse digital applications. In addition, for the design of this essential circuit, the occupied area and the delay play the primary role because using a simple formulation can reduce the occupied area, energy consumption, and the number of gates count. In the previous structures, high delay and use of traditional technology (like CMOS) caused an increase in the number of gate counts and occupied areas. Using QCA technology, simple quantum cells, and a low delay, all the previous shortcomings can be resolved to reduce the number of gate counts and low occupied area in the CLA circuit. This paper proposes a new method that helps the propagation characteristics generate suitable signals to reduce the number of gate counts based on adders in QCA technology. Several new blocks are used to design fast binary adders. Finally, an optimal four and 16-bit CLA circuit will be proposed based on the adder circuit. Furthermore, the execution and experimentation of outcomes are carried out utilizing QCADesigner-2.0.3. The simulation-based comparison of values justified the proposed design’s accuracy and efficiency. The simulation results demonstrate that the proposed circuit has a low area and quantum cell.

Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms

Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In addition to performance enhancement, transistor count require for the proposed design is quite less compared to the conventional design which result in less surface area on chip. Moreover, less transistor count accounts for less power dissipation. Hence, utilizing the proposed design in modern high-performance computing systems would bring about high-performance improvements.

Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)

This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential circuits using energy recovery technique suitable for memory circuits, (ii) an adiabatic carry look ahead adder (CLA) designed using 2PADL to study the speed performance and to prove its energy efficiency across a range of frequencies and (iii) a multiplier circuit using 2PADL compared against CMOS counterpart. The CLA adder is also implemented using the other static adiabatic logics, namely, quasi static energy recovery logic (QSERL), clocked CMOS adiabatic logic (CCAL) and conventional static CMOS logic to compare against 2PADL and validate its power advantages. The performance of the CCAL logic is tested for higher frequencies by implementing the widely presented CLA circuit. The result proves that the design is energy efficient and operates up to the frequency of 600 MHz. The simulation was carried out using industry standard Cadence® Virtuoso tool using 180[Formula: see text]nm technology library files.

Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits

In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better Ion and Cg,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices.

A Structured Approach for Optimizing 4-Bit Carry-Lookahead Adder

This paper presents a comparative research of low-power and high-speed 4-bit full adder circuits. The representative adders used are a ripple carry adder (RCA) and a carry-lookahead adder (CLA). We also design a proposed carrylookahead adder (PCLA) using a new method that uses NAND gate for modification which helps in reducing the powerdelay product (PDP) for high performance applications. To yield more realistic rise and fall times in the simulations, layouts have been made in a 0.13 􀀁m process for the RCA circuit, CLA circuit and PCLA circuit. The layouts designed were simulated by HSPICE based on 130 nm CMOS technology at 1.2 V supply voltages. Four sets of frequencies were operated: 10 MHz, 50 MHz, 100 MHz and 500 MHz with 50% duty cycle in different technology corner models. A comprehensive comparison and analysis were also carried out to test the performance of the adders. The three adders also yield different performances in terms of power consumption, PDP, and area. The simulation results of this research are expected to help designers to select the appropriate 4-bit adder cell that meets their specific applications.

Mechanical Verification of Adder Circuits using Rewrite RuleLaboratory

A methodology for mechanically verifying generic adder circuits is proposed using the rewrite-rule based theorem prover {\it Rewrite\ Rule\ Laboratory} ({\it RRL}). Proofs of properties of adder circuit descriptions are done by rewriting and induction. Carry lookahead adder circuit is described using {\it powerlists}, a data structure introduced by Misra to support {\it divide-and-conquer} strategy used for designing data-parallel algorithms. This description uses an algorithm for {\it parallel\ prefix} computation on powerlists due to Adams. Reasoning about properties of this algorithm can be of independent interest since parallel prefix operator has been found useful in many data-parallel algorithms. The correctness of the carry-lookahead adder (i.e., the adder indeed implements addition on numbers) is established by showing its equivalence to a recursive description of the ripple-carry adder, which is shown to correctly implement addition on natural numbers. The ripple carry adde r circuit is described in two different but equivalent ways: using powerlists employing the divide-and-conquer strategy, as well as using linear lists employing the linear decomposition strategy. The description of the ripple carry adder using powerlists is useful for showing equivalence of its input-output behavior to that of carry lookahead adder, whereas the description using linear lists is useful for showing its correctness with respect to addition on natural numbers. Descriptions of adder circuits using powerlists are based on Adams‘ work who also gave a hand proof of their correctness using the powerlist algebra. The emphasis in this paper is to {\it generate\ proofs\ mechanically\ by\ a\ theorem\ prover} . {\em RRL} exploits the algebraic laws of the powerlist algebra as rewrite rules, and uses heuristics for mechanizing proofs by induction using the cover set method to generate such proofs. The regularity in hardware circuits gets refl ected in compact descriptions generated using the divide-and-conquer strategy as well as in mechanically generated proofs by induction. Mechanical proofs generated by {\em RRL} closely follow the well-crafted hand-proofs which is quite encouraging. A comparison with Adams‘ hand generated proof is also made. There is strong evidence that the proposed methodology for generating proofs should scale up for large circuits exhibiting regularity that can be described using divide-and-conquer strategy in terms of powerlists.