Carrier-based Pulse Width Modulation Technique Research Articles

Design and implementation of single DC-link based three-phase multilevel inverter with CB-PWM techniques

Simulation and implementation of a single DC-link-based three-phase inverter are investigated in this article. The primary focus is on designing a single DC-link three-phase inverter for high power applications. Unlike conventional inverters that require 600 V to generate 400 V (RMS) at the output, the proposed system achieves this with only 330 V, facilitated by a 12-terminal 1:1 transformer. The system employs Proportional Integral (PI) and Neural Network (NN) controllers to optimize performance. Various Carrier-Based Pulse Width Modulation (CB-PWM) techniques, including Phase Disposition (PD), Phase Opposition Disposition (POD), and Alternative Phase Opposition Disposition (APOD), are implemented and evaluated based on Total Harmonics Distortion (THD) concerning the Modulation Index (MI) of the inverter. The proposed inverter achieves a THD reduction to 4.8%, demonstrating superior performance compared to recent studies. The system’s performance is validated through extensive MATLAB/Simulink simulations and practical implementation using XILINX FPGA software, confirming the efficacy of the proposed design.

A new single modulating and single carrier signal based control technique for symmetrical and asymmetrical multilevel inverter topology

Abstract In literature, to generate gate pulses for any inverter topology, most of the authors are using a single modulating signal with (level-1) or (level-1)/2 carrier-based pulse width modulation (PWM) techniques and single carrier (SC) signal with (level-1)/2 modulating signal based PWM techniques. Then, while going to higher-level inverter topologies, the complexity of the PWM control approach in both cases can increase. To reduce the control complexity, few authors have reported a single modulating signal with single carrier-based PWM techniques. However, these techniques need more mathematical equations and if-else loops. This article proposes a new single-modulating and single-carrier signal-based generalized PWM control approach using floor function (FF). This technique has been verified by considering one of the single-phase conventional symmetrical and asymmetrical multilevel inverter (MLI) topologies. Generally, FF rounds the value to the nearest integer towards the negative infinity. The proposed PWM control implementation process is very simple and suitable for both high switching frequency (HSF) and low switching frequency (LSF) operations. The proposed control technique (PCT) has been experimentally verified with different steady-state and transient-state studies of results under standalone operation.

A CB-PWM Technique for Eliminating CMV in Multilevel Multiphase VSI

A generalized Carrier-Based Pulse Width Modulation (CB-PWM) scheme is proposed here for the elimination of common-mode voltage (CMV) in a multilevel multiphase voltage source inverter (VSI). In this CB-PWM scheme, the switching function of x-level, q-phase VSI is obtained from the switching function of virtual y-level and (y+1) level, q-phase VSI, where y = (x+1)/2 when x is odd and y = x/2 when x is even. It is established here that the pole voltages of q-phase x-level VSI thus obtained generate zero CMV. The proposed CB-PWM technique is computationally less intensive and hence can be easily implemented in hardware. Extensive simulation and experimental results are presented to validate the proposed CMV elimination technique in 3-phase 7-level VSI, 5-phase 5-level VSI, and 6-phase 4-level VSI. A comparative study of the proposed PWM scheme with the existing technique shows the superiority of the proposed technique in eliminating CMV.

A New Level Shifted Carrier Based PWM Technique for a Cascaded Multilevel Inverter Based Induction Motor Drive

The pulse width modulation (PWM) techniques are becoming the game changer for multi-pulse power converter fed multilevel inverter-based induction motor drive (IMD) due to their significant impacts on power quality. In this paper, a new level shifted carrier-based PWM technique is proposed for a 5-level cascaded H-bridge (CHB) multilevel inverter driven by a 36-pulse ac-dc converter based IMD. To meet the power quality demand of IEEE-519 at grid side, a modular transformer is used, and the transformer is coupled to form a 36-pulse ac-dc converter. A 5-level CHB multilevel inverter is utilized on the motor side, which uses the proposed carrier based PWM technique for switching action to ensure superior performance of the IMD. The proposed PWM technique is named as third-harmonic injected inverted sinusoidal carrier PWM (THI2SCPWM), which utilizes 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> harmonic injection principle with inverted sinusoidal signal to form the proposed carrier signal. The 5-level CHB inverter used in the IMD shows less power loss and total harmonic distortion (THD) with the proposed THI2SCPWM technique. Moreover, the IMD with the THI2SCPWM shows low stator voltage THD, stator current THD, and smooth dynamic response. Apart from these, the THI2SCPWM mitigates the torque ripple of the IMD. The motor drive system with the THI2SCPWM technique is modeled and its performance is simulated on MATLAB/Simulink environment. A scaled down experimental setup is utilized to validate the superiority of the proposed PWM technique.

Real time simulation of reduced switch multilevel inverter with PWM switching sequence control

&lt;span lang="EN-US"&gt;Reduction of switch count in symmetrical and asymmetrical reduced switch multilevel inverter designs has been proposed regularly with operation of conventional carrier-based pulse width modulation technique. In this study, a novel structure of symmetrical Hexa shaped model reduced switch seven level output inverter is proposed without any auxiliary switch and H-bridge. Proposed structure offers a smaller number of switch count and voltage sources which results in the cost and complexity reduction of its implementation. To operate the switching sequence of inverter from carrier based APOD, POD and PD methods, suitable logical expression to be realize which gained more prominence. Active utilization of two voltage sources in each mode of operation results in significant reduction of voltage stress across each switch is achieved. A comparative study of proposed MLI with various reduced switch MLIs has been presented. Initially, simulation model implementation has been carried out with MATLAB/Simulink and observed the performance parameters and THD. Simulation results are carried for the comparison of the results obtained in the real time work performed on OPAL-RT 5700 simulator&lt;/span&gt;&lt;span lang="EN-US"&gt;.&lt;/span&gt;

A New Carrier-Based Pulse Width Modulation Technique for an Indirect Matrix Converter

In this work, a new carrier-based pulse width modulation (CPWM) scheme is built for three-to-three phase indirect matrix converter (IMC). In the existing CPWM schemes, the control schemes of the source side converter of the IMC are developed based on either sector based complex calculations or over-modulation operation to obtain the required performance. In the new CPWM scheme, the simplified modulation equations for the source side converter of the IMC are proposed which provide the required performance without resorting to the sector based duty cycle calculations or over-modulation operation. The source and load side converter stages of the IMC are modulated with the standard CPWM principles of the conventional inverter and rectifier topologies in the present work. This work also compares the new CPWM scheme with the SVPWM scheme based on the mathematical calculations which proves that the new CPWM scheme requires less mathematical operations as compared to SVPWM scheme. The simulation and experimental results for both modulation schemes are presented which proves that the new CPWM scheme provides the equivalent input and output performances to those of the SVPWM scheme. The control devices DSP (TMS320F28335) and FPGA (Spartan-6) are used to implement the CPWM and SVPWM schemes.

A four-state CBPWM technique for common-mode voltage reduction in two-level inverter

Common-mode voltage (CMV) leads to a large number of failures in power electronics systems, for example, in two level voltage source inverter (2L VSI)-based circuits. This paper presents a four-state (4S) carrier-based pulse-width modulation (CBPWM) technique which yields the reduced CMV (RCMV) for a 2L VSI. The proposed algorithm is called as 4S RCMV CBPWM. The principle of 4S RCMV CBPWM technique is based on the four-state space vector modulation (4S SVM), which removes the zero vectors in the switching sequence and utilizes the active vectors so that the magnitude of CMV is limited to one-sixth of DC source voltage. In addition, the proposed technique also considers the target of minimizing average CMV values on the whole operation area of the space vector diagram. To implement the proposed algorithm, the CMV function is firstly analyzed so that the requirements for minimized average CMV values are achieved. Control voltages for 2L VSI is deduced from the reference voltages and offset function, thus the required average CMV is achieved. Carrier implementation for proposed algorithm is also analyzed. The theory study is verified by simulation and experiment models the quality of proposed method is evaluated in terms of harmonics distortion factors.

A study on performances of carrier-based pulse-width modulation techniques for three-phase three-level t-type neutral-point-clamped inverter under switch-open-circuit fault on two neutral-point-connected legs

Multilevel voltage source inverters (VSIs) have been used for several decades thanks to their advantages compared with traditional two level VSI. Among various types of multilevel configuration, the T-type neutral-point-clamped VSI (3L TNPC VSI or 333-type VSI) has gained the attention in recent years. Due to the unique structure, the 333-type VSI has critical issues in reliability in operation such as switch-open-circuit (SOC) and switch-short-circuit (SSC), which lead to several unrequired issues, for instance, reduction of system performance, distorted and unbalanced output voltages and currents, or triggering the protection circuits. In some applications, the amplitude reduction and harmonics distortion of output voltages in SOC faults are not acceptable. Therefore, it is necessary to develop a pulse-width modulation (PWM) algorithm for 333-type VSI working under SOC fault which guarantees the desired output fundamental component voltage. The simultaneous SOC fault on two neutral-point-connected legs in the 333-type VSI may cause a large reduction in the output voltage. Under this circumstance, the 333-type VSI becomes an asymmetrical one called 322-type VSI. Certain studies regarding to the operation of 333-type VSI under SOC faults have been carried out. However, these studies require more semiconductor devices in order to create a redundant switching circuit. This leads to higher system cost with reduced inverter effieciency due to the additional loss. In this study, two carrier-based pulse-width modulation (CBPWM) techniques, i.e. 322-sinusoidal PWM (322-SPWM) and 322-medium offset CBPWM (322-MOCBPWM) are proposed for 322-type VSI. The proposed techniques are firstly simulated in MATLAB/Simulink and then implemented on a hardware setup. Performances of the proposed techniques are evaluated in terms of total harmonic distortion (THD) and weighted-THD (WTHD) of output voltages. Simulation results show that considering the worst output voltage under SOC fault, vBC, the proposed 322-SPWM technique could improve the THD by 40% and the WTHD by 94% compared with the uncompensated case with m=0.8. The corresponding results of 322-MOCBPWM technique are 42% and 96%, respectively. Characteristics of THD and WTHD values are also presented for demonstration the effectiveness of the proposed algorithm.

Natural DC‐link voltage balance in a single‐phase NPC inverter with four‐level legs and novel modulation method

This study presents a concept of modulation of a single-phase seven-level neutral point clamped (NPC) converter with natural DC-link voltage balance and symmetrical DC-link capacitors discharge. The method is analysed in a single-phase full-bridge inverter composed of four-level diode-clamped legs (4L-FBCLD) which utilises three capacitors in a DC-link. Under the classic pulse width modulation (PWM) technique, the discharge of DC-link capacitors is unequal in a converter operating with active power. The proposed modulation assures symmetrical discharge of the DC-link capacitors and is achieved in a two-stage design. In the first stage, the carrier-based phase disposition PWM technique with modified carriers is used. In the second stage, the pulses are directed to suitable switches with the use of a state-machine decoder. The switching patterns are different in each level of modulation and are used to trigger natural balancing in the converter on the first and third level of modulation. This study presents the concepts of switching patterns, PWM generation, as well as the simulation and results of the experiment. The latter demonstrates the operation and feasibility of the 4L-FBCLD, symmetrical DC-link capacitor discharge and natural balancing in the converter.

Hybrid Modulation Technique With DC-Bus Voltage Control for Multiphase NPC Converters

The article presents a novel carrier-based pulsewidth modulation technique for multiphase neutral point clamped converters. The technique is aimed to actively control the neutral point (NP) potential while supplying the desired set of line-to-line voltages to the load. Standard techniques are either based on the sole common mode voltage injection or on the sole multistep switching mode; contrarily, the proposed algorithm combines these two approaches to take advantage of their main benefits. The technique performs well for each number of phases, for each modulation index, and for each type of load. It can control in closed-loop the NP voltage to any desirable value with a reduced number of switching transitions. The proposed approach has been experimentally validated and compared with other carrier-based algorithms.

Sawtooth Carrier-Based PWM Methods With Common-Mode Voltage Reduction for Symmetrical Multiphase Two-Level Inverters With Odd Phase Number

The increased phase number of multiphase systems enables us to exploit more degrees of freedom, such as the shape of phase carriers in pulsewidth modulation (PWM). The sawtooth carrier-based PWM (SCPWM) techniques are proposed in this article to reduce common-mode voltage (CMV) in both the peak-to-peak amplitude and the changing frequency, and it can be easily extended to symmetrical multiphase two-level inverters with any odd phase number. Theoretical analysis reveals that the switching between mirror-symmetrical carriers within one phase narrows the range of the sum of switching states in all phases, which leads to the reduction of CMV amplitude. Meanwhile, the overlapping of sawtooth carriers' straight edges among different phases slows down the change of the sum of switching states, which results in the decrease of CMV changing frequency. Moreover, the effects of voltage harmonics injection and switches' dead-time settings on the CMV reduction performance under the proposed SCPWM techniques are investigated. Finally, the experiment results in a five-phase induction machine and multiphase RL loads verify the improved CMV performance and the extensibility of the proposed SCPWM methods.

Study and analysis of the effects of varied PWM techniques and power sharing ratios on the current ripple in open‐ended, three‐level traction motor drives

A dual inverter feeding an open-ended motor load is a feasible solution for high-power traction applications. The topology supplied from isolated DC sources has a power-sharing capability. Different pulse width modulation (PWM) techniques have been proposed for the dual inverter. The performance of these modulation schemes can be compared by analysing the current ripple output of the dual inverter drive. There are various methods in the literature to analyse the ripple content in the output current of the dual inverter. However, the existing work on ripple analysis has been done only for equal power sharing between the isolated DC sources. This study presents an output current ripple analysis for carrier-based PWM techniques for different power-sharing ratios. The variation in the current ripple with varied power-sharing ratios for different PWM techniques is demonstrated. The results to validate the analysis have been obtained using MATLAB/Simulink and real-time simulator. Based on the discussion, an optimal PWM technique under different sharing conditions has been identified.

A Single Carrier-Based Pulsewidth Modulation Technique for Three-to-Three Phase Indirect Matrix Converter

In this article, a new carrier-based pulsewidth modulation (CBPWM) technique is presented for three-to-three phase indirect matrix converter (IMC). The main feature of this technique is the use of single triangular carrier to obtain the switching signals for both converter stages of the IMC. Simplified modulation equations calculated independently from the sector judgements and space vector pulsewidth modulation (SVPWM) technique are proposed for the bidirectional rectifier and inverter stages of the IMC. As a result, the presented CBPWM technique is implemented easily with the reduced complexity as compared to the conventional single carrier-based CBPWM techniques developed based on the SVPWM technique. This new technique features all the benefits associated with the conventional CBPWM techniques of the IMC, i.e., sinusoidal input/output waveforms, voltage transfer ratio of 0.866 and generation of the switching signals independent of the lookup tables. The simulation model of the IMC is developed in the PSIM environment to verify the performance of the proposed CBPWM technique. The laboratory prototype for the IMC is developed based on the proposed scheme using the DSP and FPGA devices. The experimental results are included to support the simulation results.

Pulse Energy Modulation for a Single-Phase Bridge Inverter With Active Power Decoupling Capability

Single-phase voltage-source bridge inverters are widely used in energy storage systems (ESS) and distributed energy resources to transfer dc power to grid-side ac power. The most popular modulation strategy for controlling the ac output of bridge inverters is known as carrier-based pulsewidth modulation (PWM), which varies the duty cycle of the inverter switches at a high switching frequency to achieve a target average line-frequency output voltage or current. Regarding most carrier-based PWM techniques only enable the bridge inverters to operate under continuous conduction mode (CCM) due to the nonlinearity of discontinuous conduction mode (DCM), a pulse energy modulation (PEM) technique is proposed in this article to control single-phase bridge inverters based on energy packets, enabling the inverter to operate under both DCM and CCM and switch between them seamlessly. A single-phase bridge inverter with voltage boosting and power decoupling capabilities is examined as a case study. Small-signal analyses have been conducted for the inverter system with both L-filter and LCL-filter, and the resonant spike of LCL-filter is attenuated in PEM. Simulation and experimental results verify the feasibility of PEM on the investigated single-phase bridge inverter under both DCM and CCM.

Comparative analysis of CB‐PWM techniques in modified multilevel DC link inverter for PV applications

The performance analysis of modified multilevel DC link inverter (MMLDCLI) operating with various carrier-based pulse width modulation (CB-PWM) techniques is studied. In MMLDCLI, seven-level is achieved with six controllable switches only, making it an attractive option as a reduced device count multilevel (MLI, multilevel inverter) topology. MMLDCLI operates with two different levels of voltage source, and the absence of transformer makes this topology suitable for photovoltaic (PV) applications. Two different levels of sources can be achieved with two different combinations of PV panel arrangements. The CB-PWM is reputed modulation approach for MLIs. In this study, various CB-PWM techniques are implemented for MMLDCLI to evaluate performance parameters such as harmonic analysis, device losses and device stress. All the simulations are performed in SIMULINK, and hardware prototype is developed to validate the results.

Space Vector vs. Sinusoidal Carrier-Based Pulse Width Modulation for a Seven-Phase Voltage Source Inverter

The paper presents an extensive comparison between two pulse width modulation (PWM) control schemes, namely carrier-based and space vector based PWM for a seven-phase voltage source inverter. Sinusoidal carrier-based PWM and space vector PWM techniques are employed to control multiphase power converters supplying variable speed multiphase motor drive systems. Implicit relationships that exist between the two PWM techniques are comprehensively explored; this paper, reveal the underlying relationship between the two PWM techniques in terms of several parameters such as modulating signals and space voltage vectors, modulating signals and space voltage vector sectors, switching pattern of space vector and type of carrier. Furthermore, sharing of zero vectors among different chosen space vectors is elaborated that leads to the formulation of different types of modulation. Digital implementation of the two modulation schemes is elaborated. Simulation results are validated using experimental investigation.

Carrier-Based PWM Equivalent to Multilevel Multiphase Space Vector PWM Techniques

The space vector pulsewidth modulation (SVPWM) techniques enhance the performance of multilevel multiphase inverters. With multilevel (three-phase) inverters and with (two-level) multiphase inverters, it is widely accepted that the typical SVPWM strategies have an equivalent carrier-based pulsewidth modulation (CBPWM) counterpart, which produces identical results. However, the conclusions reached in the articles that show these cannot be applied, nor even extended, to SVPWM techniques with more than two levels and three phases. This article shows that the most widely accepted multilevel multiphase SVPWM techniques have a fully equivalent CBPWM counterpart, which consists of a phase disposition pulsewidth modulation with an appropriate zero-sequence injection scheme. Closed-form expressions to calculate the zero sequences are provided. The proposed modulation techniques are simulated and then implemented in a field-programmable gate array, showing that the equivalent CBPWM techniques produce identical results as the original SVPWM ones, but with a significant reduction of hardware requirements. The proposed methodology can be generalized to other multilevel multiphase SVPWM techniques.

Realization of 24-Sector SVPWM With New Switching Pattern for Six-Phase Induction Motor Drive

The six-phase asymmetrical induction motors (SPIMs) are employed for high power medium voltage drive due to its attractive features of reduced stator copper loss, lower torque pulsation, higher torque per ampere, and higher reliability. In this paper, analysis of carrier-comparison-based pulse width modulation (PWM) techniques namely sinusoidal PWM and double zero-sequence injection PWM are carried out from a space vector perspective. Furthermore, new space vector pulsewidth modulation (SVPWM) techniques are developed by modifying the switching sequences of carrier-based PWM techniques. A comprehensive analysis of these PWM techniques is carried out in terms of harmonic flux trajectories, squared harmonic flux, and harmonic distortion factor (HDF). As a result, modified SVPWM technique namely 6ΦSVM3 is found superior to aforesaid PWM techniques, which significantly reduces HDF and provides lower current total harmonic distortion (THD). The experimental results of aforementioned PWM techniques are obtained and verified from six phase asymmetrical induction motor fed by dual two-level 3ΦVSIs. This paper is also accompanied by a video file of experimental test setup recorded while 6ΦSVM2 is running on SPIM.

Simplified implementation of SVPWM techniques for a six‐phase machine with reduced current distortion features

In this study, space vector pulse width modulation (SVPWM) methods for six-phase asymmetrical ac drives are discussed including continuous and discontinuous switching sequences. These switching sequences are adapted from the carrier-based PWM techniques. Some additional sequences are also derived which reduce the intricacy of programming algorithm. Total six pulse width modulation (PWM) techniques are selected for simulation and experimentation. The comparative performances of these modulation techniques are studied in terms of harmonic distortion factor (HDF), torque and current ripples and switching losses. Based on study, a new PWM technique termed as 6SVM3-B2 is found that leads to the lowest HDF and current ripple in prototype model.

CARRIER BASED PWM TECHNIQUE AND ADAPTIVE NEURAL NETWORK BASED ROTOR RESISTANCE ESTIMATOR FOR THE PERFORMANCE ENHANCEMENT OF VECTOR CONTROLLED INDUCTION MOTOR DRIVES

In this paper, the carrier based Pulse Width Modulation (PWM) technique and neural network based rotor resistance estimator are proposed for vector controller Induction motor (IM) drives. The popular sine PWM is used for induction motor drive. The popular sine PWM has poor harmonic profile and (DC) utilization. The space vector modulation (SVM) technique overcomes the disadvantages of sine PWM. But SVM is computationally complex. Hence a simple PWM technique namely “carrier based PWM technique” similar to SVM is identified and proposed for vector controlled IM drive. The experimental set up is built up and the performance of carrier based PWM is validated using FPGA processor. The adaptive neural network based rotor resistance estimator in predictive mode is proposed for the vector controlled induction motor drive. The performance enhancement of the drive with carrier based PWM and rotor resistance estimator is comprehensively presented.