Carbon Nanotube Field Effect Transistor Model Research Articles

Single Ended Read Decoupled High Stable 9T CNTFET SRAM for Low Power Applications

ABSTRACTIn wireless sensor networks, conserving power is vital for prolonging battery life. This research introduces a groundbreaking solution: a 9T carbon nanotube‐field effect transistor (CNTFET) based SRAM cell (9T SRAM) designed to optimize power consumption and stability. Through meticulous analysis, the performance of this 9T SRAM cell is quantified. Power consumption metrics reveal impressive figures: the write, hold, read, and dynamic power are measured at 0.21 nW, 0.32 nW, 15.28 μW, and 8.09 μW, respectively. Furthermore, the Write SNM (WSNM), Hold SNM (HSNM), and Read SNM (RSNM) are found to be 380.11, 390.22, and 390.31 mV, respectively, indicating robust stability. The proposed bit cell has a write and read delay of 95.1 and 39.6 pS, respectively. Incorporating stacked transistors diminishes power consumption, while the decoupled read technique boosts the stability of the proposed bit cell. By comparing these results with existing SRAM cells, the superiority of the proposed 9T SRAM cell in terms of power efficiency becomes evident. Notably, it outperforms earlier models, making it an ideal candidate for integration into wireless sensor networks. These findings are supported by simulations conducted using HSPICE, alongside a 32 nm CNTFET model sourced from Stanford University.

A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes

As AI models grow in complexity to enhance accuracy, supporting hardware encounters challenges such as heightened power consumption and diminished processing speed due to high throughput demands. Compute-in-memory (CIM) technology emerges as a promising solution. Furthermore, carbon nanotube field-effect transistors (CNFETs) show significant potential in bolstering CIM technology. Despite advancements in silicon semiconductor technology, CNFETs pose as formidable competitors, offering advantages in reliability, performance, and power efficiency. This is particularly pertinent given the ongoing challenges posed by the reduction in silicon feature size. We proposed an ultra-low-power architecture leveraging CNFETs for Binary Neural Networks (BNNs), featuring an advanced state-of-the-art 8T SRAM bit cell and CNFET model to optimize performance in intricate AI computations. Through meticulous optimization, we fine-tune the CNFET model by adjusting tube counts and chiral vectors, as well as optimizing transistor ratios for SRAM transistors and nanotube diameters. SPICE simulation in 32 nm CNFET technology facilitates the determination of optimal transistor ratios and chiral vectors across various nanotube diameters under a 0.9 V supply voltage. Comparative analysis with conventional FinFET-based CIM structures underscores the superior performance of our CNFET SRAM-based CIM design, boasting a 99% reduction in power consumption and a 91.2% decrease in delay compared to state-of-the-art designs.

An Improved Dual-Gate Compact Model for Carbon Nanotube Field Effect Transistors with a Back-Gate Effect and Circuit Implementation

Compared to single-gate CNTFET, dual-gate structures have better electrostatic control over nanowire conductive channels. However, currently, there is insufficient research on the back-gate effect in a compact model of dual-gate CNTFET. This paper presents an improved dual-gate carbon nanotube field effect transistor (CNTFET) compact model. The functional relationship between the back-gate voltage (Vbg) and threshold voltage (Vth) is derived. And a voltage reference regulation mechanism is adopted so that the back-gate effect can be accurately reflected in the DC transfer characteristics. The influence of gate voltage and drain voltage on transmission probability is analyzed. Meanwhile, the drain current is optimized by modifying the mobility equation. This compact model is built based on Verilog-A hardware language and supports the Hspice simulation tool. Within the supply voltage of 2 V, the simulation results of the proposed compact model are in good agreement with the measurement results. Finally, based on the compact model, an operational amplifier is designed to verify its correctness and feasibility in analog integrated circuits. When the power supply voltage is 1.8 V, and the load capacitance is 2 pF, the gain is 11.8 dB, and the unit-gain-bandwidth (UGB) is 214 kHz, which proves the efficiency of our compact model.

Energy-Efficient High-Speed dynamic logic-based One-Trit multiplier in CNTFET technology

The appeal of portable electronics, embedded systems, and other smart devices has been steadily growing over time. The multi-valued logic (MVL) was primarily introduced to handle the interconnect issues in binary logic. The use of ternary logic reduces the circuit complexity, power consumption in interconnects, and total chip area. The carbon nanotube field-effect transistor (CNTFET) offers some significant features like low leakage power, equal hole and electron mobility, and modulation in threshold voltage by adjusting the diameter of the carbon nanotube (CNT). In this paper, a clocked dynamic and pass transistor logic-based ternary 1-trit multiplier circuit with only 28 transistors has been proposed. The proposed logic avoids the conventional approach of using logic gates, encoder/decoder, and multiplexers, which reduces the total device count to implement the multiplier. The reduced transistor count offers a reduction in power consumption, delay, power-delay-product (PDP), and energy-delay-product (EDP) in comparison to other state-of-the-art designs. Stanford 32-nm CNTFET model file and Synopsis HSPICE simulator have been used to carry out the simulations at a supply of 0.9 V. The proposed circuit shows a 34.16 %, 66.44 %, and 82.80 % reduction in power, PDP, and EDP as compared to the lowest power, delay, and PDP of the designs under consideration. The performance of the multiplier is evaluated under different temperatures, supply voltages, loads, and oxide thickness.

Impact of Parametric Variation on the Characteristics and Performance of CNTFET Inverter

In this paper, a simple carbon nanotube field effect transistor (CNTFET)-based inverter has been simulated and the impacts of changing various design and process parameters on its characteristics and performance have been analysed using HSPICE. The 32 nm CNTFET model of Stanford University has been used here for the simulation of the inverter. The simulation results and the voltage transfer characteristics (VTC) curve of the inverter have been extracted for (i) different channel lengths, (ii) top gate di-electric material thickness (tox), (iii) pitch value (iv) the number of tubes in CNTFET channel region and (v) chirality of the CNT. It has been observed that the VTC curve changes significantly with different values of these parameters. Some important output parameters like maximum dc current, power, rise time, fall time, average propagation delay, etc. have been measured in each case. Changes in maximum power consumption value due to the change in different parameter values are observed through plotted graphs. Output dc current vs. input voltage graphs have been plotted for different chirality of the tubes, the number of the tubes, and pitch values between n-type CNTFET and p-type CNTFET of the inverter.

Novel Second-Order Fully Differential All-Pass Filter Using CNTFETs.

In this paper, a new carbon nanotube field effect transistor (CNTFET)-based second-order fully differential all-pass filter circuit is presented. The realized filter uses CNTFET-based transconductors and grounded capacitors. An active-only second-order fully differential all-pass filter circuit topology is also presented by replacing the grounded capacitance with a CNTFET-based varactor to achieve filter tunability. By controlling the varactor capacitance, active-only second-order fully differential all-pass filter tunability in the range of 15 GHz to 27.5 GHz is achieved. The proposed active-only circuit works on -oltage, low-power dissipation and high tunable pole frequency. The realized circuit operations are verified through the HPSPICE simulation tool. Deng's CNTFET model is utilized to verify the filter performances at the 16 nm technology node. It is seen that the proposed filter simulation justifies the theoretical predictions and works efficiently in the deep-submicron technology.

Power efficient designs of CNTFET-based ternary SRAM

This paper presents three new power-efficient designs of ternary SRAM using carbon-nanotube-field-effect-transistors (CNTFETs). Two of the proposed ternary SRAM designs are cycle-operator based and the third design is buffer-based. The cycle operators and buffer used in the design of the proposed ternary SRAM consume low power as they use two power supplies for operation. Ternary logic implementation using CNTFETs is largely being used lately due to the advantages it provides in terms of reduced interconnect complexity and chip area. The proposed ternary SRAM designs are compared with the existing designs using HSPICE simulations that use a standard Stanford CNTFET model. All the three proposed designs show considerable improvement in power consumption for read and write operations than their existing counterparts in literature. The read, and write delays and noise margins of the proposed designs are also analysed and are found to be comparable to the existing designs.

Design of CNTFET-based Ternary Ring and Up–Down Counter Cells

In recent times, the multi-valued logic (MVL) design has been widely explored in the designing of digital computing circuits as the goals of enhanced processing capability with reduced interconnect complexity and small chip area are achieved. Hence, this work describes the design methodology of ternary logic-based asynchronous and synchronous up-counter, down-counter, and ring-counter designs using D-flip-flops in carbon nanotube technology. Carbon nanotube-field-effect transistors (CNTFETs)’ unique feature of altering the device threshold voltage by making variations in CNT diameter is exploited for the realization of multiple voltages in ternary logic design. Here the principle of the master-slave scheme is adopted for the designing of Dual shift-single shift and Single shift-dual shift-D-flip-flop circuits using the cyclic property of shifting operators. These flip-flop designs are further extended to construct multiple-digit counter structures which are suitable for realizing the logic functionality of up-counter, down-counter, and ring-counter designs. To exploit ternary logic increased computation capability benefit, a mode control up/down counter circuit is designed in which a single module is generating up and down-counting sequence based on applied mode input. To investigate the performance of the proposed designs, the simulations are performed using the Synopsys HSPICE simulator considering the 32 nm Stanford CNTFET model. According to the simulation results, a maximum energy consumption reduction up to 55% is obtained compared to the counterpart. Hence, the increased computational capability of three-valued logic is exploited in the presented work to achieve energy enhancements in designing ternary sequential circuits.

High-Stability and High-Speed 11T CNTFET SRAM Cell for MIMO Applications

Many researchers are actively working on developing a fast-performing static random-access memory (SRAM) cell with low-power consumption and high stability. This study also introduces one such new and all-round excellent SRAM cell. In this paper, an SRAM cell with eleven transistors (11T) developed using carbon nanotube field effect transistor (CNTFET) is introduced. This new 11T CNTFET SRAM cell is another variant of the Schmitt-trigger (ST)-based SRAM cell. This new SRAM cell structure is achieved by incorporating a single-ended write mode, a feed-back cutting technique and a single-ended read approach into a Schmitt-trigger (ST)-based SRAM cell. The WSNM of the proposed 11T CNTFET SRAM cell is increased by using single-ended writing scheme and feed-back cutting method in the cell. The single ended read approach of 11T CNTFET SRAM cell increases the RSNM as the storage nodes are not disturbed. The write power, hold power, read power, WSNM, HSNM, RSNM, write delay and read delay of this 11T CNTFET SRAM cell are 2.1538e-10 W, 1.7077e-09 W, 1.4524e-08 W, 423.61 mV, 402.20 mV, 425.56 mV, 1.2932e-10s and 5.5225e-12s, respectively. The parameters of the proposed cell are compared with 6T SRAM [M. Elangovan and K. Gunavathi, Stability analysis of 6T CNTFET SRAM cell for single and multiple CNTs, 2018 4th Int. Conf. Devices, Circuits Syst., Coimbatore, India, 16–17 March 2018, vol. 2, pp. 63–67], 8T SRAM [M. Elangovan, A novel Darlington based 8T CNTFET SRAM cell for low, J. Circuits Syst. Comput. 30 (2021) 2150213], 12T SRAM [S. Pal, S. Bose, W. H. Ki and A. Islam, Half-select-free low-power dynamic loop-cutting write assist SRAM cell for space applications, IEEE Trans. Electron Dev. 67 (2020) 80–89, doi:10.1109/TED.2019.2952397], 12T SRAM [N. Yadav, A. P. Shah and S. K. Vishvakarma, Stable, reliable, and bit-interleaving 12T SRAM for space applications: A device circuit co-design, IEEE Trans. Semicond. Manuf. 30 (2017) 276–284, doi:10.1109/TSM.2017.2718029], 12T SRA-M [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger-based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] and 12T SRAM [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] cells to understand the performance of the proposed SRAM cell. From the comparative study, it is observed that the proposed cell is more stable than the other cells considered for the comparison and consumes less power in all write, read and hold modes. Also, the read time of the introduced cell is much less than the others. This study also recorded the information on how the performance of an SRAM cell varies as the CNTFET parameters change. The simulation is done with the HSPICE simulation tool using the Stanford University 32[Formula: see text]nm CNTFET model.

CNTFET-based Data Independent Power Efficient and Robust 8T SRAM Cell

A new carbon nano-tube field-effect transistors (CNTFETs) based Power Efficient and Robust 8T (PER-8T) SRAM cell is proposed to reduce sub-threshold leakage currents, data dependency by improving RBL swing due to which RSNM is improved. Leakage power is reduced by using only single pull-up transistor with High V t in storage latch. Half-select issue is eliminated since proposed work uses de-coupled read port. This CNTFET based proposed PER-8T cell is analysed for performance parameters like power, delay and stability and compared to 8T SRAM cells at 45 nm technology. All simulations are performed at supply voltage of 0.9 V considering Stanford Virtual Source CNTFET(VS-CNTFET) model. It shows that RSNM and WSNM are improved by 12.07%, 14.85%, 56% and 46.46%, 20.39%, 66.05% compared to single ended 8T SRAM cells available in recent literature. Effects of VS-CNTFET parameters such as dielectric material, temperature, oxide thickness and carbon nano tube diameter values on hold power is analysed and best values are considered. The cadence tool is used for measuring all design metrics at room temperature of 25 °C.

Novel design of power-efficient quaternary logic gates using CNTFET

ABSTRACT This paper presents novel power-efficient designs of quaternary logic gates like Quaternary Minimum (QMIN) and Quaternary Maximum (QMAX), Standard Quaternary Inverter (SQI), Standard Quaternary NAND (SQNAND), Standard Quaternary NOR (SQNOR) and Standard Quaternary XOR (SQXOR) using Carbon Nanotube Field Effect Transistor (CNTFET). The designs are based on Pass Transistor Logic (PTL) and use only three types of Carbon Nanotube (CNT) diameters 0.626 nm, 1.018 nm, and 2.27 nm, which lead to lower fabrication costs and enhanced manufacturability when compared to the state-of-the-art designs. The designs are simulated in HSPICE with a 32 nm CNTFET model provided by Stanford University, and the average power and maximum propagation delay obtained from the simulation results are compared with other existing designs. It shows that the proposed designs require 75% to 90% less power and they achieve 73% to 91% less Power Delay Product (PDP) than the latest designs.

A novel CNTFET based Schmitt-Trigger read decoupled 12T SRAM cell with high speed, low power, and high [formula omitted]/[formula omitted] ratio

Many researchers are working to develop a static random access memory (SRAM) cell that uses low power, has good stability, better Ion/Ioff ratio and speed. This paper presents a single sided Schmitt-trigger driven read decoupled 12 transistors (STRD 12T) carbon nanotube field-effect transistor (CNTFET) SRAM cell with controlled power gating approach. The Schmitt-trigger (ST) inverter along with power gating and read decouple approach has low power, good read and write delay, better stability and Ion/Ioff ratio. The stacking effect reduces the leakage power of the proposed cell. The proposed STRD 12T SRAM illustrates the maximum reduction in static power consumption, write delay, read delay, and maximum improvement in Ion/Ioff ratio is 1544.34, 112.37, 1.40, and 8107.88 times respectively, than the considered SRAM cells. The simulation is performed with Cadence Virtuoso utilizing the 32 nm CNTFET model from Stanford University.

Energy efficient design of unbalanced ternary logic gates and arithmetic circuits using CNTFET

The emergence of multi-valued logic (MVL) is a substitute to binary logic approaches for realizing high-information density logic systems and high-operating speed systems. In this paper, a design for standard ternary inverter (STI), ternary NAND (TNAND), ternary NOR (TNOR) using carbon nanotube field effect transistors (CNTFETs) is proposed in which a p-type dynamic diode is used with the goal of lowering the energy consumption expressed as power delay product (PDP) and thereby reducing battery usage. Additionally, the basic arithmetic operations are then performed using proposed ternary logic circuits, which can be extended to realize more complex operations. The proposed designs are simulated in HSPICE using a 32 nm Stanford CNTFET model. With respect to variation in process parameters, the reliability of the proposed STI circuit is examined. Simulation results verify that the proposed designs show improvement in terms of power consumption and power delay product (PDP) compared to the other CNTFET based ternary logic circuits. Moreover, less variations are observed in power and PDP of the proposed logic gates with variation in process parameters, capacitance, temperature, frequency and supply voltage. The proposed circuit designs of STI, TNAND, TNOR, ternary half adder (THA), ternary multiplier (TMUL) show 78 %, 98 %, 99 %, 99 %, 99 % improvement in PDP respectively, as compared to the conventional CNTFET based circuit designs and 99 % PDP improvement in all proposed circuits compared to CNTFET based logic circuits with resistive load.

Highly-Efficient CNTFET-Based Unbalanced Ternary Logic Gates

A large number of interconnections required to implement a binary logic-based circuit leads to an increase in power/energy consumption and area overhead. Utilizing multiple-valued logic (MVL), especially ternary logic, can improve power/energy and total area by reducing the number of interconnections. A ternary logic-based circuit is easily implemented by using carbon nanotube field-effect transistors (CNTFETs) because they have the capability of manifesting different threshold voltages. This paper uses CNTFET devices for the design and implementation of highly-efficient ternary logic gates such as the standard ternary inverter (STI), ternary buffer (TBUF), ternary OR (TOR), and ternary AND (TAND). The proposed STI design offers improvement between 12% and 91.17% in energy consumption and increases noise margin by at least 1.02×, while the proposed TBUF design reduces energy consumption by 14.73%–96.82%. Furthermore, the proposed TOR design reduces power dissipation and energy consumption by at least 72.62% and 84.80%, while the proposed TAND design improves them by at least 8.55% and 11.38%, respectively. The simulations have been performed by using HSPICE software with the Stanford 32 nm CNTFET model at 0.9 V supply voltage.

A High-Speed Low-Energy One-Trit Ternary Multiplier Circuit Design in CNTFET Technology

Contemporary system-on-chip-based applications are battery-powered. To increase the operation time, they need various low-power/energy circuits. Carbon nanotube field-effect transistor (CNTFET) is a potential alternative to complementary metal-oxide-semiconductor for power/energy-efficient circuits implementation due to offering high performance. Another way to reduce power/energy consumption in a circuit is to use multiple-valued logic, especially ternary logic, which has three logical states. This paper presents a novel 1-trit ternary multiplier circuit with 23 transistors based on only unary operators of the ternary logic system and the dual-supply voltages technique. The proposed design does not use the ternary decoder/encoder, logic gates, cascading transmission gates, and ternary multiplexer to reduce the transistors count, delay, power, and energy. The Stanford CNTFET model in the 32 nm technology node is used to simulate the proposed design. The delay, power, and delay-power-product (PDP) of the proposed design at 0.9 V are 0.026 ns, 0.139 μW, and 3.614 aJ, respectively. It offers improvements between 50% and 61.19% in delay and between 52.72% and 59.75% in PDP compared to previously published multiplier circuits, which are based on the dual-supply voltages and use 23 transistors. These improvements make the proposed design a good candidate for the design of the next generation of multiplier circuits in arithmetic blocks.

CNTFET Based Fully Differential First Order All Pass Filter

A novel, carbon nanotube field effect transistor (CNTFET) based fully differential first order all pass filter (FDFAPF) circuit configuration is presented. The FDFAPF uses CNTFET based negative transconductors (NTs) and positive transconductors (PTs) in its realization. The proposed circuit topology employs two PTs, two NTs, two resistors and one capacitor. All the passive components of the realized topology are grounded. Active only fully differential first order all pass filter (AO-FDFAPF) topology is also derived from the proposed FDFAPF. The electronic tunability of the AO-FDFAPF is obtained by controlling the employed CNTFET based varactor. A tunabilty of pole frequency in the range of 10.5 to 26 GHz is obtained. Both the circuits are potential candidates for high frequency fully differential analog signal processing applications. As compared to prior state-of-the-art works, both the realized topologies have achieved highest pole frequency and lowest power dissipation. Moreover, they utilize compact circuit structures and suitable for low voltage applications. Moreover, both topologies work equally well in the deep submicron. The proposed filters are analyzed and verified through HPSPICE simulations by utilizing Stanford CNTFET model at 16 nm technology node. It is observed that the proposed circuit simulation outcomes verify the theory.

Design and analysis of ternary delay flip-flop implemented with carbon nanotube field effect transistor

Flip-flops serve as fundamental memory storage elements in digital circuits, and their efficiency significantly affects overall circuit performance. The aim of this study is to create a D flip-flop based on ternary logic and evaluate its performance in comparison to flip-flops that have already been designed. The proposed D flip-flop design leverages Carbon Nanotube Field Effect Transistors (CNTFETs). CNTFETs offer unique properties that can enhance the speed and power efficiency of flip-flop design. To evaluate the performance of the proposed design, it was simulated using the HSPICE simulator with a 32 nm Stanford CNTFET model. The simulation parameters include a power supply voltage of 0.9 volts and an operating frequency of 1 GHz. These specific settings allow researchers to analyze the behavior and performance of flip-flops under realistic operating conditions. By comparing the simulation results of the proposed D flipflop with the performance of previously designed flip-flops, the improvements are assessed in terms of the speed and power consumption. The simulation results provide valuable insights into the efficiency, reliability, and responsiveness of the proposed design. The findings of this research contribute to the advancement of digital circuit design by introducing a novel D flip-flop based on ternary logic and CNTFET technology. The goal is to enhance the overall performance efficiency of digital circuits, particularly in applications where D flip-flops are used as building blocks such as shift registers.

Performance Optimization of Carbon Nano-Tube Field Effect Transistors by Tuning Parameters

As transistors are scaled down to keep up with Moore's law, the semiconductor industry is facing several challenges due to the limitation of traditional Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology. To overcome this issue of scalability, various other technologies are being researched. Among them are Carbon Nano-Tube Field Effect Transistors (CNTFET), Ribbon Field Effect Transistors (RibbonFET), Graphene Nanoribbon Field Effect Transistor (GNRFET), and Fin shaped Field Effect Transistor (FinFET), which can substitute MOSFETs. Due to carbon nanotubes' excellent conductivity supremacy, CNTFETs are a promising new solution. However, implementing a CNTFET and making circuits from it is still challenging as CNTFETs can exhibit properties of both semiconductor and metal depending on various parameters. This paper will illustrate the characteristics of the CNTFET, compare the power consumption and propagation delay of basic logic gates made using the CNTFET and MOSFET technology. The parameter tuning is done by measuring the power and delay for all parameter values. The Simulation of CNTFET is done on the Stanford CNTFET model using H-Spice.

Design of high stability, low power and high speed 12 T SRAM cell in 32-nm CNTFET technology

Many researchers are trying to create a low power, high stability, and high-speed static random access memory (SRAM) cell. This paper introduces an SRAM cell consisting of 12 transistors (12 T) developed by carbon nanotube field-effect transistor (CNTFET) to support such an endeavor and be a milestone in creating a better SRAM cell. The proposed 12 T CNTFET SRAM cell is a modified Schmitt-trigger (ST)-based SRAM cell design. The ST-based SRAM cell feedback-cutting and single-ended read decupled techniques are introduced to improve the SRAM cell’s static noise margin (SNM) and access time. The presence of stacked N-CNTFETs reduces the proposed cell’s power consumption. In addition to conventional 6 T [9] and 8 T [10] SRAM cells, it has been compared with some of the existing SRAM cells such as 12 T SRAM [11], 12 T SRAM [12], 12 T SRAM [13] and 12 T SRAM [14], for calculating the relative performance of the proposed 12 T CNTFET SRAM cell design in terms of fundamental design metrics. The simulation results at 0.9 V show that compared to the afromentioned bit cells, the proposed design accomplishes low power consumption while writing, reading, and holding modes of operation. It has a high SNM during all the operations. The proposed cell has the least read access time. The power, SNM, and access time performance of the bit cells are evaluated for the variation of CNTFET parameters and reported in this article. The proposed cell is also implemented using MOSFET, and the performance of MOSFET and CNTFET is compared. The simulation is done with the HSPICE simulation tool using the Stanford University 32 nm CNTFET model.

Design of novel 3T ternary DRAM with single word-line using CNTFET

Ternary logic system is the most promising and pursued alternative to the prevailing binary logic systems due to the energy efficiency of circuits following reduced circuit complexity and chip area. In this paper, we have proposed a ternary 3-Transistor Dynamic Random-Access Memory (3 T-DRAM) cell using a single word-line for both read and write operations. For simulation of the circuit, we have used Carbon-Nano-Tube Field Effect Transistor (CNTFET). Here, we have analyzed the operation of the circuit considering different process variations and showed the results for write delay, read sensing time, and consumed current. Along with the basic DRAM design, we have proposed a ternary sense circuitry for the proper read operation of the proposed DRAM. The simulation and analysis are executed using the H-SPICE tool with Stanford University CNTFET model.