Capacitorless Dynamic Memory Research Articles

A critique of length and bias dependent constraints for 1T-DRAM operation through RFET

Capacitorless dynamic memory (one transistor dynamic random access memory (1T-DRAM)) operation in a reconfigurable field effect transistor (RFET) is critically governed by different lengths associated with the architecture. These lengths consisting of ungated region (L UG), control gate (L CG), polarity gate (L PG), storage region length (L S), and total length (L T) can be sensitive to the fabrication process, and hence, critical for 1T-DRAM. This work presents an insightful critique of the above mentioned lengths for realising optimal 1T-DRAM performance. It is shown that RFET with highest values of L S/L T and L CG/L T shows good short channel immunity but does not necessarily ensure enhanced 1T-DRAM metrics. Results indicate that for a fixed L T, retention time can vary over a wide range (550 ms to 8.7 s) depending on the values of L S/L T and L CG/L T, and hence, appropriate optimization is imperative. The work contributes towards better understanding and optimizing L CG/L T to ensure improved 1T-DRAM metrics in terms of enhanced retention (>64 ms), acceptable sense margin (>6 µA µm−1), current ratio (>104) with low values of read (2 ns) and write (1 ns) time to further extend multi-functional facets of nanoscale RFETs for memory applications. In addition, the effect of traps, process sensitivity, reduced number of voltage levels, and disturbance caused by shared word line (WL)/bit line (BL) are also analysed in this work. Results indicate that state ‘0’ of the cell sharing BL with the selected cell is strongly affected by BL disturbance. WL disturbance primarily impacts state ‘1’ of the cell sharing WL with selected cell (only for write 1 and read operations).

Enhancing multi-functionality of reconfigurable transistors by implementing high retention capacitorless dynamic memory

A key indicator of multi-functional attributes of a transistor is technological competiveness vis-à-vis existing architectures. Apart from the well-known logic circuit implementation through reconfigurable field effect transistors (RFETs), this work showcases feasible memory operation by realising capacitorless (1T) dynamic random access memory (DRAM). The memory operation in RFET is achieved through back control gate which creates an electrostatic potential well to store holes. Due to the inherent features of RFET architecture a wider and deeper potential well results in a significantly high retention time (RT) of 2.3 s at 85 °C for a total length of 90 nm. Apart from high retention, RFET based 1T-DRAM exhibits a low write time of ∼2 ns, sense margin (SM) of ∼76 µA µm−1 and a high current ratio (CR) of ∼105. Benchmarking the performance metrics against previously published results indicates competitiveness for RT in terms of total length, storage volume and high temperature operation. Critical insights aiding competitive multi-functional behaviour through 1T-DRAM highlights the possible implementation of logic and memory blocks with RFETs.

Simulation of capacitorless dynamic random access memory based on junctionless FinFETs using grain boundary of polycrystalline silicon

In this paper, we report a junctionless FinFET-based capacitor less dynamic memory by using three-dimensional technology computer-aided design simulations. To realize the 1T-DRAM, the proposed device has been designed as a structure in which a poly-si layer is deposited on the fins of a typical junctionless FinFET. Poly-si has one or more grain boundaries (GB). A GB contains multiple traps, and these traps generally degrade device performance. Also, when poly-si is grown and utilized in semiconductor devices, non-uniform GB is formed across the entire wafer. Therefore, devices manufactured using poly-si have different GBs for each device and the performance of devices fabricated on the same wafer is different. Therefore, it is essential to design a device that can operate normally regardless of GB. The 1T-DRAM proposed in this study was simulated with the existence of GB and the direction of GB differently. Finally, a device that operates normal memory regardless of GB was designed. According to the simulation results, the retention time of the proposed 1T-DRAM has a margin of more than 10 uA/um and a retention time of more than 64 ms, regardless of the presence or absence of GBs.

Improved Retention Time in Twin Gate 1T DRAM With Tunneling Based Read Mechanism

We report a twin gate tunnel field effect transistor-based capacitorless dynamic memory with improved retention characteristics through well-calibrated simulations. The first front gate of the twin gate architecture regulates the read mechanism based on band-to-band tunneling whereas the second front gate creates and maintains a dedicated volume for the charge storage near the drain region. The profound well along with the optimized bias values aid to attain a retention time ( RT ) of $\sim 1.5$ s at 85 °C. Systematic analysis shows that the storage region can be scaled down to 50 nm with further improvement in RT by using an underlap region between drain and second gate. Optimally designed twin gate device exhibits an improved RT at higher temperature (125 °C).

Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering

In this work, we report on the impact of position, bias, and workfunction of back gate on retention time of Tunnel Field Effect Transistor (TFET) based dynamic memory in ultra thin buried oxide and Double Gate (DG) transistors. The front gate of the TFET is aligned at a partial portion of the semiconductor film and controls the read mechanism based on band-to-band tunneling. The back gate is engineered to improve the performance of the dynamic cell by positioning it at the region uncovered by the front gate where it forms a deep potential well. The physical well formed by the back gate misalignment is made more profound by using a p+ poly workfunction as it accumulates more holes in the storage region and forms a deep potential well that sustains holes for longer duration, thereby increasing the retention time. The retention time is also governed by the generation and recombination phenomenon which can be controlled through the applied bias at the back gate. The retention time attained is ∼2 s at a temperature of 85 °C through optimal back gate engineering in DG transistors. The work shows innovative viewpoints of transforming gate misalignment, traditionally considered detrimental into a unique opportunity, coupled with appropriate selection of back gate workfunction and bias to significantly improve the retention time of capacitorless dynamic memory.

A Novel FinFET With High-Speed and Prolonged Retention for Dynamic Memory

A trigate FinFET with a charge trap gate dielectric is demonstrated for high-speed and long retention memory applications. For a capacitor-less dynamic memory cell, a nitride layer is utilized as a charge storage node and it is directly formed on a silicon channel. In addition, novel gate-stacks allow high-speed and write processes under low voltage WITH remarkably endurable operation of up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cycles. By virtue of the charge trap operation, stored data is maintained for >10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s at 125°C.