Capacitive Neutralization Technique Research Articles

Ka-Band Three-Stack CMOS Power Amplifier with Split Layout of External Gate Capacitor for 5G Applications

In this study, we designed a Ka-band two-stage differential power amplifier (PA) using a 65 nm RFCMOS process. To enhance the output power of the PA, a three-stack structure was utilized in the power stage, while the driver stage of the PA was designed with a common-source structure to minimize power consumption in the driver stage. The layout of an external gate capacitor for the stacked power stage was split to maximize the performance of the power transistor. With the proposed split layout of the external capacitor, gain, output power, and power-added efficiency (PAE) were improved. Additionally, a capacitive neutralization technique was applied to the power and driver stages to ensure the stability and enhance the gain of the PA. The measured P1dB and the saturation power were 22.0 dBm and 23.3 dBm, respectively, while the peak PAE was 27.8% at 28.5 GHz.

An AM-PM Compensation of Cross-Coupled Capacitance Neutralization Technique in a Differential Power Amplifier

An AM-PM Compensation of Cross-Coupled Capacitance Neutralization Technique in a Differential Power Amplifier

A K-band broadband low noise amplifier with 18.8dB gain and -13dBm IP<sub>1dB</sub> in 0.13-µm CMOS

A K-band CMOS broadband low noise amplifier (LNA) based on the magnetically coupled resonator (MCR) matching network technique is presented and implemented in 0.13-µm CMOS technology. Such LNA consists of two common-source (CS) pseudo-differential stages, which use the capacitive neutralization technique to enhance the inversion isolation and Gain. The MCR-based input matching network achieves good balance and loss performance by inventing a compensated capacitor and series resistor loaded at the center point of the transformer’s second coil, which improves the linearity and Noise Figure (NF) of the LNA. The measurement NF is 3.7-5.6dB within the frequency range of 20.9-26.2GHz (BW3dB), and the peak gain is 18.8dB. The measured IP1dB is -13dBm at 24GHz with a power consumption of 18mW under 1.2V supply.

A novel stair‐finger grid type transistor for high‐performance millimeter‐wave power amplifier

A novel stair-finger grid type (SFGT) transistor layout is proposed in this letter to improve the f T ${f}_{{\rm{T}}}$ and f max ${f}_{\max }$ of large-sized transistors for the millimeter-wave power amplifier (PA). It combines the promoted stair-finger transistor cells in a grid pattern to minimize parasitic capacitances and metal losses, which has been verified to provide higher gain over broadband by measurements. Two three-stage dual-differential PAs with different transistor layouts are compared in this letter. The PA employs a capacitive neutralization technique and distributed active transformer-based combiner and divider. Fabricated in the Huali Microelectronics Corporation (HLMC) 40-nm Complementary Metal Oxide (CMOS) (Co process, the PA with SFGT transistor [PA2] achieves higher gain and output power than the PA with the currently best-known transistor [PA1]). PA2 achieves 15.22 dBm saturated output power ( P sat ${P}_{\mathrm{sat}}$ ), 14.25 dBm output power at 1 dB compression point ( P 1 dB ${P}_{1\unicode{x0200A}\mathrm{dB}}$ ), and 18.09 dB power gain when the basic supply is 1.1 V at 83 GHz.

A 90 GHz Broadband Balanced 8-Way Power Amplifier for High Precision FMCW Radar Sensors in 65-nm CMOS.

We present a W-band 8-way wideband power amplifier (PA) for a high precision frequency modulated continuous wave (FMCW) radar in 65-nm CMOS technology. To achieve a broadband operation with an improved output power for a high range resolution and high distance coverage of FMCW radar sensors, a balanced architecture is employed with the Lange coupler which naturally combines the output powers from two 4-way push-pull PAs. By utilizing a transformer-based push-pull structure with a cross-coupled capacitive neutralization technique, the gate-drain capacitance of the 4-way PA is compensated for the stabilization with an improved power gain. Interstage matching was performed with transformers for a reduced loss from the matching network and minimal area occupation. The implemented balanced 8-way PA achieved a saturated output power (Psat) of 16.5 dBm, a 1-dB compressed output power (OP1dB) of 13.3 dBm, a power-added efficiency (PAE) of 9.9% at 90 GHz and 3-dB power bandwidth was 20.4 GHz (79.2–99.6 GHz).

Analysis and Design of a 35-GHz Hybrid π-Network High-Gain Phase Shifter With 360° Continuous Phase Shifting

This paper presents the analysis and design of a 35-GHz high-gain phase shifter with 360° continuous phase shifting. To enhance the phase shift range, a hybrid $\pi $ -network realized by combining the electrical tuning through capacitors and magnetic tuning through transformers is developed. The phase shift modules are inserted between the vertically stacking transistors to achieve the embedded phase shifting with the minimum loss. Furthermore, the Gm stages offer additional signal gain to suppress attenuation in the passive phase shifter. The capacitive neutralization technique is utilized to further increase the gain and enhance stability. This prototype, fabricated in a 28-nm CMOS process, demonstrates a 360° continuous phase shift with a maximum gain of 25.6 dB and a minimum noise figure of 4.1 dB. It consumes 26-mW power with a supply voltage of 0.9 V and 1.25 mm $\times0.75$ mm chip area.

A 25.1 dBm 25.9-dB Gain 25.4% PAE X-band Power Amplifier Utilizing Voltage Combining Transformer in 65-nm CMOS

We present an X-band two-stage power amplifier (PA) in 65-nm CMOS process using a transformer (TF)-based voltage combining technique (VTC) which achieves the highest figure of merit (FOM) among recently reported CMOS PAs. The PA architecture is constructed with two-stage push-pull amplifiers with a three-way voltage power combiner and splitter which play the main role to achieve outstanding performance. The power combining was applied in the voltage domain to increase the output device size aiming at boosting the output power of the CMOS PA. We constructed a compact two-stage PA with a push-pull structure with conjugate matchings at the input, inter-stage, and output with the capacitive neutralization technique to improve the power gain and drain efficiency. Working under a 1.2-V supply with DC quiescent current of 865-mA, the proposed PA achieved a maximum saturated output power of 25.1 dBm with a 1-dB power bandwidth of 3-GHz from 8.4-GHz to 11.4-GHz, a peak power added efficiency (PAE) of 25.4% at 10.2 GHz, a power gain of 25.9-dB at 9.5-GHz with a 3-dB gain bandwidth of 2-GHz (8.7-10.7 GHz). The total chip size is 0.9 mm2, and the core size excluding pads is only 0.342 mm2.

A CMOS low-noise active mixer with enhanced linearity and isolation by exploiting capacitive neutralization technique

In this paper, a broadband complementary metal–oxide–semiconductor (CMOS) active down-conversion mixer is presented. Specifically, a capacitor cross-coupled (CCC) transconductor serves as the input stage to reduce noise figure of the mixer while providing wideband input matching. Moreover, a capacitive neutralization technique is used to compensate the source-drain parasitic of input stage and boost loop gain of the transconductor, resulting in improved isolation and linearity. The current-reuse technique applied to the developed transconductor by stacked nMOS/pMOS architecture efficiently saves power consumption of the circuit. Implemented in the TSMC 28-nm CMOS process, post-simulations show that the proposed mixer provides a maximal conversion gain of 11.4 dB and an NF of 3.9–4.7 dB across RF input frequency range of 2–9.6 GHz. The average IIP3 of 5 dBm are obtained while the mixer core consumes 6.2 mW from a 1 V supply.

Investigation on a Novel Capacitive Electrode for Geophysical Surveys

Nonpolarizable electrodes are applied widely in the electric field measurement for geophysical surveys. However, there are two major problems: (1) systematic errors caused by poor electrical contact in the high resistive terrains and (2) environmental damage associated with using nonpolarizable electrodes. A new alternative structure of capacitive electrode, which is capable of sensing surface potential through weak capacitive coupling, is presented to solve the above problems. A technique is introduced to neutralize distributed capacitance and input capacitance of the detection circuit. With the capacitance neutralization technique, the transmission coefficient of capacitive electrode remains stable when environmental conditions change. The simulation and field test results indicate that the new capacitive electrode has an operating bandwidth range from 0.1 Hz to 1 kHz. The capacitive electrodes have a good prospect of the applications in geophysical prospecting, especially in resistive terrains.

An inductorless CMOS programmable-gain amplifier with a > 3 GHz bandwidth for 60 GHz wireless transceivers

An inductorless wideband programmable-gain amplifier (PGA) for 60 GHz wireless transceivers is presented. To attain wideband characteristics, a modified Cherry—Hooper amplifier with a negative capacitive neutralization technique is employed as the gain cell while a novel circuit technique for gain adjustment is adopted; this technique can be universally applicable in wideband PGA design and greatly simplifying the design of wideband PGA. By cascading two gain cells and an output buffer stage, the PGA achieves the highest gain of 30 dB with the bandwidth much wider than 3 GHz. The PGA has been integrated into one whole 60 GHz wireless transceiver and implemented in the TSMC 65 nm CMOS process. The measurements on the receiver front-end show that the receiver front-end achieves an 18 dB variable gain range with a > 3 GHz bandwidth, which proves the proposed PGA achieves an 18 dB variable gain range with a bandwidth much wider than 3 GHz. The PGA consumes 10.7 mW of power from a 1.2-V supply voltage with a core area of only 0.025 mm2.

Current reused Colpitts VCO and frequency divider with quadrature outputs

A low power current reused Colpitts VCO and divide-by-two circuit is proposed in 0.18µm CMOS technology. The divider is stacked on top of a common drain gm-boosted differential Colpitts VCO to share DC current. A capacitance neutralization technique is used to compensate the miller effect of the parasitic gate-drain capacitance Cgd in the VCO, and improves the generated negative resistance and phase noise performance. The Colpitts VCO works at 4.293-4.513GHz, and can provide 2.147-2.257GHz quadrature outputs through the stacked divide-by-two circuit. The VCO circuit exclude the output buffer consumes 2.8mA at 1.8V supply voltage. The measured phase noise is -109dBc/Hz at 1MHz offset frequency when the VCO output is 4.513GHz.