Capacitive Cross-coupling Technique Research Articles

Wideband Balun-LNAs using asymmetric CCC technique for WLAN and mobile WiMAX applications

Capacitive Cross-Coupling (CCC) buffers require the output impedances of their drivers to be equal. For drivers with unequal output impedances such as the CG-CS balun-LNA, an asymmetric CCC technique denoted as A-CCC is proposed in this paper. Two Wideband Balun LNAs– LNA1 which uses A-CCC and an auxiliary current reuse amplifier (ACRA), and LNA2 which uses A-CCC, ACRA and shunt peaking are proposed to achieve noise figure (NF) less than 2 ​dB. The proposed LNAs are implemented in 0.18 ​μm CMOS technology and are evaluated through post-layout simulations. It is found that NF, Gain, 3dB band of (1.81–2.5 ​dB, 23.7–26.7 ​dB, 1 – 4 ​GHz) and (1.97–4.14 ​dB, 25–28 ​dB, 1 – 6 ​GHz) are obtained for LNA1 and LNA2 respectively. The average IIP3, IIP2 of LNA1 and LNA2 are found to be (−8.45 dBm, +11.73 dBm) and (−2.59 dBm, +17.42 dBm). The LNA1 and LNA2 consume 6.7 ​mW and 6.53 ​mW power from a 1.2 ​V supply for core areas of 0.25 ​mm2, 0.85 mm2.

A high linearity dual-band mixer for IMT-A and UWB systems

The design and analysis of a reconfigurable dual-band down-conversion mixer for IMT-advanced (3.4–3.6 GHz) and UWB (4.2–4.8 GHz) applications are presented. Based on a folded double-balanced Gilbert cell, which is well known for its low voltage, simplicity and well balanced performance, the mixer adopts a capacitive cross-coupling technique for input matching and performance improvement. Switched capacitors and resistors are added to shift the working bands. Fabricated in a TSMC 0.13 μm process, the test results show flat conversion gains from 9.6 to 10.3 dB on the IMT-A band and from 9.7 to 10.4 dB on the UWB band, with a noise figure of about 15 dB on both bands. The input third-order intercept points (IIP3) are about 7.3 dBm on both of the frequency bands. The whole chip consumes 11 mW under 1.2 V supply and the total area of the layout is 0.76 × 0.65 mm2.

Special issue on selected papers from NORCHIP 2013 conference

This special issue of Analog Integrated Circuits and Signal Processing presents the extended versions of selected papers from the 31th NORCHIP conference which was held in Vilnius, Lithuania, November 11–12, 2013. The 31th NORCHIP conference had 56 registered participants and 45 papers were presented during the 2 days the conference lasted whereof 30 papers were presented in 10 oral lecture sessions in two tracs, 12 papers were presented in two poster sessions, the 3 presentation, in session on Education and Training. The 3 invited presentations (first—Romualdas Navickas, ‘‘Self-formation in high speed integrated circuits’’, second—Petar Popovski, ‘‘Wireless technologies competing for a seat in the 5G bandwagon’’, and third—Ville Eerola, ‘‘Correlator design and implementation for GNSS receivers’’) were given. However, more submissions are originating from the local area of the conference (only one accepted paper was from a non-European country). From the contributed papers nine papers have been selected for this special issue. The selection of the papers for this special issue is based on quality criteria and they reflect the topics in analog circuit design highlighted during the conference, the feedback of the session chairs and the selected papers all contain contributions that will be of interest to the reader. The papers are briefly introduced below. The two first papers present two RF amplifiers. In the first paper ‘‘Triple Cascaded Current-Reuse Low Noise Amplifier’’ Muh-Dey Wei, Sheng-Fuh Chang, Renato Negra present a triple cascaded current-reuse CMOS low noise amplifier (LNA) for 3.5 GHz WiMAX application. Three commonsource amplifiers are stacked and reuse the same current. This triple cascaded topology is able to enhance power gain but needs two coupling networks which costs enormous chip size. In order to have reasonable chip size, two coupling methods are investigated. For obtaining simultaneous input and noise matching, an additional capacitor is employed to adjust quality factor and reduce the gate induced current noise. The proposed chip is implemented in 180 nm CMOS technology. The measurement results show a maximum power gain of 21.7 dB and minimum noise figure of 3.11 dB. The chip size is 1.05 9 0.93 mm including all pads and the power consumption is 5.16 mW with a supply voltage of 1.5 V. In the second paper ‘‘A 1 V Power Amplifier for 81–86 GHz E-band’’ authors Tobias Tired, Henrik Sjoland, Carl Bryant and Markus Tormanen describe the design and layout of a two stage SiGe E-band power amplifier using a stacked transformer for output power combination. In EMsimulations with ADS Momentum, at E-band frequencies, the power combiner consisting of two individual single turn transformers performs significantly better than a single 2:1 transformer with two turns on the secondary side. Imbalances in the stacked transformer structure are reduced with tuning capacitors for maximum gain and output power. At 84 GHz the simulated loss of the stacked transformer is as low as 1.35 dB, superseding the performance of an also presented alternative power combiner. The power combination allows for a low supply voltage of 1 V, which is beneficial since the supply can then be shared between the power amplifier and the transceiver, thereby eliminating the need of a separate voltage regulator. To improve the gain of the two-stage amplifier it employs a capacitive cross-coupling technique not yet seen in mm-wave SiGe Pas. Capacitive cross-coupling is an effective technique for gain enhancement but is also sensitive to process variations as shown by Monte Carlo simulations. To mitigate this two R. Navickas (&) Department of Computer Engineering, Vilnius Gediminas Technical University, Naugarduko str. 41, r. 437, 03227 Vinius, Lithuania e-mail: romualdas.navickas@vgtu.lt

A 1 V power amplifier for 81–86 GHz E-band

The design and layout of a two stage SiGe E-band power amplifier using a stacked transformer for output power combination is presented. In EM-simulations with ADS Momentum, at E-band frequencies, the power combiner consisting of two individual single turn transformers performs significantly better than a single 2:1 transformer with two turns on the secondary side. Imbalances in the stacked transformer structure are reduced with tuning capacitors for maximum gain and output power. At 84 GHz the simulated loss of the stacked transformer is as low as 1.35 dB, superseding the performance of an also presented alternative power combiner. The power combination allows for a low supply voltage of 1 V, which is beneficial since the supply can then be shared between the power amplifier and the transceiver, thereby eliminating the need of a separate voltage regulator. To improve the gain of the two-stage amplifier it employs a capacitive cross-coupling technique not yet seen in mm-wave SiGe PAs. Capacitive cross-coupling is an effective technique for gain enhancement but is also sensitive to process variations as shown by Monte Carlo simulations. To mitigate this two alternative designs are presented with the cross coupling capacitors implemented either with diode coupled transistors or with varactors. The PA is designed in a SiGe process with f T = 200 GHz and achieves a power gain of 12 dB, a saturated output power of 16 dBm and a 14 % peak PAE. Excluding decoupling capacitors it occupies a die area of 0.034 mm2.

A 0.5–2.5 GHz 910 uW complementary LNA employing positive–negative feedback

A 0.5---2.5 GHz ultra low power differential resistive feedback common gate low noise amplifier (RFCGLNA) without the use of inductor is presented. The proposed RFCGLNA adopts the NMOS and PMOS complementary topology to reduce the power consumption by half. Based on common-gate topology, the proposed RFCGLNA employs capacitive cross-coupling (CCC) and resistive feedback techniques. The CCC technique can further reduce the power consumption by half. The resistive feedback technique can constrain the common mode voltages of the proposed RFCGLNA and meanwhile, improve the third-order input intercept point (IIP3). The DC path is supplied by the current source transistor which forms a positive feedback loop to improve the gain at low frequency. Implemented with 65 nm standard complementary metal oxide semiconductor (CMOS) technology, the measured performance achieves 15 dB gain with S11 < ?10 dB in the 0.5---2.5 GHz band. The noise figure (NF) is 3.9---5.0 dB and the IIP3 is 3.1---3.6 dBm. The power consumption is only 910 uW.

Design of a Low Voltage Highly Linear 2.4 GHz Up-Conversion Mixer in 0.18 μm CMOS Technology

This paper presents a low voltage highly linear up-conversion mixer for 2.4 GHz IEEE 802.11b WLAN transmitter applications based on a Chartered 0.18 μm CMOS technology. In the proposed mixer, the double balanced Gilbert cell topology was adopted and the dual resistive current-reuse and current-bleeding techniques in both the driver and switching stages with a capacitive cross-coupling technique were used. The up-conversion mixer can convert a 10 MHz intermediate frequency signal to a 2.4 GHz radio frequency signal, with a local oscillator power of 0 dBm at 2.39 GHz. A comparison with conventional CMOS mixer shows that this up-conversion mixer has advantages of low voltage, low power consumption and high performance. The post-layout simulation results demonstrate that at 2.4 GHz, the circuit provides 7.1 dB of conversion gain and the input-referred third-order intercept point of 11.3 dBm, while drawing only 5 mA for the mixer core under a supply voltage of 1.2 V. The chip area including testing pads is only 0.65 × 0.75 mm.

A 0.6‐V high reverse‐isolation through feedback self‐cancellation for single‐stage noncascode CMOS LNA

AbstractIn many designs, a low supply voltage is selected for efficient use of power. However, this often leads to low reverse‐isolation which is critical to the RF front–end circuits and particularly to the low‐noise amplifier (LNA). In this letter, a fully integrated differential low‐voltage CMOS LNA with high reverse‐isolation is presented. This LNA makes use of the single‐stage noncascode structure and the capacitive cross‐coupling (CCC) technique. The CCC technique has been utilized in many LNA designs. However, in all of the reported works using CCC, the CCC technique was mainly used to improve the noise figure (NF), not the reverse‐isolation. The poor reverse‐isolation problem in single‐stage noncascode structure has never been analyzed in the capacitive cross‐coupling cascaded low noise amplifier (CCCLNA). This work shows a novel analysis on the feedback self‐cancellation mechanism to improve the reverse‐isolation. Other analyses on input matching, gain and NF were also performed to show the feasibility of using CCC technique for the low‐voltage LNA as well as the advantages of the CCCLNA over the conventional common‐source and common‐gate (CG) LNA. The LNA consumes only 0.5 mW from 0.6 V supply voltage. It achieves a gain of 14 dB and a NF of 3.55 dB. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett, 54:374–379, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26542

A 5 GHz 7.2 dB NF low power direct conversion receiver front-end with balun LNA

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consumption at low gain mode. The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm2. It achieves 35 dB conversion gain across 4.9–5.1 GHz, a noise figure of 7.2 dB and an IIP3 of −16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.

A low-voltage low-power CMOS transmitter front-end using current mode approach for 2.4 GHz wireless communications

This paper presents a low-voltage low-power transmitter front-end using current mode approach for 2.4GHz wireless communication applications, which is fabricated in a chartered 0.18μm CMOS technology. The direct up-conversion is implemented with a current mode mixer employing a novel input driver stage, which can significantly improve the linearity and consume a small amount of DC current. The driver amplifier utilizes a transimpedance amplifier as the first stage and employs an inter-stage capacitive cross-coupling technique, which enhances the power conversion gain as well as high linearity. The measured results show that at 2.4GHz, the transmitter front-end provides 15.5dB of power conversion gain, output P−1dB of 3dBm, and the output-referred third-order intercept point (OIP3) of 13.8dBm, while drawing only 6mA from the transmitter front-end under a supply voltage of 1.2V. The chip area including the testing pads is only 0.9mm×1.1mm.

A Wideband Noise Cancelling Low Noise Amplifier for 3GPP LTE Standard

This paper presents the design of a wideband low noise amplifier (LNA) for the 3GPP LTE (3rd Generation Partnership Project Long Term Evolution) standard. The proposed LNA uses a common gate topology with a noise cancellation technique for wideband (0.7 to 2.7GHz) and low noise operation. The capacitive cross coupling technique is adopted for the common gate amplifier. Consequently input matching is achieved with lower transconductance, thereby reducing the power consumption and noise contribution. The LNA is designed in a 0.18µm process and the simulations show lower than -10dB input return loss (S11), and 2.4∼2.6dB noise figure (NF) over the entire operating band (0.7∼2.7GHz) while drawing 9mA from a 1.8V supply.

A Low-Voltage CMOS Current Mode Integrated Transmitter Front-end for 2.4-GHz Wireless Communications

This paper presents a low-voltage low-power current mode transmitter front-end for 2.4 GHz wireless communication applications, which is fabricated in a chartered 0.18-mm CMOS technology. The direct up-conversion is implemented with a current mode mixer employing a novel input driver stage, which can significantly improve the linearity and consume a small amount of DC current. The driver amplifier utilizes a transimpedance amplifier as the first stage and employs an inter-stage capacitive cross-coupling technique which enhances the power conversion gain as well as high linearity. The measured results show that at 2.4GHz, the transmitter front-end provides 15.5dB of power conversion gain, output P-1dB of 3dBm, and the output-referred third-order intercept point (OIP3) of 13.8dBm, while drawing only 6 mA from the transmitter front-end under a supply voltage of 1.2 V. The chip area including testing pads is only 0.9 mm 1.1 mm. Index Terms –CMOS, up-conversion mixer, driver amplifier, transmitter, current mode, high linearity, low-power