Capacitive Transimpedance Amplifier Research Articles

A Low-Power, High-Resolution Analog Front-End Circuit for Carbon-Based SWIR Photodetector

Carbon nanotube field-effect transistors (CNT-FETs) have shown great promise in infrared image detection due to their high mobility, low cost, and compatibility with silicon-based technologies. This paper presents the design and simulation of a column-level analog front-end (AFE) circuit tailored for carbon-based short-wave infrared (SWIR) photodetectors. The AFE integrates a Capacitor Trans-impedance Amplifier (CTIA) for current-to-voltage conversion, coupled with Correlated Double Sampling (CDS) for noise reduction and operational amplifier offset suppression. A 10-bit/125 kHz Successive Approximation analog-to-digital converter (SAR ADC) completes the signal processing chain, achieving rail-to-rail input/output with minimized component count. Fabricated using 0.18 μm CMOS technology, the AFE demonstrates a high signal-to-noise ratio (SNR) of 59.27 dB and an Effective Number of Bits (ENOB) of 9.35, with a detectable current range from 500 pA to 100.5 nA and a total power consumption of 7.5 mW. These results confirm the suitability of the proposed AFE for high-precision, low-power SWIR detection systems, with potential applications in medical imaging, night vision, and autonomous driving systems.

Development and validation of a 64-channel ROIC prototype for SWIR line scan sensor applications

This paper introduces the development and validation of a 64-channel readout integrated circuit (ROIC) prototype, specifically engineered for short-wave infrared (SWIR) line scan sensors. The design of the prototype undergoes various evaluation through comprehensive silicon-level testing, ensuring its robust performance across a variety of operational modes. Key features such as capacitive transimpedance amplifier (CTIA) gain control and sensitivity control are examined, demonstrating the prototype's ability to handle different input currents and capacitance values with precision. Fabricated with 0.18-μm CMOS technology, the ROIC is tailored for integration with Indium Gallium Arsenide (InGaAs) pixels, facilitating high-resolution imaging. The prototype consumes 26.55 mW with A 3.3 V power supply. The fabricated chip show that the total random noise (RN) level is 128 μVrms and column fixed pattern noise (FPN) is 0.16 mVrms

Ultra-low noise front-end design for smart optical sensors with high sensitivity and wide dynamic range.

Ultra-low noise is a critical component in the design of high-precision sensor front-ends. We introduced differential phase-sensitive detection (d-PSD) to mitigate both multiplicative and additive noise in optical sensors, aiming for an enhanced performance and cost-effectiveness. The d-PSD combines a capacitive transimpedance amplifier (C-TIA), a delta-sigma analog-to-digital converter (ΔΣ-ADC), and a software-based lock-in amplifier (s-LIA). The first two components utilize the DDC112 (a dual current input 20-bit ADC) for a minimal analog channel length, thus reducing noise efficiently, while the latter employs a cost-effective 32-bit microcontroller unit (MCU), the HC32F460. This approach was successfully implemented as the front-end for a smart optical sensor. Testing indicated that the sensor achieved an equivalent current noise level of 0.6 nA/√Hz, primarily attributed to the light source driver rather than the sensor's front-end circuit. The sensor exhibited an exceptional performance, with a 3σ measurement precision of 5.4 × 10-4 over a 1-second integration time and a dynamic range of 100 dB, leveraging the proposed method and design. Furthermore, the front-end of the sensor boasts a compact size, low power consumption, and affordability, making it an ideal, versatile solution for ultra-high precision, smart optical sensors.

A CMOS Current Sensing Interface With Sub-pA DC Uncertainty

This paper presents a CMOS current sensing interface with a dedicated analysis on dc uncertainty, especially the relationship among averaging, standard deviation and Allan variance. The dependence of the Allan variance on various noise sources is analyzed. The noise leakage mechanisms due to circuit nonidealities that lead to dc uncertainty are presented. A general design strategy toward a low dc uncertainty is drawn in this work. An auto-zeroing (AZ) capacitive transimpedance amplifier (CTIA) is reported for near-zero signal loss and near-perfect noise cancelation to achieve a low dc uncertainty. A prototype design implemented on 180nm CMOS process is presented and the measurement result shows a 73fA dc uncertainty.

A Highly Integrated Lab-on-a-CMOS Platform for Real-Time Monitoring of E. Coli Growth Kinetics.

Existing miniaturized and cost-effective solutions for bacterial growth monitoring usually require offline incubators with constant temperature to culture the bio-samples prior to measurement. Such a separated sample preparation and detection scheme requires extensive human intervention, risks contamination, and suffers from poor temporal resolution. To achieve integrated sample preparation and real-time bacterial growth monitoring, this article presents a lab-on-a-CMOS platform incorporates an optical sensor array, temperature sensor array, micro-heaters, and readout circuits. Escherichia coli's (E. coli) optimum growth temperature of 37 °C is achieved through a heat regulation system consisting of two micro-heaters and an on-chip temperature sensor array. A photodiode array with an in-pixel capacitive trans-impedance amplifier to reduce inter-pixel cross-coupling is designed to extract the optical information during bacterial growth. To balance the footprint, power consumption, and quantization speed, a 10 b column successive-approximation register (SAR)/single-slope (SS) dual-mode analog-to-digital converter (ADC) is designed to digitize the temperature and optical signals. Fabricated in a standard 0.18 um CMOS process, the proposed platform can regulate the sample temperature to 37 +/- 0.2/0.3 °C within 32 mins. Enabled by an on-chip heat regulation system and photodetectors, the prototype demonstrates a real-time monitoring of bacterial growth kinetics and antibiotic responses. Minute-level temporal resolution is achieved as this proposed platform is free of extensive and time-consuming human intervention. The proposed platform can be viably used in contamination sensitive applications such as antibiotic tests, stem cell cultures, and organ-on-chips.

A Voltage-Assist 16-Channel Electrochemical Biosensor with Linearity Compensation.

Large capacitive loading of electrodes induces massive error current and imperfect settling in the electrochemical signal acquisition process, leading to inaccurate acquisition results. To efficiently mitigate this inaccuracy, this paper presents a current-and-voltage dual-mode acquisition technique in which a voltage front-end (VFE) is employed to acquire the electrode voltage error and compensate the nonlinearity induced by the electrode capacitive loading. Therefore, the gain and bandwidth requirements of the current front end (CFE) can be relaxed to reduce the complexity and power consumption. With a relieved gain requirement, an inverter-based capacitive trans-impedance amplifier (IB-CTIA) is adopted to boost the input transconductance for low-noise design. By reusing the supply current, the IB-CTIA effectively achieves a low input-referred current noise of 3.9 pArms and a dynamic range (DR) of 126 dB with only 18-μW static power. The prototype chip is fabricated in a 180-nm CMOS process. Interleukin-6 immunoassays (IL-6) are implemented to verify the chip's performance. With the proposed nonlinear error compensation, the correlation coefficient of the detection result is improved from 0.951 to 0.980 and the limit of detection (LoD) is reduced from 8.31 pg/mL to 6.90 pg/mL.

Modeling of graphene photodetector based on photogating effect for circuits simulation

Abstract Graphene photodetectors based on the photogating effect offer the advantages of high responsivity. However, physical model of these photodetectors which is suitable for circuit design are still missing at present time. This paper aims to develop a physical model of the detector by introducing a ‘virtual back-gate’ method, which translates incident optical power into the Dirac point voltage of the transfer curve. Additionally, a physical model of the detector is established by combining the ‘virtual back-gate’ and ‘photo-gate’. To investigate the relationship between input optical power and photocurrent, a detector PSPICE model is developed using the gate-controlled current sources realized through the ‘virtual back-gate’ and ‘photo-gate’. A capacitive transimpedance amplifier circuit is employed for simulation verification. The research presented in this paper serves as a valuable reference for the circuit design of two-dimensional material photodetectors based on the photogating effect.

The Design of a Low-Noise, High-Speed Readout-Integrated Circuit for Infrared Focal Plane Arrays

This paper describes the design of a low-noise, high-speed readout-integrated circuit for use in InGaAs infrared focal plane arrays, and analyzes the working principle and noise index of the pixel circuit in detail. The design fully considers the dynamic range, noise, and power consumption of the pixel circuit in which a capacitance transimpedance amplifier structure is adopted as the input stage circuit, and chip fabrication via an XFAB 0.18 µm CMOS process is successfully realized. The ROIC adopts monolithic integration and implements various functions, such as windowing, subsampling, and different integration and readout modes. The ROIC reached an array scale of 32 × 32, a frame rate of 100 Hz, and a readout rate of 20 Mbps with an analog power consumption of less than 52 mW. The measurement results show that the input reference noise can be reduced to 143 e- via the CDS, and the fully customized scheme has certain advantages in the research of high-performance ROICs.

An 8nA-512μA Current-to-Digital Converter With Mixed-Signal Coarse-Fine Subrange Normalization

This brief presents a current to digital convertor (CDC) with low power, wide dynamic range and fast conversion speed. Proposed coarse converter extends the maximum input current range, and achieves fast conversion speed with the input adaptive control scheme. Capacitive transimpedance amplifier (CTIA) based fine converter digitizes the residue current and achieves fine resolution. Proposed mixed-signal coarse-fine subrange normalization technique enables seamless processing of the final converter output. The proposed CDC implemented in 0.18 μm CMOS process converts input current up to 512 μA with 7.8125nA resolution and 400 μs conversion time. Power consumption is 79.4 μW.

Evaluating the GeoSnap 13‐μ$$ \mu $$m cutoff HgCdTe detector for mid‐IR ground‐based astronomy

AbstractNew mid‐infrared HgCdTe (MCT) detector arrays developed in collaboration with Teledyne Imaging Sensors (TIS) have paved the way for improved 10‐m sensors for space‐ and ground‐based observatories. Building on the successful development of longwave HAWAII‐2RGs for space missions such as NEO Surveyor, we characterize the first 13‐m GeoSnap detector manufactured to overcome the challenges of high‐background rates inherent in ground‐based mid‐IR astronomy. This test device merges the longwave HgCdTe photosensitive material with Teledyne's GeoSnap‐18 (18‐m pixel) focal plane module, which is equipped with a capacitive transimpedance amplifier (CTIA) readout circuit paired with an onboard 14‐bit analog‐to‐digital converter (ADC). The final assembly yields a mid‐IR detector with high QE, fast readout (>85 Hz), large well depth (>1.2 million electrons), and linear readout. Longwave GeoSnap arrays would ideally be deployed on existing ground‐based telescopes as well as the next generation of extremely large telescopes. While employing advanced adaptive optics (AO) along with state‐of‐the‐art diffraction suppression techniques, instruments utilizing these detectors could attain background‐ and diffraction‐limited imaging at inner working angles <10 /D, providing improved contrast‐limited performance compared with JWST MIRI while operating at comparable wavelengths. We describe the performance characteristics of the 13‐m GeoSnap array operating between 38 45 K, including quantum efficiency, well depth, linearity, gain, dark current, and frequency‐dependent () noise profile.

A High Dynamic Range Protein Sensing Platform for Low-Volume Magneto Immunoassay Automation

Immunoassays have been employed in diagnosing numerous diseases. Typically, these tests require a large volume of biofluid sample and overnight reaction. In this paper, a high dynamic range microfluidic protein sensing platform is presented. This platform reduces the required sample volume, expedites the reactions, and automatically controls the sample processing procedures. The platform includes a high-performance potentiostat circuit for redox signal acquisition, and an 8-channel polydimethylsiloxane (PDMS) microfluidic device for automatic sample processing. The sensing circuit employs a capacitive transimpedance amplifier (CTIA) architecture, which achieves low current noise (15.8pA), wide (116dB) dynamic range, and good linearity. The linearity of the whole platform is verified with electrochemical measurements using potassium ferricyanide (K3[Fe(CN)6]). The immunoassays are performed with patients’ serum samples and horseradish peroxidase (HRP)/3,3’,5,5’-tetramethylbenzidine (TMB) substrate-based assays. The limit-of-detection (LoD) of the whole system is 7pg/mL.

Ultra-low noise current meter for measuring quickly changing currents from attoampere to nanoampere

Abstract Low-noise current meters are usually designed using high value feedback resistors. However, a high resistance reduces the maximum measurable current at a given output voltage and the maximum bandwidth at a given parasitic capacitance. Capacitive transimpedance amplifiers integrating the current to be measured correspond to a nearly infinite resistance. Here, we present a novel active reset architecture for discharging the integration capacitor that eliminates the leakage currents and charge injection of the necessary switches. This enables a capacitive current meter achieving the noise current of an ideal resistive transimpedance amplifier with an ideal resistance of 650 GΩ, while the dynamic range, bandwidth and zero-point stability are orders of magnitude greater due to the capacitive operating principle. At a 3-dB bandwidth of 50 Hz, the noise current standard deviation is σ i = 2.6 fA {\sigma _{i}}=2.6\hspace{0.1667em}\text{fA} with a dynamic range of six orders of magnitude from femto- to nanoamperes. Digitally adjusting the 3-dB bandwidth to 0.45 mHz for measuring direct currents reduces the noise by three orders of magnitude down to σ i = 8.7 aA {\sigma _{i}}=8.7\hspace{0.1667em}\text{aA} , resulting in a dynamic range of nine orders of magnitude. This is possible due to an excellent zero-point stability within ± 25 aA without temperature or humidity compensation.

An integrate-and-fire neuron with capacitive trans-impedance amplifier for improving linearity in Spiking Neural Networks

In this paper, we propose a novel neuron circuit with capacitive trans-impedance amplifier (CTIA) integrator to enhance the linearity of pre-synaptic current summation. The proposed neuron circuit achieved an improvement compared to the conventional neuron circuit with a current mirror, thereby maintaining the input node of a neuron circuit at virtual ground by the negative feedback of an amplifier. The relative potential difference is integrated into the membrane capacitor of CTIA feedback loop with a negative integration. From the simulation results, we confirmed that the proposed neuron circuit successfully improves output linearity for a wide range of the input current level.

Threshold Uniformity Improvement in 1b Quanta Image Sensor Readout Circuit.

A new readout architecture for single-bit quanta image sensor (QIS) consisting of a capacitive transimpedance amplifier (CTIA) before a 1-bit quantizer to improve the threshold uniformity of the readout cluster is proposed in this paper. The 1-bit quantizer in the previous single-bit QIS had significant threshold non-uniformity likely caused by the fluctuation of the common-mode voltage of the jot output. To guarantee the stability of the common-mode voltage of input signals fed to the 1-bit quantizer, the CTIA is added before the 1-bit quantizer. A pipeline operation mode is also proposed so the CTIA and 1-bit ADC can work at the same time, thereby reducing the CTIA power consumption. A 2048 × 1024 high-speed test chip was implemented with 45 nm/65 nm stacked backside illuminated (BSI) CMOS image sensor (CIS) process and tested. According to the measured D-log-H results, a good threshold uniformity in the range of 0.3 to 0.8 e− for all readout clusters is demonstrated at 500 frame per second (fps) equivalent timing with 68 mW power consumption.

In-Pixel CTIA & Readout Circuitry for an Active CMOS Image Sensor

This work aims to design and simulate an in-pixel Capacitive Transimpedance Amplifier (CTIA) and peripheral circuitry that ensures pixel reading. Each pixel circuit is composed of four transistors using 90nm CMOS technology with a supply voltage of 1.8 V and is part of an array of pixels that make up a CMOS image sensor with peripheral circuitry. Pixel output is sent to a delta difference sampling (DDS) circuit to filter reset voltages. The Gain Margin achieved for the in-pixel CTIA is 44dB and 91dB for the Phase Margin. We also present measured pixel parameters and give a comparison with prior work. The timing and readout circuitry is also described.

The Long Neglected Cycloidal Mass Analyzer.

In 1938, Walker Bleakney and John A. Hipple first described the cycloidal mass analyzer as the only mass analyzer configuration capable of "perfect" ion focusing. Why has their geometry been largely neglected for many years and how might it earn a respectable place in the world of modern chemical analysis? This Perspective explores the properties of the cycloidal mass analyzer and identifies the lack of suitable ion array detectors as a significant reason why cycloidal mass analyzers are not widely used. The recent development of capacitive transimpedance amplifier array detectors can enable several techniques using cycloidal mass analyzers including spatially coded apertures and single particle mass analysis with a "virtual-slit", helping the cycloidal mass analyzer earn a respectable place in chemical analysis.

Research on a pulse-based high-line-rate TDI CMOS image sensor

In this paper, a 256-stage pulse-based time delay integration (TDI) CMOS image sensor is presented. In this sensor, a capacitive trans-impedance amplifier (CTIA) based pipeline charge transfer (PCT) pixel structure is proposed, which achieves low noise signal accumulation. A pulse generator circuit is used after the PCT-pixel to detect and generate pulse, which starts processing self-reset operations when the pulse is generated. Therefore, 1-bit output is realized for each stage of TDI signal processing circuit. The pulse signal is easier to accumulate in the digital accumulator. With a high line rate of 100 KHz, SNR improvement of the proposed sensor is 24.15 dB and the energy consumption of the sensor is 0.44 nJ/pixel.

The Isotopx NGX and ATONA Faraday amplifiers

Abstract. We installed the new Isotopx ATONA Faraday cup detector amplifiers on an Isotopx NGX mass spectrometer at Lamont-Doherty Earth Observatory in early 2018. The ATONA is a capacitive transimpedance amplifier, which differs from the traditional resistive transimpedance amplifier used on most Faraday detectors for mass spectrometry. Instead of a high-gain resistor, a capacitor is used to accumulate and measure charge. The advantages of this architecture are a very low noise floor, rapid response time, stable baselines, and very high dynamic range. We show baseline noise measurements and measurements of argon from air and cocktail gas standards to demonstrate the capabilities of these amplifiers. The ATONA exhibits a noise floor better than a traditional 1013 Ω amplifier in normal noble gas mass spectrometer usage, superior gain and baseline stability, and an unrivaled dynamic range that makes it practical to measure beams ranging in size from below 10−16 to above 10−9 A using a single amplifier.

A Capacitive Feedback Transimpedance Amplifier with a DC Feedback Loop Using a Transistor for High DC Dynamic Range

This study proposes a capacitive feedback transimpedance amplifier (CF-TIA) using a transistor in the direct current (DC) feedback loop for high DC dynamic range. In some applications, the background DC input can vary widely from the minimum to the maximum, and TIA have to sense the target signal even on the top of the maximum DC input. In a conventional CF-TIA, however, the allowable DC input is constrained by the value of the resistor in the DC feedback loop. To allow a fairly high DC input, the resistor is set to a very low value. This causes the thermal noise current to increase significantly. The increased thermal noise is always present even in the minimum DC input, thus degrading the overall noise performance. The circuit proposed herein overcomes this shortcoming by using the transistor instead of the resistor. The adverse effect of the parasitic capacitance of the transistor on system stability is compensated for as well. Then, the analyses of the overall frequency response and design parameters, including the cut-off frequency and attenuation ratio associated with system stability, are presented for the proposed circuit. In addition, in order to cope with the problem that stability is dependent on the amount of DC input, a simple method for ensuring system stability regardless of DC component value is introduced. The presented analyses and the method are generalized for all CF-TIA applications.

PIN photodiode-based active pixel for a near-infrared imaging application in 0.35-μm CMOS

We present an active pixel for a spectral domain optical coherence tomography sensor on a chip, where optical components are realized in a photonic layer and monolithically integrated with the electronics, whereby light is brought to the pixels using waveguides. The core of the pixel is an amplifier with capacitive feedback (so-called capacitive transimpedance amplifier), apart from that, a correlated double sampling circuit is implemented within the pixel. The proposed active pixel is based on a PIN photodiode and fabricated in 0.35-μm high-voltage CMOS technology. We use three different epitaxial starting material thicknesses (20, 30, and 40 μm) in order to find the device with best performance. The pixel is optimized for high efficiency in a spectral range between 800 and 900 nm. We explain advantages in the spectral responsivity and crosstalk of this pixel over conventional p / n photodiode-based pixels in standard CMOS processes and over the pinned photodiode-based pixel. We also present measured pixel parameters and give comparison with prior work.